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authorukw2011-09-12 10:02:26 +0000
committerukw2011-09-12 10:02:26 +0000
commit476267f4e9854c75c890799df29225e61623c3cc (patch)
tree2372f195b08c708708854ad7ea1f3bad638c7eae
parent2b27d37bdb090a10a5f3bc6175984aafbe146035 (diff)
downloadirmp-476267f4e9854c75c890799df29225e61623c3cc.zip
version 2.0.0-pre7: added support for ATtiny84, added ISR in main.c, corrected timer1_init() for ATTiny85, added NEC16 & NEC42 for IRSND.
git-svn-id: svn://mikrocontroller.net/irmp@80 aeb2e35e-bfc4-4214-b83c-9e8de998ed28
-rw-r--r--irmp.c3
-rw-r--r--irsnd.c7
-rw-r--r--irsndmain.c16
-rw-r--r--main.c2
4 files changed, 15 insertions, 13 deletions
diff --git a/irmp.c b/irmp.c
index 13e7a1e..208e22d 100644
--- a/irmp.c
+++ b/irmp.c
@@ -9,7 +9,8 @@
*
* Supported mikrocontrollers:
*
- * ATtiny84, ATtiny85
+ * ATtiny45, ATtiny85
+ * ATtiny84
* ATmega8, ATmega16, ATmega32
* ATmega162
* ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284
diff --git a/irsnd.c b/irsnd.c
index 47bea6c..a7b3b6a 100644
--- a/irsnd.c
+++ b/irsnd.c
@@ -5,7 +5,8 @@
*
* Supported mikrocontrollers:
*
- * ATtiny84, ATtiny85
+ * ATtiny45, ATtiny85
+ * ATtiny84
* ATmega8, ATmega16, ATmega32
* ATmega162
* ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284
@@ -72,7 +73,7 @@ typedef unsigned short uint16_t;
* ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B
*---------------------------------------------------------------------------------------------------------------------------------------------------
*/
-#if defined (__AVR_ATtiny84__) // ATtiny85 uses OC0A = PB2 or OC0B = PA7
+#if defined (__AVR_ATtiny84__) // ATtiny84 uses OC0A = PB2 or OC0B = PA7
#if IRSND_OCx == IRSND_OC0A // OC0A
#define IRSND_PORT PORTB // port B
#define IRSND_DDR DDRB // ddr B
@@ -85,7 +86,7 @@ typedef unsigned short uint16_t;
#error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
#endif // IRSND_OCx
-#elif defined (__AVR_ATtiny85__) // ATtiny85 uses OC0A = PB0 or OC0B = PB1
+#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1
#if IRSND_OCx == IRSND_OC0A // OC0A
#define IRSND_PORT PORTB // port B
#define IRSND_DDR DDRB // ddr B
diff --git a/irsndmain.c b/irsndmain.c
index 213a4f8..ff4838c 100644
--- a/irsndmain.c
+++ b/irsndmain.c
@@ -30,18 +30,18 @@
void
timer1_init (void)
{
-#if defined (__AVR_ATtiny85__) // ATtiny85:
- OCR1A = (F_CPU / (2 * F_INTERRUPTS) / 2) - 1; // compare value: 1/28800 of CPU frequency, presc = 2
- TCCR1 = (1 << CTC1) | (1 << CS11); // switch CTC Mode on, set prescaler to 2
-#else // ATmegaXX:
- OCR1A = (F_CPU / (2 * F_INTERRUPTS)) - 1; // compare value: 1/28800 of CPU frequency
- TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1
+#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:
+ OCR1A = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4
+ TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4
+#else // ATmegaXX:
+ OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency
+ TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1
#endif
#ifdef TIMSK1
- TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare
+ TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare
#else
- TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare
+ TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare
#endif
}
diff --git a/main.c b/main.c
index 589bb88..44fe1bb 100644
--- a/main.c
+++ b/main.c
@@ -32,7 +32,7 @@
void
timer1_init (void)
{
-#if defined (__AVR_ATtiny85__) // ATtiny85:
+#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:
OCR1A = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4
TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4
#else // ATmegaXX: