diff options
Diffstat (limited to 'main.c')
| -rw-r--r-- | main.c | 93 |
1 files changed, 66 insertions, 27 deletions
@@ -3,11 +3,12 @@ *
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
*
- * $Id: main.c,v 1.15 2012/11/18 17:51:26 fm Exp $
+ * $Id: main.c,v 1.16 2012/12/06 08:49:33 fm Exp $
*
- * ATMEGA88 @ 8 MHz
+ * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)
*
- * Fuses: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9
+ * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9
+ * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,6 +23,12 @@ #error F_CPU unkown
#endif
+/*---------------------------------------------------------------------------------------------------------------------------------------------------
+ * ATMEL AVR part:
+ *---------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+#if defined (ATMEL_AVR)
+
void
timer1_init (void)
{
@@ -35,59 +42,89 @@ timer1_init (void) TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4
#endif
-#elif defined(STELLARIS_ARM_CORTEX_M4)
- SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
- TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);
-
- TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);
- IntEnable(INT_TIMER1A);
- TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
- TimerEnable(TIMER1_BASE, TIMER_A);
- // Important: Timer1IntHandler has to be configured in startup_ccs.c !
#else // ATmegaXX:
OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency
TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1
#endif
-#if (!defined(STELLARIS_ARM_CORTEX_M4))
-# ifdef TIMSK1
+#ifdef TIMSK1
TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare
-# else
+#else
TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare
-# endif
#endif
}
-/*---------------------------------------------------------------------------------------------------------------------------------------------------
- * Timer 1 output compare A interrupt service routine, called every 1/15000 sec
- *---------------------------------------------------------------------------------------------------------------------------------------------------
- */
#ifdef TIM1_COMPA_vect // ATtiny84
-ISR(TIM1_COMPA_vect)
-#elif defined(STELLARIS_ARM_CORTEX_M4)
-void Timer1IntHandler(void)
+#define COMPA_VECT TIM1_COMPA_vect
#else
-ISR(TIMER1_COMPA_vect)
+#define COMPA_VECT TIMER1_COMPA_vect // ATmega
#endif
+
+ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec
{
(void) irmp_ISR(); // call irmp ISR
// call other timer interrupt routines...
}
+int
+main (void)
+{
+ IRMP_DATA irmp_data;
+
+ irmp_init(); // initialize irmp
+ timer1_init(); // initialize timer1
+ sei (); // enable interrupts
+
+ for (;;)
+ {
+ if (irmp_get_data (&irmp_data))
+ {
+ // ir signal decoded, do something here...
+ // irmp_data.protocol is the protocol, see irmp.h
+ // irmp_data.address is the address/manufacturer code of ir sender
+ // irmp_data.command is the command code
+ // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)
+ }
+ }
+}
+
+/*---------------------------------------------------------------------------------------------------------------------------------------------------
+ * LM4F120 Launchpad (ARM Cortex M4):
+ *---------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+
+void
+timer1_init (void)
+{
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
+ TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);
+
+ TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);
+ IntEnable(INT_TIMER1A);
+ TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
+ TimerEnable(TIMER1_BASE, TIMER_A);
+ // Important: Timer1IntHandler has to be configured in startup_ccs.c !
+}
+
+void
+Timer1IntHandler(void) // Timer1 Interrupt Handler
+{
+ (void) irmp_ISR(); // call irmp ISR
+ // call other timer interrupt routines...
+}
int
main (void)
{
IRMP_DATA irmp_data;
-#if defined(STELLARIS_ARM_CORTEX_M4)
ROM_FPUEnable();
ROM_FPUStackingEnable();
ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
-#endif
irmp_init(); // initialize irmp
- timer1_init(); // initialize timer 1
+ timer1_init(); // initialize timer1
sei (); // enable interrupts
for (;;)
@@ -102,3 +139,5 @@ main (void) }
}
}
+
+#endif
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