diff options
| author | Leo C | 2015-04-28 21:48:28 +0200 |
|---|---|---|
| committer | Leo C | 2015-04-28 21:48:28 +0200 |
| commit | 296050043a19ee9b18c850dad01cc36ee64bd7b0 (patch) | |
| tree | 7072f565cdcfbf43911875cd75e4d9f38b82a036 /z180/config.inc | |
| parent | 4cbc8d3ed4e0d5624872ead9f8519b1cea8cf5ac (diff) | |
| download | z180-stamp-296050043a19ee9b18c850dad01cc36ee64bd7b0.zip | |
Integrate changes from z80-support branch
Diffstat (limited to 'z180/config.inc')
| -rw-r--r-- | z180/config.inc | 57 |
1 files changed, 51 insertions, 6 deletions
diff --git a/z180/config.inc b/z180/config.inc index 9cef051..390d3bc 100644 --- a/z180/config.inc +++ b/z180/config.inc @@ -1,7 +1,17 @@ +;-----------------------------------------------------
+; CPU and BANKING types
+
+CPU_Z180 equ 1 ; 0 = Z80, else Z180
+ROMSYS equ 0
-FOSC equ 9216 ;Oscillator frequency [KHz]
-PHI equ FOSC*2 ;CPU frequency
+AVRCLK equ 18432 ;[KHz]
+
+ if CPU_Z180
+
+;-----------------------------------------------------
+FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]
+PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)
;-----------------------------------------------------
; Programmable Reload Timer (PRT)
@@ -27,15 +37,50 @@ BANKS equ 18 ;max nr. of banks CREFSH equ 0 ;Refresh rate register (disable refresh)
CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States
-
-ROMSYS equ 0
+ else ; Z80
+
+PHI equ AVRCLK/5 ;CPU frequency [KHz]
+BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]
+;BDCLK16 equ
+
+SIOAD EQU 0bch
+SIOAC EQU 0bdh
+SIOBD EQU 0beh
+SIOBC EQU 0bfh
+
+CTC0 EQU 0f4h
+CTC1 EQU 0f5h
+CTC2 EQU 0f6h
+CTC3 EQU 0f7h
+
+;
+; Init Serial I/O for console input and output (SIO-A)
+;
+; Baudrate clock: 1843200 Hz (Bus connector pin A17)
+;
+; Baudrate Divider SIO CTC
+; ---------------------------------
+; 115200 16 16 1
+; 57600 32 16 2
+; 38400 48 16 3
+; 19200 96 16 6
+; 9600 192 16 12
+; 4800 384 16 24
+; 2400 768 16 48
+; 1200 1536 16 96
+; 600 3072 16 192
+; 300 6144 64 92
+
+ endif ; CPU_Z180
if ROMSYS
c$rom equ 0a5h
ROM_EN equ 0C0h
ROM_DIS equ ROMEN+1
+ if CPU_Z180
CWAITROM equ 2 shl MWI0
endif
+ endif
DRSTNUM equ 30h ;DDTZ Restart vector (breakpoints)
@@ -50,8 +95,8 @@ co.fifo_len equ 256 s1.rx_len equ 256 ;Serial 1 (ASCI1) buffers
s1.tx_len equ 256 ;
-AVRINT5 equ 40h
-AVRINT6 equ 50h
+AVRINT5 equ 4Fh
+AVRINT6 equ 5Fh
;PMSG equ 80h
;-----------------------------------------------------
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