summaryrefslogtreecommitdiff
path: root/z180/z180reg.inc
diff options
context:
space:
mode:
authorLeo C2014-09-05 11:45:31 +0200
committerLeo C2014-09-05 11:45:31 +0200
commit815c173542f40f3bcfac050831454d86633b555a (patch)
treeabb5d9c74ee3d51f4b5511c54357087ad3143da9 /z180/z180reg.inc
parent04cffff06efa61b5300105d0db98c0f4fbfa8d47 (diff)
downloadz180-stamp-815c173542f40f3bcfac050831454d86633b555a.zip
Enable X2 Clock Multiplier, disable Clock Divider
Diffstat (limited to 'z180/z180reg.inc')
-rw-r--r--z180/z180reg.inc9
1 files changed, 5 insertions, 4 deletions
diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 616138c..5bbd088 100644
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -51,10 +51,10 @@ stat1 equ IOBASE+05h ;ASCI Status Channel 1
b2m TDRE,1 ;Transmit Data Register Empty
b2m TIE,0 ;Transmit Interrupt Enable
-tdr0 equ IOBASE+06h ;ASCI Transmit Data
-tdr1 equ IOBASE+07h ;ASCI Transmit Data
-rdr0 equ IOBASE+08h ;ASCI Receive Data
-rdr1 equ IOBASE+09h ;ASCI Receive Data
+tdr0 equ IOBASE+06h ;ASCI Transmit Data
+tdr1 equ IOBASE+07h ;ASCI Transmit Data
+rdr0 equ IOBASE+08h ;ASCI Receive Data
+rdr1 equ IOBASE+09h ;ASCI Receive Data
cntr equ IOBASE+0Ah ;CSI/O Control Register
trdr equ IOBASE+0Bh ;CSI/O Transmit/Receive Data Register
@@ -94,6 +94,7 @@ cmr equ IOBASE+1Eh ;Clock Mutiplier Register
b2m LNC,6 ;Low Noise Crystal
ccr equ IOBASE+1Fh ;CPU Control Register
+ b2m NCD 7 ;No Clock Divide
sar0l equ IOBASE+20h ;DMA Src Adr Register Channel 0
sar0h equ IOBASE+21h ;