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Diffstat (limited to 'Z180/z180reg.inc')
| -rw-r--r-- | Z180/z180reg.inc | 190 |
1 files changed, 190 insertions, 0 deletions
diff --git a/Z180/z180reg.inc b/Z180/z180reg.inc new file mode 100644 index 0000000..616138c --- /dev/null +++ b/Z180/z180reg.inc @@ -0,0 +1,190 @@ + .xlist
+
+;;
+;; HD64180/Z180 Register Definitions
+;;
+
+
+b2m macro name,nr
+name equ nr
+M_&name equ 1 shl nr
+ endm
+
+; ifndef IOBASE
+IOBASE equ 0
+; endif
+
+cntla0 equ IOBASE+00h ;ASCI Control Register A Channel 0
+cntla1 equ IOBASE+01h ;ASCI Control Register A Channel 1
+ b2m MPE, 7 ;Multi-Processor Mode Enable
+ b2m RE, 6 ;Receiver Enable
+ b2m TE, 5 ;Transmitter Enable
+ b2m RTS0, 4 ;Request to Send Channel 0
+ b2m CKA1D, 4 ;
+ b2m MPBR, 3 ;Multiprocessor Bit Receive (Read)
+ b2m EFR, 3 ;Error Flag Reset (Write)
+ b2m MOD2, 2 ;Data Format Mode 1 = 8-Bit data
+ b2m NOD1, 1 ;1 = Parity enabled
+ b2m MOD0, 0 ;1 = 2 stop bits
+
+cntlb0 equ IOBASE+02h ;ASCI Control Register B Channel 0
+cntlb1 equ IOBASE+03h ;ASCI Control Register B Channel 1
+ b2m MPBT,7 ;Multiprocessor Bit Transmit
+ b2m MP,6 ;Multiprocessor Mode
+ b2m CTS,5 ;Clear to Send
+ b2m PS,5 ;Prescale
+ b2m PEO,4 ;Parity Even Odd
+ b2m DR,3 ;Divede Ratio
+ b2m SS2,2 ;Source/Speed Select 2,1,0
+ b2m SS1,1 ;
+ b2m SS0,0 ;
+
+stat0 equ IOBASE+04h ;ASCI Status Channel 0
+stat1 equ IOBASE+05h ;ASCI Status Channel 1
+ b2m RDRF,7 ;Receive Data Register Full
+ b2m OVRN,6 ;Overrun Error
+ b2m PERR,5 ;Parity Error (M80: PE conflicts with JP/CALL cc)
+ b2m FE,4 ;Framing Error
+ b2m RIE,3 ;Receive Interrupt Enable
+ b2m DCD0,2 ;Data Carrier Detect (Ch 0)
+ b2m CTS1E,2 ;Clear To Send (Ch 1)
+ b2m TDRE,1 ;Transmit Data Register Empty
+ b2m TIE,0 ;Transmit Interrupt Enable
+
+tdr0 equ IOBASE+06h ;ASCI Transmit Data
+tdr1 equ IOBASE+07h ;ASCI Transmit Data
+rdr0 equ IOBASE+08h ;ASCI Receive Data
+rdr1 equ IOBASE+09h ;ASCI Receive Data
+
+cntr equ IOBASE+0Ah ;CSI/O Control Register
+trdr equ IOBASE+0Bh ;CSI/O Transmit/Receive Data Register
+
+tmdr0l equ IOBASE+0Ch ;Timer Data Register Channel 0
+tmdr0h equ IOBASE+0Dh ;
+rldr0l equ IOBASE+0Eh ;Timer Reload Register Channel 0
+rldr0h equ IOBASE+0Fh ;
+tcr equ IOBASE+10h ;Timer Control Register
+ b2m TIF1,7 ;Timer Interrupt Flag
+ b2m TIF0,6 ;
+ b2m TIE1,5 ;Timer Interrupt Enable
+ b2m TIE0,4 ;
+ b2m TOC1,3 ;Timer Output Control
+ b2m TOC0,2 ;
+ b2m TDE1,1 ;Timer Down Count Enable
+ b2m TDE0,0 ;
+
+
+asext0 equ IOBASE+12h ;ASCI Extension Control Register
+asext1 equ IOBASE+13h ;ASCI Extension Control Register
+
+tmdr1l equ IOBASE+14h ;Timer Data Register Channel 1
+tmdr1h equ IOBASE+15h ;
+rldr1l equ IOBASE+16h ;Timer Reload Register Channel 1
+rldr1h equ IOBASE+17h ;
+
+frc equ IOBASE+18h ;Free Running Counter
+
+astc0l equ IOBASE+1Ah ;ASCI Time Constant Register 0
+astc0h equ IOBASE+1Bh ;
+astc1l equ IOBASE+1Ch ;ASCI Time Constant Register 1
+astc1h equ IOBASE+1Dh ;
+
+cmr equ IOBASE+1Eh ;Clock Mutiplier Register
+ b2m X2CM,7 ;X2 Clock Multiplier
+ b2m LNC,6 ;Low Noise Crystal
+
+ccr equ IOBASE+1Fh ;CPU Control Register
+
+sar0l equ IOBASE+20h ;DMA Src Adr Register Channel 0
+sar0h equ IOBASE+21h ;
+sar0b equ IOBASE+22h ;
+dar0l equ IOBASE+23h ;DMA Dst Adr Register Channel 0
+dar0h equ IOBASE+24h ;
+dar0b equ IOBASE+25h ;
+bcr0l equ IOBASE+26h ;DMA Byte Count Register Channel 0
+bcr0h equ IOBASE+27h ;
+
+mar1l equ IOBASE+28h ;DMA Memory Address Register Channel 1
+mar1h equ IOBASE+29h ;
+mar1b equ IOBASE+2Ah ;
+iar1l equ IOBASE+2Bh ;DMA I/O Address Register Channel 1
+iar1h equ IOBASE+2Ch ;
+iar1b equ IOBASE+2Dh ;
+ b2m ALTE,7 ;Alternating Chnnels
+ b2m ALTC,6 ;Currently selected DMA Channel when Bit7=1
+ b2m REQ1SEL2,2 ;
+ b2m REQ1SEL1,1 ;
+ b2m REQ1SEL0,0 ;
+
+bcr1l equ IOBASE+2Eh ;DMA Byte Count Register Channel 1
+bcr1h equ IOBASE+2Fh ;
+
+dstat equ IOBASE+30h ;DMA Status Register
+ b2m DE1,7 ;DMA enable ch 1,0
+ b2m DE0,6 ;
+ b2m DWE1,5 ;DMA Enable Bit Write Enable 1,0
+ b2m DWE0,4 ;
+ b2m DIE1,3 ;DMA Interrupt Enable 1,0
+ b2m DIE0,2 ;
+ b2m DME,0 ;DMA Master enable
+
+dmode equ IOBASE+31h ;DMA Mode Register
+ b2m DM1,5 ;Ch 0 Destination Mode 1,0
+ b2m DM0,4 ;
+ b2m SM1,3 ;Ch 0 Source Mode 1,0
+ b2m SM0,2 ;
+ b2m MMOD,1 ;Memory MODE select (0=cycle steel/1=burst)
+
+dcntl equ IOBASE+32h ;DMA/WAIT Control
+ b2m MWI1,7 ;Memory Wait Insertion
+ b2m MWI0,6 ;
+ b2m IWI1,5 ;I/O Wait Insertion
+ b2m IWI0,4 ;
+ b2m DMS1,3 ;DREQi Select (Edge/Level)
+ b2m DMS0,2 ;
+ b2m DIMA1,1 ;DMA Ch1 I/O Memory Mode Select
+ b2m DIMA0,0
+M_MWI equ M_MWI1 + M_MWI0
+M_IWI equ M_IWI1 + M_IWI0
+
+il equ IOBASE+33h ;Interrupt Vector Low Register
+itc equ IOBASE+34h ;INT/TRAP Control Register
+ b2m TRAP,7 ;Trap
+ b2m UFO,6 ;Unidentified Fetch Object
+ b2m ITE2,2 ;/INT Enable 2,1,0
+ b2m ITE1,1 ;
+ b2m ITE0,0 ;
+
+rcr equ IOBASE+36h ;Refresh Control Register
+ b2m REFE,7 ;Refresh Enable
+ b2m REFW,6 ;Refresh Wait State
+ b2m CYC1,1 ;Cycle select
+ b2m CYC0,0 ;
+
+cbr equ IOBASE+38h ;MMU Common Base Register
+bbr equ IOBASE+39h ;MMU Bank Base Register
+cbar equ IOBASE+3Ah ;MMU Common/Bank Register
+
+omcr equ IOBASE+3Eh ;Operation Mode Control Register
+ b2m M1E,7 ;M1 Enable
+ b2m M1TE,6 ;M1 Temporary Enable
+ b2m IOC,5 ;I/O Compatibility
+
+icr equ IOBASE+3Fh ;I/O Control Register
+ b2m IOSTP,5 ;I/O Stop
+;
+; Interrupt Vectors
+;
+
+IV$INT1 equ 0 ;/INT1 (highest priority)
+IV$INT2 equ 2 ;/INT2
+IV$PRT0 equ 4 ;PRT channel 0
+IV$PRT1 equ 6 ;PRT channel 1
+IV$DMA0 equ 8 ;DMA channel 0
+IV$DMA1 equ 10 ;DMA channel 1
+IV$CSIO equ 12 ;CSI/O
+IV$ASCI0 equ 14 ;ASCI channel 0
+IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)
+
+ .list
+
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