diff options
Diffstat (limited to 'avr/z80-if.c')
-rw-r--r-- | avr/z80-if.c | 127 |
1 files changed, 54 insertions, 73 deletions
diff --git a/avr/z80-if.c b/avr/z80-if.c index 955a61a..207aed1 100644 --- a/avr/z80-if.c +++ b/avr/z80-if.c @@ -95,6 +95,7 @@ struct bits { #define BUSREQ 7 #define DDR_BUSREQ DDRD #define P_BUSACK PORTD +#define PIN_BUSACK PIND #define BUSACK 6 #define DDR_BUSACK DDRD //#define P_HALT PORTA @@ -117,8 +118,8 @@ struct bits { #define P_ADH PORTC #define P_ADB PORTE #define PIN_ADB PINE -#define DDR_ADL DDRE -#define DDR_ADH DDRE +#define DDR_ADL DDRA +#define DDR_ADH DDRC #define DDR_ADB DDRE #define ADB_WIDTH 3 @@ -126,49 +127,16 @@ struct bits { //#define ADB_PORT PORTE - -#define ADp1_OFS 0 -#define ADp1_WIDTH 8 -#define ADp1_SHIFT 1 -#define ADp1_PORT GPIOA - -#define ADp2_OFS ADp1_WIDTH -#define ADp2_WIDTH 8 -#define ADp2_SHIFT 0 -#define ADp2_PORT GPIOC - -#define ADp3_OFS (ADp2_OFS+ADp2_WIDTH) -#define ADp3_WIDTH 3 -#define ADp3_SHIFT 10 -#define ADp3_PORT GPIOC - -#define ADunbuff1_WIDTH 1 -#define ADunbuff1_SHIFT 8 -#define ADunbuff1_PORT GPIOA - -#define ADunbuff2_WIDTH 2 -#define ADunbuff2_SHIFT 6 -#define ADunbuff2_PORT GPIOC - -#define ADunbuff3_WIDTH 3 -#define ADunbuff3_SHIFT 10 -#define ADunbuff3_PORT GPIOC - -#define DB_OFS 0 -#define DB_WIDTH 8 -#define DB_SHIFT 8 -#define DB_PORT GPIOB - - #define Z80_O_MREQ SBIT(P_MREQ, 4) #define Z80_O_RD SBIT(P_RD, 3) #define Z80_O_WR SBIT(P_WR, 2) #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7) //#define Z80_O_NMI SBIT(P_NMI, ) #define Z80_O_RST SBIT(P_RST, 5) -#define Z80_I_BUSACK SBIT(P_BUSACK, 6) +#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6) //#define Z80_I_HALT SBIT(P_HALT, ) + void z80_busreq(level_t level) { Z80_O_BUSREQ = level; @@ -210,25 +178,31 @@ typedef union { /*--------------------------------------------------------------------------*/ - -/* - * A0..A6, A8..A13 are buffered. No need to disable. - * A7, A14..A18: set to input. - */ - -static void z80_setup_adrbus_tristate(void) +static void z80_setup_addrbus_tristate(void) { + /* /MREQ, /RD, /WR: Input, no pullup */ + DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR)); + Z80_O_MREQ = 0; + Z80_O_RD = 0; + Z80_O_WR = 0; + P_ADL = 0; DDR_ADL = 0; P_ADH = 0; DDR_ADH = 0; - PIN_ADB = P_ADB & MASK(ADB_WIDTH) << ADB_SHIFT; + PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); } -static void z80_setup_adrbus_active(void) +static void z80_setup_addrbus_active(void) { + /* /MREQ, /RD, /WR: Output and high */ + Z80_O_MREQ = 1; + Z80_O_RD = 1; + Z80_O_WR = 1; + DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); + DDR_ADL = 0xff; DDR_ADH = 0xff; DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT); @@ -247,66 +221,66 @@ static void z80_setup_dbus_out(void) DDR_DB = 0xff; } -static -void z80_setaddress(uint32_t addr) -{ - addr_t x; x.l = addr; - - P_ADL = x.b[0]; - P_ADH = x.b[1]; - PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ; -} - void z80_setup_bus(void) { + /* /ZRESET: Output and low */ Z80_O_RST = 0; DDR_RST |= _BV(RST); + /* /BUSREQ: Output and high */ Z80_O_BUSREQ = 1; DDR_BUSREQ |= _BV(BUSREQ); -// Z80_O_NMI = 1; -// DDR_NMI |= _BV(NMI); - - Z80_O_MREQ = 1; - Z80_O_RD = 1; - Z80_O_WR = 1; - DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); - + /* /BUSACK: Input, no pullup */ DDR_BUSACK &= ~_BV(BUSACK); P_BUSACK &= ~_BV(BUSACK); + /* /IOCS1: Input, no pullup */ DDR_IOCS1 &= ~_BV(IOCS1); P_IOCS1 &= ~_BV(IOCS1); - //Z80_O_BUSREQ = 0; - //while(Z80_I_BUSACK == 1); - - z80_setup_adrbus_tristate(); + z80_setup_addrbus_tristate(); z80_setup_dbus_in(); } +/*--------------------------------------------------------------------------*/ + void z80_request_bus(void) { Z80_O_BUSREQ = 0; while(Z80_I_BUSACK == 1); - z80_setup_adrbus_active(); + z80_setup_addrbus_active(); } void z80_release_bus(void) { z80_setup_dbus_in(); - z80_setup_adrbus_tristate(); + z80_setup_addrbus_tristate(); Z80_O_BUSREQ = 1; - while(Z80_I_BUSACK == 0); + //while(Z80_I_BUSACK == 0); +} + +/*--------------------------------------------------------------------------*/ + +static +//inline __attribute__ ((always_inline)) +void z80_setaddress(uint32_t addr) +{ + addr_t x; x.l = addr; + + P_ADL = x.b[0]; + P_ADH = x.b[1]; + PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ; } void z80_write(uint32_t addr, uint8_t data) { z80_setaddress(addr); Z80_O_MREQ = 0; - P_DB = data; z80_setup_dbus_out(); + P_DB = data; + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; Z80_O_MREQ = 1; @@ -321,6 +295,7 @@ uint8_t z80_read(uint32_t addr) z80_setup_dbus_in(); Z80_O_RD = 0; Z80_O_RD = 0; + Z80_O_RD = 0; data = PIN_DB; Z80_O_RD = 1; Z80_O_MREQ = 1; @@ -336,13 +311,15 @@ void z80_memset(uint32_t addr, uint8_t data, uint32_t length) while(length--) { z80_setaddress(addr++); P_DB = data; + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; } Z80_O_MREQ = 1; } -void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) +void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; @@ -352,6 +329,8 @@ void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) z80_setaddress(dest++); data = *src++; P_DB = data; + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; } @@ -547,6 +526,7 @@ int z80_msg_fifo_getc(void) { int c = -1; +#if 0 if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) { c = msg_fifo.buf[msg_fifo.count]; if (++msg_fifo.count == NELEMS(msg_fifo.buf)) @@ -558,6 +538,7 @@ int z80_msg_fifo_getc(void) z80_release_bus(); } } +#endif return c; } |