diff options
Diffstat (limited to 'stm32/z80-if.c')
| -rw-r--r-- | stm32/z80-if.c | 66 |
1 files changed, 36 insertions, 30 deletions
diff --git a/stm32/z80-if.c b/stm32/z80-if.c index 171fea9..6c415d1 100644 --- a/stm32/z80-if.c +++ b/stm32/z80-if.c @@ -1,3 +1,9 @@ +/* + * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + /** * * Pin assignments @@ -111,8 +117,8 @@ AFIO_MAPR_SPI1_REMAP AFIO_MAPR2 = -AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees -AFIO_MAPR_SPI1_REMAP +AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees +AFIO_MAPR_SPI1_REMAP */ @@ -220,7 +226,7 @@ AFIO_MAPR_SPI1_REMAP #define IOFIELD_GET(src, width, shift) \ ((src>>shift) & MASK(width)) - + #define CNF_MODE_I_F (GPIO_CNF_INPUT_FLOAT<<2 |GPIO_MODE_INPUT) #define CNF_MODE_O_PP (GPIO_CNF_OUTPUT_PUSHPULL<<2 | GPIO_MODE_OUTPUT_10_MHZ) @@ -249,16 +255,16 @@ static void tim16_setup(void) { RCC_APB2RSTR |= RCC_APB2RSTR_TIM16RST; RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM16RST; - + TIM16_BDTR = TIM_BDTR_MOE; - + TIM16_CCMR1 = 0 - | TIM_CCMR1_OC1M_FORCE_LOW + | TIM_CCMR1_OC1M_FORCE_LOW | TIM_CCMR1_CC1S_OUT; - + TIM16_CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP; - + TIM16_ARR = 48; /* default */ TIM16_CCR1 = 1; /* */ } @@ -268,7 +274,7 @@ static void tim16_setup(void) static void tim16_set(int mode) { uint16_t cc_mode; - + cc_mode = TIM_CCMR1_CC1S_OUT; TIM16_CR1 = TIM_CR1_OPM; @@ -281,9 +287,9 @@ static void tim16_set(int mode) TIM16_ARR = mode; cc_mode |= TIM_CCMR1_OC1M_PWM2; } - + TIM16_CCMR1 = cc_mode; - + if (mode > 0) TIM16_CR1 |= TIM_CR1_CEN; } @@ -292,44 +298,44 @@ static void tim16_set(int mode) -/* +/* * A0..A6, A8..A13 are buffered. No need to disable. * A7, A14..A18: set to input. */ - + static void z80_setup_adrbus_tristate(void) { #if 0 gpio_set_mode(ADunbuff1_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, MASK(ADunbuff1_WIDTH) << ADunbuff1_SHIFT); - gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, + gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, (MASK(ADunbuff2_WIDTH) << ADunbuff2_SHIFT) | (MASK(ADunbuff3_WIDTH) << ADunbuff3_SHIFT)); #else - GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) + GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) | (CNF_MODE_I_F << (4 * 0)); GPIO_CRL(GPIOC) = (GPIO_CRL(GPIOC) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7)))) | ((CNF_MODE_I_F << (4 * 6)) | (CNF_MODE_I_F << (4 * 7))); GPIO_CRH(GPIOC) = (GPIO_CRH(GPIOC) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4)))) | ((CNF_MODE_I_F << (4*2)) | (CNF_MODE_I_F << (4*3)) | (CNF_MODE_I_F << (4*4))); -#endif +#endif } - + static void z80_setup_adrbus_active(void) { #if 0 gpio_set_mode(ADunbuff1_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, MASK(ADunbuff1_WIDTH) << ADunbuff1_SHIFT); - gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, + gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, (MASK(ADunbuff2_WIDTH) << ADunbuff2_SHIFT) | (MASK(ADunbuff3_WIDTH) << ADunbuff3_SHIFT)); #else - GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) + GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) | (CNF_MODE_O_PP << (4 * 0)); GPIO_CRL(GPIOC) = (GPIO_CRL(GPIOC) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7)))) | ((CNF_MODE_O_PP << (4 * 6)) | (CNF_MODE_O_PP << (4 * 7))); GPIO_CRH(GPIOC) = (GPIO_CRH(GPIOC) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4)))) | ((CNF_MODE_O_PP << (4*2)) | (CNF_MODE_O_PP << (4*3)) | (CNF_MODE_O_PP << (4*4))); -#endif +#endif } @@ -402,9 +408,9 @@ void z80_release_bus(void) void z80_reset(level_t level) { int x = level ? -1 : 0; - + tim16_set(x); - + // Z80_O_RST = level; } @@ -469,7 +475,7 @@ void z80_memset(uint32_t addr, uint8_t data, int length) void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; - + z80_setup_dbus_out(); Z80_O_ME = 0; while(length--) { @@ -488,7 +494,7 @@ void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) 017B' rx.out_idx: ds 1 ; 017C' rx.buf: ds rx.buf_len ; 018B' rx.buf_end equ $-1 ; last byte (start+len-1) - + 018C' tx.bs_mask: ds 1 ; (buf_len - 1) 018D' tx.in_idx: ds 1 ; 018E' tx.out_idx: ds 1 ; @@ -517,7 +523,7 @@ static struct { idx_in, mask; } fifo_dsc[NUM_FIFOS]; - + void z80_memfifo_init(const fifo_t f, uint32_t adr) { @@ -557,7 +563,7 @@ int z80_memfifo_is_empty(const fifo_t f) int z80_memfifo_is_full(const fifo_t f) { int rc = 1; - + if (fifo_dsc[f].base != 0) { z80_request_bus(); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) @@ -570,7 +576,7 @@ int z80_memfifo_is_full(const fifo_t f) uint8_t z80_memfifo_getc(const fifo_t f) { uint8_t rc, idx; - + while (z80_memfifo_is_empty(f)) ; @@ -580,7 +586,7 @@ uint8_t z80_memfifo_getc(const fifo_t f) fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); z80_release_bus(); - + return rc; } @@ -588,7 +594,7 @@ uint8_t z80_memfifo_getc(const fifo_t f) void z80_memfifo_putc(fifo_t f, uint8_t val) { int idx; - + while (z80_memfifo_is_full(f)) ; @@ -714,7 +720,7 @@ DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); int z80_msg_fifo_getc(void) { int c = -1; - + if (msg_fifo.count != (NELEMS(msg_fifo.buf) - DMA1_CNDTR4)) { c = msg_fifo.buf[msg_fifo.count]; if (++msg_fifo.count == NELEMS(msg_fifo.buf)) |