From 35edb766593d019b89a3f40b6d6cdd2b50f18032 Mon Sep 17 00:00:00 2001 From: Leo C Date: Tue, 16 Dec 2014 16:03:06 +0100 Subject: Add copyright notice --- stm32/debug.h | 5 ++++ stm32/serial.c | 5 ++-- stm32/serial.h | 6 ++++ stm32/z180-stamp-stm32.c | 71 +++++++++++++++++++++++++----------------------- stm32/z80-if.c | 66 ++++++++++++++++++++++++-------------------- stm32/z80-if.h | 5 ++++ 6 files changed, 91 insertions(+), 67 deletions(-) (limited to 'stm32') diff --git a/stm32/debug.h b/stm32/debug.h index d542317..692c879 100644 --- a/stm32/debug.h +++ b/stm32/debug.h @@ -1,3 +1,8 @@ +/* + * (C) Copyright 2014 Leo C. + * + * SPDX-License-Identifier: GPL-2.0+ + */ #ifndef DEBUG_H_ #define DEBUG_H_ diff --git a/stm32/serial.c b/stm32/serial.c index 9193005..d2f1a93 100644 --- a/stm32/serial.c +++ b/stm32/serial.c @@ -1,8 +1,7 @@ /* - * serial.c + * (C) Copyright 2014 Leo C. * - * Created on: 04.05.2014 - * Author: leo + * SPDX-License-Identifier: GPL-2.0+ */ #include diff --git a/stm32/serial.h b/stm32/serial.h index 1a0f510..62d95e2 100644 --- a/stm32/serial.h +++ b/stm32/serial.h @@ -1,3 +1,9 @@ +/* + * (C) Copyright 2014 Leo C. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #ifndef SERIAL_H #define SERIAL_H diff --git a/stm32/z180-stamp-stm32.c b/stm32/z180-stamp-stm32.c index 15d732d..7000c53 100644 --- a/stm32/z180-stamp-stm32.c +++ b/stm32/z180-stamp-stm32.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2014 Leo C. + * + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -86,26 +89,26 @@ static void clock_setup(void) /* Enable clocks for: GPIO port A (for GPIO_USART1_TX and Button) - GPIO port C (LEDs) + GPIO port C (LEDs) USART1 - TIM16 (RST-Pin) + TIM16 (RST-Pin) TIM1 (IOCS1) */ - rcc_peripheral_enable_clock(&RCC_APB2ENR, - RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN - | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN + rcc_peripheral_enable_clock(&RCC_APB2ENR, + RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN + | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN); /* Enable clocks for: TIM3 */ - rcc_peripheral_enable_clock(&RCC_APB1ENR, + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); /* Enable clocks for: DMA1 */ - rcc_peripheral_enable_clock(&RCC_AHBENR, + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); } @@ -129,19 +132,19 @@ static void nvic_setup(void) static void tim3_setup(void) { TIM3_CR1 = TIM_CR1_CMS_EDGE | TIM_CR1_DIR_UP; - + TIM3_CCMR2 = 0 - | TIM_CCMR2_OC4M_FORCE_LOW + | TIM_CCMR2_OC4M_FORCE_LOW /* | TIM_CCMR2_OC4M_FORCE_HIGH */ /* | TIM_CCMR2_OC4M_PWM2 */ - + /* | TIM_CCMR2_OC4PE */ /* | TIM_CCMR2_OC4FE */ | TIM_CCMR2_CC4S_OUT; - + TIM3_CCER = TIM_CCER_CC4E | TIM_CCER_CC4P; - + TIM3_ARR = 48; /* default */ TIM3_CCR4 = 1; /* */ } @@ -154,7 +157,7 @@ static void gpio_setup(void) Remap TIM3 (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON, + gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_TIM3_REMAP_FULL_REMAP | AFIO_MAPR_PD01_REMAP); @@ -174,7 +177,7 @@ static void gpio_setup(void) void delay_systicks(int ticks) { int start, stop, now; - + start = STK_CVR; stop = start - ticks; if (stop < 0) { @@ -298,13 +301,13 @@ static void key_timerproc() { // key_state = key_state & key_in | (key_state | key_in) & key_in_last; key_state = c | ((key_in_last | key_in) & key_state); - + // key_state = (key_state&key_in_last) | (key_state&key_in) | (key_in_last&key_in); key_press |= c; - + key_in_last = key_in; - + if ((key_state & REPEAT_MASK) == 0) // check repeat function rpt = REPEAT_START; @@ -330,7 +333,7 @@ void sys_tick_handler(void) Stat |= S_10MS_TO; tick_10ms = 0; - + i = led_timer[0]; if (i) led_timer[0] = i - 1; @@ -339,11 +342,11 @@ void sys_tick_handler(void) led_timer[1] = i - 1; key_timerproc(); - + /* Drive timer procedure of low level disk I/O module */ //disk_timerproc(); } - + count_ms++; if (count_ms == 1000) { count_ms = 0; @@ -366,7 +369,7 @@ void rtc_isr(void) void tim3_set(int mode) { uint16_t cc_mode; - + cc_mode = TIM_CCMR2_CC4S_OUT; TIM3_CR1 = TIM_CR1_CMS_EDGE | TIM_CR1_DIR_UP /*| TIM_CR1_OPM */ ; @@ -380,9 +383,9 @@ void tim3_set(int mode) TIM3_CCR4 = mode/2; cc_mode |= TIM_CCMR2_OC4M_PWM2; } - + TIM3_CCMR2 = cc_mode; - + if (mode > 0) TIM3_CR1 |= TIM_CR1_CEN; } @@ -393,17 +396,17 @@ static uint32_t z80_sram_cmp(uint32_t addr, uint32_t length, uint8_t wval, int i { uint8_t rval; int_fast8_t errors = 0; - + DBG_P(1, "SRAM: Check %#.5x byte... ", length); while (length--) { if ((rval = z80_read(addr)) != wval) { - if (errors == 0) { + if (errors == 0) { printf("\nSRAM: Address W R\n" \ " -------------\n"); // 12345 00 11 } printf(" %.5lx %.2x %.2x\n", addr, wval, rval); - + if (++errors > 16 ) break; } @@ -421,7 +424,7 @@ static void z80_sram_fill(uint32_t addr, int length, uint8_t startval, int inc) printf("SRAM: Write %#.5x byte... ", length); //fflush(stdout); while (length--) { z80_write(addr, startval); - ++addr; + ++addr; startval += inc; } printf("Done.\n"); @@ -465,18 +468,18 @@ const char * const qbcat = "Zhe quick brown fox jumps over the lazy cat!"; uint8_t z80_get_byte(uint32_t adr) { uint8_t data; - + z80_request_bus(); data = z80_read(adr), z80_release_bus(); - + return data; } /*--------------------------------------------------------------------------*/ -static void do_10ms(void) +static void do_10ms(void) { for (uint_fast8_t i = 0; i < 2; i++) { switch (led_stat[i].mode) { @@ -696,19 +699,19 @@ int main(void) z80_reset(HIGH); z80_request_bus(); DBG_P(1, "got it!\n"); - + z80_memset(0, 0x76, 0x80000); //z80_sram_fill(0, 512 * 1024, 0x76, 0); z80_sram_cmp(0, (uint32_t)512 * 1024, 0x76, 0); - + z80_load_mem(); z80_reset(LOW); DBG_P(1, "Bus released!\n"); z80_release_bus(); z80_reset(HIGH); DBG_P(1, "Reset released!\n"); - - + + ledset(0, BLINK1, 50); while (1) { diff --git a/stm32/z80-if.c b/stm32/z80-if.c index 171fea9..6c415d1 100644 --- a/stm32/z80-if.c +++ b/stm32/z80-if.c @@ -1,3 +1,9 @@ +/* + * (C) Copyright 2014 Leo C. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + /** * * Pin assignments @@ -111,8 +117,8 @@ AFIO_MAPR_SPI1_REMAP AFIO_MAPR2 = -AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees -AFIO_MAPR_SPI1_REMAP +AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (frees +AFIO_MAPR_SPI1_REMAP */ @@ -220,7 +226,7 @@ AFIO_MAPR_SPI1_REMAP #define IOFIELD_GET(src, width, shift) \ ((src>>shift) & MASK(width)) - + #define CNF_MODE_I_F (GPIO_CNF_INPUT_FLOAT<<2 |GPIO_MODE_INPUT) #define CNF_MODE_O_PP (GPIO_CNF_OUTPUT_PUSHPULL<<2 | GPIO_MODE_OUTPUT_10_MHZ) @@ -249,16 +255,16 @@ static void tim16_setup(void) { RCC_APB2RSTR |= RCC_APB2RSTR_TIM16RST; RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM16RST; - + TIM16_BDTR = TIM_BDTR_MOE; - + TIM16_CCMR1 = 0 - | TIM_CCMR1_OC1M_FORCE_LOW + | TIM_CCMR1_OC1M_FORCE_LOW | TIM_CCMR1_CC1S_OUT; - + TIM16_CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP; - + TIM16_ARR = 48; /* default */ TIM16_CCR1 = 1; /* */ } @@ -268,7 +274,7 @@ static void tim16_setup(void) static void tim16_set(int mode) { uint16_t cc_mode; - + cc_mode = TIM_CCMR1_CC1S_OUT; TIM16_CR1 = TIM_CR1_OPM; @@ -281,9 +287,9 @@ static void tim16_set(int mode) TIM16_ARR = mode; cc_mode |= TIM_CCMR1_OC1M_PWM2; } - + TIM16_CCMR1 = cc_mode; - + if (mode > 0) TIM16_CR1 |= TIM_CR1_CEN; } @@ -292,44 +298,44 @@ static void tim16_set(int mode) -/* +/* * A0..A6, A8..A13 are buffered. No need to disable. * A7, A14..A18: set to input. */ - + static void z80_setup_adrbus_tristate(void) { #if 0 gpio_set_mode(ADunbuff1_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, MASK(ADunbuff1_WIDTH) << ADunbuff1_SHIFT); - gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, + gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, (MASK(ADunbuff2_WIDTH) << ADunbuff2_SHIFT) | (MASK(ADunbuff3_WIDTH) << ADunbuff3_SHIFT)); #else - GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) + GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) | (CNF_MODE_I_F << (4 * 0)); GPIO_CRL(GPIOC) = (GPIO_CRL(GPIOC) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7)))) | ((CNF_MODE_I_F << (4 * 6)) | (CNF_MODE_I_F << (4 * 7))); GPIO_CRH(GPIOC) = (GPIO_CRH(GPIOC) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4)))) | ((CNF_MODE_I_F << (4*2)) | (CNF_MODE_I_F << (4*3)) | (CNF_MODE_I_F << (4*4))); -#endif +#endif } - + static void z80_setup_adrbus_active(void) { #if 0 gpio_set_mode(ADunbuff1_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, MASK(ADunbuff1_WIDTH) << ADunbuff1_SHIFT); - gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, + gpio_set_mode(ADunbuff2_PORT, GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, (MASK(ADunbuff2_WIDTH) << ADunbuff2_SHIFT) | (MASK(ADunbuff3_WIDTH) << ADunbuff3_SHIFT)); #else - GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) + GPIO_CRH(GPIOA) = (GPIO_CRH(GPIOA) & ~(0x0f << (4 * 0))) | (CNF_MODE_O_PP << (4 * 0)); GPIO_CRL(GPIOC) = (GPIO_CRL(GPIOC) & ~((0x0f << (4 * 6)) | (0x0f << (4 * 7)))) | ((CNF_MODE_O_PP << (4 * 6)) | (CNF_MODE_O_PP << (4 * 7))); GPIO_CRH(GPIOC) = (GPIO_CRH(GPIOC) & ~((0x0f << (4*2)) | (0x0f << (4*3)) | (0x0f << (4*4)))) | ((CNF_MODE_O_PP << (4*2)) | (CNF_MODE_O_PP << (4*3)) | (CNF_MODE_O_PP << (4*4))); -#endif +#endif } @@ -402,9 +408,9 @@ void z80_release_bus(void) void z80_reset(level_t level) { int x = level ? -1 : 0; - + tim16_set(x); - + // Z80_O_RST = level; } @@ -469,7 +475,7 @@ void z80_memset(uint32_t addr, uint8_t data, int length) void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; - + z80_setup_dbus_out(); Z80_O_ME = 0; while(length--) { @@ -488,7 +494,7 @@ void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) 017B' rx.out_idx: ds 1 ; 017C' rx.buf: ds rx.buf_len ; 018B' rx.buf_end equ $-1 ; last byte (start+len-1) - + 018C' tx.bs_mask: ds 1 ; (buf_len - 1) 018D' tx.in_idx: ds 1 ; 018E' tx.out_idx: ds 1 ; @@ -517,7 +523,7 @@ static struct { idx_in, mask; } fifo_dsc[NUM_FIFOS]; - + void z80_memfifo_init(const fifo_t f, uint32_t adr) { @@ -557,7 +563,7 @@ int z80_memfifo_is_empty(const fifo_t f) int z80_memfifo_is_full(const fifo_t f) { int rc = 1; - + if (fifo_dsc[f].base != 0) { z80_request_bus(); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) @@ -570,7 +576,7 @@ int z80_memfifo_is_full(const fifo_t f) uint8_t z80_memfifo_getc(const fifo_t f) { uint8_t rc, idx; - + while (z80_memfifo_is_empty(f)) ; @@ -580,7 +586,7 @@ uint8_t z80_memfifo_getc(const fifo_t f) fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); z80_release_bus(); - + return rc; } @@ -588,7 +594,7 @@ uint8_t z80_memfifo_getc(const fifo_t f) void z80_memfifo_putc(fifo_t f, uint8_t val) { int idx; - + while (z80_memfifo_is_full(f)) ; @@ -714,7 +720,7 @@ DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); int z80_msg_fifo_getc(void) { int c = -1; - + if (msg_fifo.count != (NELEMS(msg_fifo.buf) - DMA1_CNDTR4)) { c = msg_fifo.buf[msg_fifo.count]; if (++msg_fifo.count == NELEMS(msg_fifo.buf)) diff --git a/stm32/z80-if.h b/stm32/z80-if.h index d7c030d..e65f160 100644 --- a/stm32/z80-if.h +++ b/stm32/z80-if.h @@ -1,3 +1,8 @@ +/* + * (C) Copyright 2014 Leo C. + * + * SPDX-License-Identifier: GPL-2.0+ + */ typedef enum {LOW, HIGH} level_t; -- cgit v1.2.3