From 296050043a19ee9b18c850dad01cc36ee64bd7b0 Mon Sep 17 00:00:00 2001
From: Leo C
Date: Tue, 28 Apr 2015 21:48:28 +0200
Subject: Integrate changes from z80-support branch

---
 z180/Tupfile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'z180/Tupfile')

diff --git a/z180/Tupfile b/z180/Tupfile
index bb88946..3105c94 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -2,7 +2,7 @@ include_rules
 
 PROG	= hdrom
 
-SRC 	= r3init.180 
+SRC 	= init.180 
 SRC	+= ddtz.180
 #SRC	+= fifoio.180 msgbuf.180 ser1-i.180 console.180
 SRC	+= msgbuf-a.180 conbuf-a.180 ser1-i.180 bioscio.180 chario.180
-- 
cgit v1.2.3


From 8df5b65577a04a48849387475634b3b694094dca Mon Sep 17 00:00:00 2001
From: Leo C
Date: Wed, 29 Apr 2015 19:23:29 +0200
Subject: Continue Integration

---
 z180/Tupfile     |   3 +-
 z180/bioscio.180 |   3 +-
 z180/ddtz.180    |   3 +-
 z180/init.180    | 424 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
 4 files changed, 394 insertions(+), 39 deletions(-)

(limited to 'z180/Tupfile')

diff --git a/z180/Tupfile b/z180/Tupfile
index 3105c94..1becb04 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -38,7 +38,8 @@ grep -q '^ 0 Error(s) Detected' ${OUTPUT}; ERROR=$?;\
 rm -f ${OUTPUT}; exit ${ERROR} \
 |> %B.rel | %B.lst 
 
-!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
+#!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
+!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) %f |> | %O.map
 
 #ifndef DEBUG
 
diff --git a/z180/bioscio.180 b/z180/bioscio.180
index 5ec55c6..b0fd4da 100644
--- a/z180/bioscio.180
+++ b/z180/bioscio.180
@@ -65,7 +65,8 @@ c$init$loop:
 	dec	c
 	jp	p,c$init$loop
 
-	ld	hl,1000000000000000b	; assign console to HOST
+;	ld	hl,1000000000000000b	; assign console to HOST
+	ld	hl,0100000000000000b	; assign console to ASCI1
 	ld	(@civec),hl
 	ld	(@covec),hl
 	ld	hl,0000000000000000b	; assign auxiliary to nothing
diff --git a/z180/ddtz.180 b/z180/ddtz.180
index 5f8bf20..490b829 100644
--- a/z180/ddtz.180
+++ b/z180/ddtz.180
@@ -6130,7 +6130,8 @@ l28dbh:
 ;------------------------------------------
 
 vartab:
-	dseg
+;	dseg
+	cseg
 ddtram:				
 ;todo:
 ; The following 2 params are changeable by user.
diff --git a/z180/init.180 b/z180/init.180
index 9edeaf2..16ca852 100644
--- a/z180/init.180
+++ b/z180/init.180
@@ -4,6 +4,7 @@
 	extrn ddtz,bpent
 	extrn $stack
 	extrn charini,?const,?conin
+	extrn ?cono,?conos
 
 	extrn romend
 
@@ -11,32 +12,35 @@
 	global	isv_sw
 
 	include config.inc
-	include	z180reg.inc
-	include z180.lib
+	if CPU_Z180
+	 include	z180reg.inc
+	 include z180.lib
+	endif
 
-;CR	equ	0dh
 
 
 
 ;----------------------------------------------------------------------
 
 	cseg
+romstart equ	$
 
+	org	romstart+0
 	jp start
 
+iobyte:	db	0
 ; restart vectors
 
 rsti	defl	1
 	rept	7
-	 db 0, 0, 0, 0, 0
+	org	8*rsti + romstart
 	 jp bpent
 rsti	 defl rsti+1
 	endm
-	 db 0, 0, 0, 0, 0
 
 ;----------------------------------------------------------------------
 	
-	;org	40h
+	org	romstart+40h
 
 	dw	0
 	db	0
@@ -48,6 +52,36 @@ $crom:	 defb c$rom		;
 	 db	0		;
 	endif
 
+INIWAITS defl	CWAITIO
+	if	ROMSYS
+INIWAITS defl	INIWAITS+CWAITROM
+	endif
+
+hwini0:
+	if CPU_Z180
+
+	 db	3		;count
+	 db	rcr,CREFSH	;configure DRAM refresh
+	 db	dcntl,INIWAITS	;wait states
+	 db	cbar,SYS$CBAR
+	else
+	 db     0
+	endif
+
+;----------------------------------------------------------------------
+
+	org	romstart+50h
+start:
+	jp	cstart
+	jp	wstart
+	jp	?const
+	jp	?conin
+	jp	?cono
+	jp	?conos
+	jp	charini
+
+;----------------------------------------------------------------------
+
 dmclrt:				;clear ram per dma
 	db	dmct_e-dmclrt-2 ;
 	db	sar0l		;first port
@@ -59,22 +93,9 @@ nullbyte:
 	dw 	0-romend	;count (64k)
 dmct_e:
 
-INIWAITS defl	CWAITIO
-	if	ROMSYS
-INIWAITS defl	INIWAITS+CWAITROM
-	endif
-
-hwini0:
-	db	3		;count
-	db	rcr,CREFSH	;configure DRAM refresh
-	db	dcntl,INIWAITS	;wait states
-	db	cbar,SYS$CBAR
+cstart:
+	if CPU_Z180
 
-;----------------------------------------------------------------------
-
-start:
-	ld	(tmpstack),sp
-	ld	sp,tmpstack
 	push af
 	in0 a,(itc)		;Illegal opcode trap?
 	jp m,??st01
@@ -82,10 +103,10 @@ start:
 	jr z,??st02		;    yes, harware reset
 
 ??st01:
+; TODO: SYS$CBR
 	ld	a,(syscbr)
 	out0	(cbr),a
 	pop af			;restore registers
-	ld	sp,(tmpstack)	;
 	jp bpent		;
 
 ??st02:
@@ -99,9 +120,16 @@ start:
 	out0	(ccr),a
 ;	ld	a,M_X2CM	;X2 Clock Multiplier
 ;	out0	(cmr),a
+	else
+	di
+	xor	a
+	ld	(@cbnk),a
+	endif
 
 ; search warm start mark
 
+	if CPU_Z180
+
 	ld ix,mark_55AA		;00b8	; top of common area
 	ld a,SYS$CBAR		;
 	out0 (cbar),a		;
@@ -127,11 +155,28 @@ swsm_l:
 	ld sp,$stack		;00e0	mark found, check
 	call checkcrc_alv	;00e3
 	jp z,wstart		;00e6	check ok,
-
+	else
+	ld ix,mark_55AA		; top of common area
+	ld a,0aah		;
+	cp (ix+000h)		;
+	jr nz,kstart		;
+	cp (ix+002h)		;
+	jr nz,kstart		;
+	cpl			;
+	cp (ix+001h)		;
+	jr nz,kstart		;
+	cp (ix+003h)		;
+	jr nz,kstart		;
+	ld sp,$stack		; mark found, check
+	jp z,wstart		; check ok,
+	endif
 ;
 ; ram not ok, initialize    --  kstart --
 
 kstart:
+	if CPU_Z180
+	
+	if 0
 
 	ld	a,088h		;00e9	0000-7fff: common 0
 	out0	(cbar),a	;00eb   8000-ffff: common 1
@@ -168,6 +213,14 @@ kstart:
 	add	a,8
 	cp	078h		;	stop at 078000
 	jr	nz,??cp_0
+	
+	else
+	
+	ld	de,0ffffh
+	ld	a,070h
+	out0	(cbr),a
+	
+	endif
 
 ;
 ;  ram test found 1 or more error free blocks (32k)
@@ -194,10 +247,15 @@ alloc:
 	out0	(cbr),c		;01de
 	ld	a,c
 	ld	(syscbr),a
+	endif
 	ld	sp,$stack	;01e1
 
 ; Clear RAM using DMA0
 
+	if CPU_Z180
+
+	if 0
+	
 	ld	hl,dmclrt	;load DMA registers
 	call	io.ini.m
 	ld	a,0cbh		;01ef	dst +1, src fixed, burst
@@ -208,6 +266,8 @@ alloc:
 ??cl_1:
 	out0	(dstat),a	;01f9	clear (up to) 64k
 	djnz	??cl_1		;	end of RAM?
+	
+	endif
 
 ; Init bank manager
 
@@ -271,24 +331,29 @@ l024ah:
 	ld	c,l		;
 	or	a		;
 	call	z,sub_04b5h	;
+	endif
 
 	ld	hl,055AAh	;set warm start mark
 	ld	(mark_55AA),hl	;
 	ld	(mark_55AA+2),hl;
 
 ;
-; crc ok       --  wstart  --
+; (crc ok)      --  wstart  --
 ;
 wstart:
 	call	sysram_init	;027f
 	call	ivtab_init
-
-	call	prt0_init
+	if CPU_Z180
+	 call	prt0_init
+	endif
 
 	call	charini
-
 	call	bufferinit
 
+	iff CPU_Z180
+	 ld	a,0
+	 call	selbnk
+	endif
 
 
 	im 2			;?030e
@@ -299,15 +364,19 @@ wstart:
 	or a			;028a
 	call nz,?conin		;028d
 
-	ld a,(banktab)		;
-	ld e,a			;
+	if CPU_Z180
+	 ld a,(banktab)		;
+	 ld e,a			;
+	else
+; TODO:
+	endif
 	jp ddtz			;0290
 
 
-	ds	8
-tmpstack:
-	dw	2
+	if CPU_Z180
+; TODO: SYS$CBR
 syscbr:	db	1
+	endif
 
 ;
 ;----------------------------------------------------------------------
@@ -376,6 +445,7 @@ endif
 
 
 bufferinit:
+	if CPU_Z180
 	call	 msginit
 
 	ld	hl,buffers
@@ -392,15 +462,15 @@ bfi_1:
 
 	or	a
 	jr	nz,bfi_2
-	in0	a,cbr
-	call	log2phys
+;	in0	a,(cbr)
+	call	hw_log2phys
 	ld	(40h+0),hl
 	ld	(40h+2),a
 	out0	(AVRINT5),a
 	jr	bfi_3	
 bfi_2:
-	in0	a,cbr
-	call	log2phys
+;	in0	a,(cbr)
+	call	hw_log2phys
 	ld	(bufdat+1),hl
 	ld	(bufdat+3),a
 	ld	hl,inimsg
@@ -409,6 +479,45 @@ bfi_3:
 	pop	hl
 	djnz	bfi_1
 	ret
+	else
+	call	 msginit
+
+	ld	hl,buffers
+	ld	b,buftablen
+bfi_1:
+	ld	a,(hl)
+	inc	hl
+	ld	(bufdat+0),a
+	ld	e,(hl)
+	inc	hl
+	ld	d,(hl)
+	inc	hl
+	ex	de,hl
+
+	or	a
+	jr	nz,bfi_2
+
+	ld	a,(@cbnk)
+	call	bnk2phys
+
+	ld	(40h+0),hl
+	ld	(40h+2),a
+	out	(AVRINT5),a
+	jr	bfi_3
+bfi_2:
+
+	ld	a,(@cbnk)
+	call	bnk2phys
+
+	ld	(bufdat+1),hl
+	ld	(bufdat+3),a
+	ld	hl,inimsg
+	call	msg.sout
+bfi_3:
+	ex	de,hl
+	djnz	bfi_1
+	ret
+	endif
 
 buffers:
 	db	0
@@ -451,7 +560,9 @@ ivtab_init:
 	ld	hl,ivtab	;
 	ld	a,h		;
 	ld	i,a		;
+	if CPU_Z180
 	out0	(il),l		;
+	endif
 
 ; Let all vectors point to spurious int routines.
 
@@ -469,6 +580,7 @@ ivt_i1:
 
 ;----------------------------------------------------------------------
 
+	if CPU_Z180
 prt0_init:
 	ld	a,i
 	ld	h,a
@@ -490,6 +602,7 @@ prt0itab:
 	dw	PRT_TC10MS
 	db	M_TIE0+M_TDE0	;enable timer 0 interrupt and down count.
 prt0it_e:
+	endif
 
 
 ;
@@ -498,9 +611,13 @@ prt0it_e:
 
 io.ini:
 	push	bc
+	if CPU_Z180
+
 	ld	b,0		;high byte port adress
 	ld	a,(hl)		;count
 	inc	hl
+	or	a
+	jr	z,ioi_e
 ioi_1:
 	ld	c,(hl)		;port address
 	inc	hl
@@ -508,9 +625,24 @@ ioi_1:
 	inc	b		;outi decrements b
 	dec	a
 	jr	nz,ioi_1
+
+	else
+	jr	ioi_nxt
+ioi_l:
+	ld	c,(hl)		;port address
+	inc	hl
+	otir
+ioi_nxt:
+	ld	b,(hl)		;count
+	inc	hl
+	inc	b
+	djnz	ioi_l
+	endif
+ioi_e:	
 	pop	bc
 	ret
 
+	if CPU_Z180
 io.ini.m:
 	push	bc
 	ld	b,(hl)
@@ -520,13 +652,17 @@ io.ini.m:
 	otimr
 	pop	bc
 	ret
+	endif
 
 io.ini.l:
 ;
 
+;
 ;----------------------------------------------------------------------
 ;
 
+	if CPU_Z180
+
 ; compute crc
 ; hl: start adr
 ; bc: len
@@ -802,6 +938,61 @@ log2phys:
 	pop	bc		;
 	ret			;
 
+;--------------------------------------------------------------
+;
+; de: Log. Address
+; 
+;
+; OP: ahl = (bankbase<<12) + (d<<8) + e
+;
+;out ahl: Phys. (linear) Address
+
+
+hw_log2phys:
+	push	bc		;
+	in0	c,(cbar)
+	ld	a,d
+	or	00fh
+	cp	c
+	jr	c,hlp_1
+	in0	c,(cbr)
+	jr	hlp_e
+hlp_1:
+	ld	b,16
+	mlt	bc
+	ld	a,d
+	cp	c
+	ld	c,0
+	jr	c,hlp_e
+	in0	c,(bbr)
+hlp_e:	
+	ld	b,16		;
+	mlt	bc		;bc = a<<4
+	ld	l,d		;
+	ld	h,0		;
+	add	hl,bc		;bc + d == a<<4 + d
+	ld	a,h		;
+	ld	h,l		;
+	ld	l,e		;
+	pop	bc		;
+	ret			;
+
+	else
+
+;
+;----------------------------------------------------------------------
+;
+
+bnk2phys:
+	sla	h
+	jr	nc,b2p_1		;A15=1 --> common
+	ld	a,3
+b2p_1:
+	srl	a
+	rr	h
+	ret
+
+	endif
 
 ;--------------------------------------------------------------
 ;
@@ -868,6 +1059,7 @@ jphl:
 
 ; ---------------------------------------------------------
 
+	if CPU_Z180
 
 iprt0:
 	push	af
@@ -890,6 +1082,8 @@ iprt_1:
 	ei
 	ret
 
+	endif
+
 ; ---------------------------------------------------------
 
 sp.int0:
@@ -915,6 +1109,160 @@ sp.i.1:
 ;	out	(80h),a
 	halt
 
+; ---------------------------------------------------------
+
+	iff CPU_Z180
+
+; Get IFF2
+; This routine may not be loaded in page zero
+;
+; return Carry clear, if INTs are enabled.
+;
+	global getiff
+getiff:
+	xor	a		;clear accu and carry
+	push	af		;stack bottom := 00xxh
+	pop	af
+	ld	a,i		;P flag := IFF2
+	ret	pe		;exit carry clear, if enabled
+	dec	sp
+	dec	sp		;has stack bottom been overwritten?
+	pop	af
+	and	a		;if not 00xxh, INTs were
+	ret	nz		;actually enabled
+	scf			;Otherwise, they really are disabled
+	ret
+
+;----------------------------------------------------------------------
+
+	global	selbnk
+
+; a: bank (0..2)
+
+selbnk:
+	push	bc
+	ld	c,a
+	call	getiff
+	push	af
+
+	ld	a,c
+	di
+	ld	(@cbnk),a
+	ld	a,5
+	out	(SIOAC),a
+	ld	a,(mm_sio0)
+	rla
+	srl	c
+	rra
+	out	(SIOAC),a
+	ld	(mm_sio0),a
+
+	ld	a,5
+	out	(SIOBC),a
+	ld	a,(mm_sio1)
+	rla
+	srl	c
+	rra
+	out	(SIOBC),a
+	ld	(mm_sio1),a
+	pop	af
+	pop	bc
+	ret	c			;INTs were disabled
+	ei
+	ret
+
+;----------------------------------------------------------------------
+
+; c: bank (0..2)
+
+	if 0
+
+selbnk:
+	ld	a,(@cbnk)
+	xor	c
+	and	3
+	ret	z		;no change
+
+	call	getiff
+	push	af
+	ld	a,c
+	di
+	ld	(@cbnk),a
+	ld	a,5
+	out	(SIOAC),a
+	ld	a,(mm_sio0)
+	rla
+	srl	c
+	rra
+	out	(SIOAC),a
+	ld	(mm_sio0),a
+
+	ld	a,5
+	out	(SIOBC),a
+	ld	a,(mm_sio1)
+	rla
+	srl	c
+	rra
+	out	(SIOBC),a
+	ld	(mm_sio1),a
+	pop	af
+	ret	nc			;INTs were disabled
+	ei
+	ret
+
+	endif
+
+;----------------------------------------------------------------------
+
+	if 0
+	ex	af,af'
+	push	af
+	ex	af,af'
+
+	rra
+	jr	nc,stbk1
+	ex	af,af'
+	ld	a,5
+	out	(SIOAC),a
+	ld	a,(mm_sio0)
+	rla
+	srl	c
+	rra
+	out	(SIOAC),a
+	ld	(mm_sio1),a
+	ex	af,af'
+
+stbk1:
+	rra
+	jr	nc,stbk2
+	ex	af,af'
+	ld	a,5
+	out	(SIOBC),a
+	ld	a,(mm_sio1)
+	rla
+	srl	c
+	rra
+	out	(SIOBC),a
+	ld	(mm_sio1),a
+	ex	af,af'
+
+stbk2:
+	endif
+
+	global	@cbnk
+	global	mm_sio0, mm_sio1
+
+@cbnk:	db	0		; current bank (0..2)
+mm_sio0:
+	ds	1
+mm_sio1:
+	ds	1
+
+
+	endif
+
+;----------------------------------------------------------------------
+
 curph	defl	$
 	.dephase
 sysrame:
@@ -925,6 +1273,8 @@ tim_s:	dw	0
 
 ;-----------------------------------------------------
 
+	if CPU_Z180
+
 	dseg
 
 	ds	1
@@ -941,6 +1291,8 @@ crc_len	equ	$-banktabsys
 crc_memalv:
 	ds	2	;
 
+	endif
+
 	cseg
 
 	;.phase	0ffc0h
-- 
cgit v1.2.3


From 23f85294a1f0ba1900bd3210965201cf73c04d6c Mon Sep 17 00:00:00 2001
From: Leo C
Date: Thu, 30 Apr 2015 20:46:39 +0200
Subject: Rename file "ser1-i.180" to "asci1-i.180" (Interrupt driver for
 ASCI1)

---
 z180/Makefile    |  11 ++-
 z180/Tupfile     |  13 ++-
 z180/asci1-i.180 | 258 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 z180/ser1-i.180  | 258 -------------------------------------------------------
 4 files changed, 269 insertions(+), 271 deletions(-)
 create mode 100644 z180/asci1-i.180
 delete mode 100644 z180/ser1-i.180

(limited to 'z180/Tupfile')

diff --git a/z180/Makefile b/z180/Makefile
index bd46639..11f9093 100644
--- a/z180/Makefile
+++ b/z180/Makefile
@@ -1,7 +1,7 @@
 
 
 SRC :=  init.180 ddtz.180
-SRC += fifoio.180 msgbuf.180 ser1-i.180 console.180
+SRC += fifoio.180 msgbuf.180 asci1-i.180 console.180
 SRC += romend.180
 
 INC := config.inc z180reg.inc z180.lib
@@ -11,7 +11,7 @@ OBJ := $(SRC:.180=.rel)
 #CP/M emulator
 CPMEMU = zxcc
 
-#Location of CP/M binaries 
+#Location of CP/M binaries
 CPMBIN = /usr/local/lib/cpm/bin80
 
 #AS = $(CPMEMU) $(CPMBIN)/m80.com
@@ -24,7 +24,7 @@ AS_OPT := MFS
 AS_QUIET = 1
 LN_QUIET = 1
 
-#LNKCMD = 
+#LNKCMD =
 LN_VERB = /V
 LN_PROG = 0
 LN_DATA = C000
@@ -80,7 +80,7 @@ if [ "$${ERROR}" != "0" ]; then cat $${OUTPUT}; rm -f $@; fi ; \
 exit $${ERROR}
 endef
 
-hdrom.c: hdrom.hex	
+hdrom.c: hdrom.hex
 	srec_cat -o $@ -c_array $(basename $<) -C_COMpressed -include $< -Intel
 
 hdrom.hex : $(OBJ)
@@ -92,7 +92,7 @@ hdrom.hex : $(OBJ)
 
 hdrom.map: hdrom.hex
 
-%.sym: hdrom.map %.lst 
+%.sym: hdrom.map %.lst
 	@$(cpm-mksym)
 
 .phony: clean realclean
@@ -123,4 +123,3 @@ realclean: clean
 	if [ "$${ERROR}" != "0" ]; then cat $${OUTPUT}; fi ; \
 	rm $${OUTPUT}; \
 	exit $${ERROR}
-
diff --git a/z180/Tupfile b/z180/Tupfile
index 1becb04..46aae4e 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -2,12 +2,12 @@ include_rules
 
 PROG	= hdrom
 
-SRC 	= init.180 
+SRC 	= init.180
 SRC	+= ddtz.180
-#SRC	+= fifoio.180 msgbuf.180 ser1-i.180 console.180
-SRC	+= msgbuf-a.180 conbuf-a.180 ser1-i.180 bioscio.180 chario.180
+#SRC	+= fifoio.180 msgbuf.180 asci1-i.180 console.180
+SRC	+= msgbuf-a.180 conbuf-a.180 asci1-i.180 bioscio.180 chario.180
 # serial (asci1) console only:
-#SRC	+= ser1-i.180 console.180
+#SRC	+= asci1-i.180 console.180
 SRC	+= romend.180
 
 
@@ -28,7 +28,7 @@ AS = $(CPMEMU) slr180.com
 
 ###############################################################################
 
-!AS-plain = |> $(AS) -%B/$(AS_OPT) |> %B.rel | %B.lst 
+!AS-plain = |> $(AS) -%B/$(AS_OPT) |> %B.rel | %B.lst
 
 !AS = |> ^ $(AS) -%B/$(AS_OPT)^ set +e; OUTPUT=\$(mktemp);\
 $(AS) -%B/$(AS_OPT) > ${OUTPUT};\
@@ -36,7 +36,7 @@ grep -q '^ 0 Error(s) Detected' ${OUTPUT}; ERROR=$?;\
 [ "${ERROR}" != "0" ] && cat ${OUTPUT};\
 [ "${ERROR}" != "0" ] && rm -f %B.rel;\
 rm -f ${OUTPUT}; exit ${ERROR} \
-|> %B.rel | %B.lst 
+|> %B.rel | %B.lst
 
 #!LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) -D $(LN_DATA) %f |> | %O.map
 !LINK = |> ld80 -o %o -ms %O.map -P $(LN_PROG) %f |> | %O.map
@@ -52,4 +52,3 @@ rm -f ${OUTPUT}; exit ${ERROR} \
 
 
 #endif
-
diff --git a/z180/asci1-i.180 b/z180/asci1-i.180
new file mode 100644
index 0000000..2410e38
--- /dev/null
+++ b/z180/asci1-i.180
@@ -0,0 +1,258 @@
+	page	200
+
+
+	extrn	buf.init
+	extrn	isv_sw
+
+	
+	global	ser.init
+	global	ser.ist,ser.in
+	global	ser.ost,ser.out
+
+;TODO: define a trampoline area somewhere in top ram. 
+rtxisvjmp	equ	0FF60h	;momentan frei...
+
+	include config.inc
+	include	z180reg.inc
+
+
+;-----------------------------------------------------
+
+	dseg
+	
+buf_start:
+	mkbuf	ser1.inbuf,s1.rx_len
+	mkbuf	ser1.outbuf,s1.tx_len
+buf_end:
+
+
+
+;-----------------------------------------------------
+
+	cseg
+;
+; Init Serial I/O for console input and output (ASCI1)
+;
+	
+
+ser.init:
+;	ld	a,i
+;	push	af		;save IFF
+;	di
+
+	xor	a		;
+	out0	(stat1),a	;Disable rx/tx interrupts
+		
+	ld hl,rxtx_src		;move rx and tx isv to common ram
+	ld de,rxtx_dst		;
+	ld bc,rxtx_src_e-rxtx_src ;	
+	ldir			;
+
+	ld hl,rtxisvjmp		;rx/tx int vector
+	ld (ivtab + IV$ASCI1),hl;
+	ld a,0cdh		;
+	ld (rtxisvjmp),a	;
+	ld hl,isv_sw		;
+	ld (rtxisvjmp + 1),hl	;
+	ld hl,rxtxisv		;
+	ld (rtxisvjmp + 3),hl	;
+
+; ASCI1: 8N1, highest baudrate (56700), CTS disabled
+
+	ld	a,M_MPBT 
+	out0	(cntlb1),a
+	ld	a,M_RE + M_TE + M_MOD2
+	out0	(cntla1),a
+	ld	a,M_RIE
+	out0	(stat1),a	;Enable rx interrupts
+
+	ld	ix,ser1.inbuf
+	ld	a,ser1.inbuf.mask
+	call	buf.init
+	ld	ix,ser1.outbuf
+	ld	a,ser1.outbuf.mask
+	call	buf.init
+
+;	pop	af
+;	ret	po
+;	ei
+	ret			;
+
+ser.ist:
+	push	ix
+	ld	ix,ser1.inbuf	;
+
+buf.empty:
+	ld	a,(ix+o.in_idx)	;
+	sub	(ix+o.out_idx)	;
+	pop	ix
+	ret	z
+	or	0ffh
+	ret
+	
+ser.in:
+	push	hl			;11	
+	push	de			;11
+	ld	hl,ser1.inbuf-1		; 9	hl = &rx.out_idx	
+	ld	a,(hl)			; 6	a = rx.out_idx
+	dec	hl			; 4	hl = &rx.in_idx
+	jr	bg.w1
+bg.wait:
+	halt
+bg.w1:
+	cp	(hl)			; 6	while (out_idx==in_idx) 
+	jr	z,bg.wait		; 6 (/8)	;
+
+	ld	e,a			; 4	
+	ld	d,0			; 6
+	inc	de
+	inc	de
+
+	ex	de,hl			; 3
+	add	hl,de			;10
+	ld	l,(hl)			; 6
+	ex	de,hl			; 3	
+
+	inc	a			; 4
+	dec	hl			; 4
+	and	(hl)			; 6	
+	inc	hl			; 4
+	inc	hl			; 4
+	ld	(hl),a			; 7
+	
+	ld	a,e			; 4
+	pop	de			; 9
+	pop	hl			; 9
+	ret				; 9
+					;   153 
+
+ser.ost:
+	push	ix
+	ld	ix,ser1.outbuf		;
+buf.full:
+	ld	a,(ix+o.in_idx)		;
+	inc	a
+	and	(ix+o.mask)
+	sub	(ix+o.out_idx)		;
+	pop	ix
+	ret	z
+	or	0ffh
+	ret
+
+
+ser.out:
+	push	ix
+	ld	ix,ser1.outbuf		;
+buf.put:
+	push	hl			;
+	push	bc
+	push	ix
+	pop	hl
+	ld	a,c
+	ld	c,(ix+o.in_idx)		;
+	ld	b,0
+	add	hl,bc
+	ld	(hl),a
+
+	ld	a,c			;
+	inc	a
+	and	(ix+o.mask)
+bp.wait:
+	cp	(ix+o.out_idx)		;
+	jr	z,bp.wait
+	ld	(ix+o.in_idx),a
+
+	di			;036f
+	in0	a,(stat1)	;0374
+	set	TIE,a		;0377
+	out0	(stat1),a	;0379
+	ei			;037c
+
+	ld	a,b
+	pop	bc
+	pop	hl
+	pop	ix
+	ret
+
+
+;------------------------------------------
+; ASCI 1 Transmit/Receive interupt routines
+; moved to common ram
+
+rxtx_src:
+	dseg
+rxtx_dst:				; (0c097h)  old
+
+rxtxisv:
+	inidat
+	in0 a,(stat1)			;receive flag set?
+	jp p,txisv			;
+
+	in0	d,(rdr1)		;todo: break detection
+	bit	FE,a			;framing error?
+	jr	nz,??ri_1
+	
+	push	ix
+	ld	ix,ser1.inbuf		;
+	ld	hl,ser1.inbuf		;
+	ld	c,(ix+o.in_idx)		;
+	ld	b,0
+	add	hl,bc
+
+	ld	a,c			;
+	inc	a
+	and	(ix+o.mask)
+	cp	(ix+o.out_idx)		;
+	jr	z,??ri_0
+	ld	(hl),d
+	ld	(ix+o.in_idx),a
+??ri_0:
+	pop	ix
+??ri_1:
+	in0	a,(cntla1)		;0705	c0c0
+	res	EFR,a			;0708
+	out0	(cntla1),a		;070a
+	ret
+
+	inidate
+
+txisv:
+	inidat
+	push	ix
+	ld	ix,ser1.outbuf		;
+
+	ld	a,(ix+o.out_idx)	;
+	cp	(ix+o.in_idx)		;
+	jr	z,??ti_2
+
+	ld	hl,ser1.outbuf		;
+	add	a,l
+	ld	l,a
+	jr	nc,??ti_1
+	inc	h
+??ti_1:
+	ld	l,(hl)
+	out0	(tdr1),l		;071b
+	
+	ld	a,(ix+o.out_idx)	;
+	inc	a
+	and	(ix+o.mask)
+	ld	(ix+o.out_idx),a
+	jr	??ti_3
+??ti_2:
+	in0	a,(stat1)		;0730	disable tx-int
+	res	TIE,a			;0733
+	out0	(stat1),a		;0735
+??ti_3:
+	pop	ix
+	ret
+
+	inidate
+
+	cseg
+rxtx_src_e:
+
+
+	end
+
+
diff --git a/z180/ser1-i.180 b/z180/ser1-i.180
deleted file mode 100644
index 2410e38..0000000
--- a/z180/ser1-i.180
+++ /dev/null
@@ -1,258 +0,0 @@
-	page	200
-
-
-	extrn	buf.init
-	extrn	isv_sw
-
-	
-	global	ser.init
-	global	ser.ist,ser.in
-	global	ser.ost,ser.out
-
-;TODO: define a trampoline area somewhere in top ram. 
-rtxisvjmp	equ	0FF60h	;momentan frei...
-
-	include config.inc
-	include	z180reg.inc
-
-
-;-----------------------------------------------------
-
-	dseg
-	
-buf_start:
-	mkbuf	ser1.inbuf,s1.rx_len
-	mkbuf	ser1.outbuf,s1.tx_len
-buf_end:
-
-
-
-;-----------------------------------------------------
-
-	cseg
-;
-; Init Serial I/O for console input and output (ASCI1)
-;
-	
-
-ser.init:
-;	ld	a,i
-;	push	af		;save IFF
-;	di
-
-	xor	a		;
-	out0	(stat1),a	;Disable rx/tx interrupts
-		
-	ld hl,rxtx_src		;move rx and tx isv to common ram
-	ld de,rxtx_dst		;
-	ld bc,rxtx_src_e-rxtx_src ;	
-	ldir			;
-
-	ld hl,rtxisvjmp		;rx/tx int vector
-	ld (ivtab + IV$ASCI1),hl;
-	ld a,0cdh		;
-	ld (rtxisvjmp),a	;
-	ld hl,isv_sw		;
-	ld (rtxisvjmp + 1),hl	;
-	ld hl,rxtxisv		;
-	ld (rtxisvjmp + 3),hl	;
-
-; ASCI1: 8N1, highest baudrate (56700), CTS disabled
-
-	ld	a,M_MPBT 
-	out0	(cntlb1),a
-	ld	a,M_RE + M_TE + M_MOD2
-	out0	(cntla1),a
-	ld	a,M_RIE
-	out0	(stat1),a	;Enable rx interrupts
-
-	ld	ix,ser1.inbuf
-	ld	a,ser1.inbuf.mask
-	call	buf.init
-	ld	ix,ser1.outbuf
-	ld	a,ser1.outbuf.mask
-	call	buf.init
-
-;	pop	af
-;	ret	po
-;	ei
-	ret			;
-
-ser.ist:
-	push	ix
-	ld	ix,ser1.inbuf	;
-
-buf.empty:
-	ld	a,(ix+o.in_idx)	;
-	sub	(ix+o.out_idx)	;
-	pop	ix
-	ret	z
-	or	0ffh
-	ret
-	
-ser.in:
-	push	hl			;11	
-	push	de			;11
-	ld	hl,ser1.inbuf-1		; 9	hl = &rx.out_idx	
-	ld	a,(hl)			; 6	a = rx.out_idx
-	dec	hl			; 4	hl = &rx.in_idx
-	jr	bg.w1
-bg.wait:
-	halt
-bg.w1:
-	cp	(hl)			; 6	while (out_idx==in_idx) 
-	jr	z,bg.wait		; 6 (/8)	;
-
-	ld	e,a			; 4	
-	ld	d,0			; 6
-	inc	de
-	inc	de
-
-	ex	de,hl			; 3
-	add	hl,de			;10
-	ld	l,(hl)			; 6
-	ex	de,hl			; 3	
-
-	inc	a			; 4
-	dec	hl			; 4
-	and	(hl)			; 6	
-	inc	hl			; 4
-	inc	hl			; 4
-	ld	(hl),a			; 7
-	
-	ld	a,e			; 4
-	pop	de			; 9
-	pop	hl			; 9
-	ret				; 9
-					;   153 
-
-ser.ost:
-	push	ix
-	ld	ix,ser1.outbuf		;
-buf.full:
-	ld	a,(ix+o.in_idx)		;
-	inc	a
-	and	(ix+o.mask)
-	sub	(ix+o.out_idx)		;
-	pop	ix
-	ret	z
-	or	0ffh
-	ret
-
-
-ser.out:
-	push	ix
-	ld	ix,ser1.outbuf		;
-buf.put:
-	push	hl			;
-	push	bc
-	push	ix
-	pop	hl
-	ld	a,c
-	ld	c,(ix+o.in_idx)		;
-	ld	b,0
-	add	hl,bc
-	ld	(hl),a
-
-	ld	a,c			;
-	inc	a
-	and	(ix+o.mask)
-bp.wait:
-	cp	(ix+o.out_idx)		;
-	jr	z,bp.wait
-	ld	(ix+o.in_idx),a
-
-	di			;036f
-	in0	a,(stat1)	;0374
-	set	TIE,a		;0377
-	out0	(stat1),a	;0379
-	ei			;037c
-
-	ld	a,b
-	pop	bc
-	pop	hl
-	pop	ix
-	ret
-
-
-;------------------------------------------
-; ASCI 1 Transmit/Receive interupt routines
-; moved to common ram
-
-rxtx_src:
-	dseg
-rxtx_dst:				; (0c097h)  old
-
-rxtxisv:
-	inidat
-	in0 a,(stat1)			;receive flag set?
-	jp p,txisv			;
-
-	in0	d,(rdr1)		;todo: break detection
-	bit	FE,a			;framing error?
-	jr	nz,??ri_1
-	
-	push	ix
-	ld	ix,ser1.inbuf		;
-	ld	hl,ser1.inbuf		;
-	ld	c,(ix+o.in_idx)		;
-	ld	b,0
-	add	hl,bc
-
-	ld	a,c			;
-	inc	a
-	and	(ix+o.mask)
-	cp	(ix+o.out_idx)		;
-	jr	z,??ri_0
-	ld	(hl),d
-	ld	(ix+o.in_idx),a
-??ri_0:
-	pop	ix
-??ri_1:
-	in0	a,(cntla1)		;0705	c0c0
-	res	EFR,a			;0708
-	out0	(cntla1),a		;070a
-	ret
-
-	inidate
-
-txisv:
-	inidat
-	push	ix
-	ld	ix,ser1.outbuf		;
-
-	ld	a,(ix+o.out_idx)	;
-	cp	(ix+o.in_idx)		;
-	jr	z,??ti_2
-
-	ld	hl,ser1.outbuf		;
-	add	a,l
-	ld	l,a
-	jr	nc,??ti_1
-	inc	h
-??ti_1:
-	ld	l,(hl)
-	out0	(tdr1),l		;071b
-	
-	ld	a,(ix+o.out_idx)	;
-	inc	a
-	and	(ix+o.mask)
-	ld	(ix+o.out_idx),a
-	jr	??ti_3
-??ti_2:
-	in0	a,(stat1)		;0730	disable tx-int
-	res	TIE,a			;0733
-	out0	(stat1),a		;0735
-??ti_3:
-	pop	ix
-	ret
-
-	inidate
-
-	cseg
-rxtx_src_e:
-
-
-	end
-
-
-- 
cgit v1.2.3


From 2fe441224da6410ec112322abf78524589b15498 Mon Sep 17 00:00:00 2001
From: Leo C
Date: Fri, 1 May 2015 20:43:26 +0200
Subject: Add polling driver for ASCI0/1

---
 avr/command_tbl.c |   2 +-
 z180/Tupfile      |   4 +-
 z180/asci-p.180   | 133 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 z180/bioscio.180  |   2 +-
 z180/chario.180   |  29 ++++++++----
 z180/init.180     |  66 ++++++++++++++++++++++-----
 z180/z180reg.inc  |   7 +++
 7 files changed, 218 insertions(+), 25 deletions(-)
 create mode 100644 z180/asci-p.180

(limited to 'z180/Tupfile')

diff --git a/avr/command_tbl.c b/avr/command_tbl.c
index 6c1c10d..b3c401c 100644
--- a/avr/command_tbl.c
+++ b/avr/command_tbl.c
@@ -150,7 +150,7 @@ CMD_TBL_ITEM(
 	""
 ),
 CMD_TBL_ITEM(
-	connect, 1, 1,	do_console,
+	connect, 1, 0,	do_console,
 	"Connect to CPU console i/o",
 	""
 ),
diff --git a/z180/Tupfile b/z180/Tupfile
index 46aae4e..23855f8 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -4,8 +4,8 @@ PROG	= hdrom
 
 SRC 	= init.180
 SRC	+= ddtz.180
-#SRC	+= fifoio.180 msgbuf.180 asci1-i.180 console.180
-SRC	+= msgbuf-a.180 conbuf-a.180 asci1-i.180 bioscio.180 chario.180
+#SRC	+= fifoio.180 msgbuf.180 asci-p.180 console.180
+SRC	+= msgbuf-a.180 conbuf-a.180 asci-p.180 bioscio.180 chario.180
 # serial (asci1) console only:
 #SRC	+= asci1-i.180 console.180
 SRC	+= romend.180
diff --git a/z180/asci-p.180 b/z180/asci-p.180
new file mode 100644
index 0000000..956faf1
--- /dev/null
+++ b/z180/asci-p.180
@@ -0,0 +1,133 @@
+	page	200
+
+	extrn	ioiniml
+
+	global	as0init
+	global	as0ista,as0inp
+	global	as0osta,as0out
+	global	as1init
+	global	as1ista,as1inp
+	global	as1osta,as1out
+
+	include config.inc
+	include	z180reg.inc
+
+
+;-----------------------------------------------------
+;
+;
+; TC = (f PHI /(2*baudrate*Clock_mode)) - 2
+;
+; TC = (f PHI / (32 * baudrate)) - 2
+;
+
+	cseg
+;
+; Init Serial I/O for console input and output (ASCI1)
+;
+	
+
+
+as0init:
+	ld	hl,initab0
+	jp	ioiniml
+
+as1init:
+	ld	hl,initab1
+	jp	ioiniml
+
+		
+	ld	a,M_MPBT 
+	out0	(cntlb1),a
+	ld	a,M_RE + M_TE + M_MOD2	;Rx/Tx enable 
+	out0	(cntla1),a
+	ld	a,M_RIE
+	out0	(stat1),a	;Enable rx interrupts
+
+	ret			;
+
+
+initab0:
+	db	1,stat0,0		;Disable rx/tx interrupts
+					;Enable baud rate generator
+	db	1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS
+	db	2,astc0l,low 28, high 28
+	db	1,cntlb0,M_MPBT		;No MP Mode, X16
+	db	1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1
+	db	0
+
+initab1:
+	db	1,stat1,0		;Disable rx/tx ints, disable CTS1
+	db	1,asext1,M_BRGMOD	;Enable baud rate generator
+	db	2,astc1l,low 3, high 3
+	db	1,cntlb1,M_MPBT		;No MP Mode, X16
+	db	1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1
+	db	0
+
+
+
+as0ista:
+	in0	a,(stat0)
+	and	M_RDRF
+	ret	z
+	or	0ffh
+	ret
+	
+as1ista:
+	in0	a,(stat1)
+	and	M_RDRF
+	ret	z
+	or	0ffh
+	ret
+	
+
+as0inp:
+	in0	a,(stat0)
+	rlca
+	jr	nc,as0inp
+	in0	a,rdr0
+	ret
+
+as1inp:
+	in0	a,(stat1)
+	rlca
+	jr	nc,as1inp
+	in0	a,rdr1
+	ret
+
+
+
+as0osta:
+	in0	a,(stat0)
+	and	M_TDRE
+	ret	z
+	or	0ffh
+	ret
+
+as1osta:
+	in0	a,(stat1)
+	and	M_TDRE
+	ret	z
+	or	0ffh
+	ret
+
+
+as0out:
+	in0	a,(stat0)
+	and	M_TDRE
+	jr	z,as0out
+	out0	(tdr0),c
+	ld	a,c
+	ret
+
+as1out:
+	in0	a,(stat1)
+	and	M_TDRE
+	jr	z,as1out
+	out0	(tdr1),c
+	ld	a,c
+	ret
+
+	end
+
+
diff --git a/z180/bioscio.180 b/z180/bioscio.180
index b0fd4da..2d8e5e0 100644
--- a/z180/bioscio.180
+++ b/z180/bioscio.180
@@ -66,7 +66,7 @@ c$init$loop:
 	jp	p,c$init$loop
 
 ;	ld	hl,1000000000000000b	; assign console to HOST
-	ld	hl,0100000000000000b	; assign console to ASCI1
+	ld	hl,0010000000000000b	; assign console to ASCI1
 	ld	(@civec),hl
 	ld	(@covec),hl
 	ld	hl,0000000000000000b	; assign auxiliary to nothing
diff --git a/z180/chario.180 b/z180/chario.180
index 6632690..8313658 100644
--- a/z180/chario.180
+++ b/z180/chario.180
@@ -8,14 +8,15 @@
 	public	@ctbl
 
 	extrn	ff.init,ff.i.st,ff.in,ff.o.st,ff.out
-	extrn	ser.init,ser.ist,ser.in,ser.ost,ser.out
+	extrn	as0init,as0ista,as0inp,as0osta,as0out
+	extrn	as1init,as1ista,as1inp,as1osta,as1out
 	
 	include config.inc
 	include	z180reg.inc
 	include modebaud.inc	; define mode bits and baud eqautes
 
 
-max$device	equ 2
+max$device	equ 3
 
 	cseg
 
@@ -25,7 +26,8 @@ max$device	equ 2
 	ld	b,c
 	call	vector$io
 	dw	ff.init
-	dw	ser.init
+	dw	as0init
+	dw	as1init
 	dw	rret
 
 ; b = device, c = output char, a = input char
@@ -33,25 +35,29 @@ max$device	equ 2
 ?ci:				; character input
 	call	vector$io
 	dw	ff.in
-	dw	ser.in
+	dw	as0inp
+	dw	as1inp
 	dw	null$input
 
 ?cist:				; character input status
 	call	vector$io
 	dw	ff.i.st
-	dw	ser.ist
+	dw	as0ista
+	dw	as1ista
 	dw	null$status
 
 ?co:				; character output
 	call	vector$io
 	dw	ff.out
-	dw	ser.out
+	dw	as0out
+	dw	as1out
 	dw	rret
 
 ?cost:				; character output status
 	call	vector$io
 	dw	ff.o.st
-	dw	ser.ost
+	dw	as0osta
+	dw	as1osta
 	dw	ret$true
 
 vector$io:
@@ -89,10 +95,15 @@ null$status:
 
 @ctbl:
 	db	'HOST  '	; device 0
-	db	mb$output
+	db	mb$in$out
 	db	baud$none
 
-	db	'ASCI1 '	; device 0
+	db	'ASCI1 '	; device 1
+	db	mb$in$out+mb$serial+mb$soft$baud
+ser0$baud:
+	db	baud$19200
+
+	db	'ASCI1 '	; device 2
 	db	mb$in$out+mb$serial+mb$soft$baud
 ser1$baud:
 	db	baud$19200
diff --git a/z180/init.180 b/z180/init.180
index 0bd37c1..39b03fc 100644
--- a/z180/init.180
+++ b/z180/init.180
@@ -5,7 +5,6 @@
 	extrn $stack
 	extrn charini,?const,?conin
 	extrn ?cono,?conos
-
 	extrn romend
 
 
@@ -75,14 +74,12 @@ start:
 
 hwini0:
     if CPU_Z180
-
 	db	3		;count
 	db	rcr,CREFSH	;configure DRAM refresh
 	db	dcntl,INIWAITS	;wait states
 	db	cbar,SYS$CBAR
-    else
-	db     0
     endif
+	db     0
 
     if CPU_Z180
 dmclrt:				;clear ram per dma
@@ -95,6 +92,7 @@ nullbyte:
 	db	00h		;dst
 	dw 	0-romend	;count (64k)
 dmct_e:
+	db	0
     endif
 
 
@@ -165,7 +163,7 @@ kstart:
      if 0
 	
 	ld	hl,dmclrt	;load DMA registers
-	call	io.ini.m
+	call	ioiniml
 	ld	a,0cbh		;01ef	dst +1, src fixed, burst
 	out0	(dmode),a	;01f1
 
@@ -434,7 +432,7 @@ prt0_init:
 	inc	hl
 	ld	(hl),high iprt0
 	ld	hl,prt0itab
-	call	io.ini.m
+	call	ioiniml
 	ret
 
 prt0itab:
@@ -444,6 +442,7 @@ prt0itab:
 	dw	PRT_TC10MS
 	db	M_TIE0+M_TDE0	;enable timer 0 interrupt and down count.
 prt0it_e:
+	db	0
     endif
 
 
@@ -451,24 +450,55 @@ prt0it_e:
 ;----------------------------------------------------------------------
 ;
 
+    if CPU_Z180
 io.ini:
+     if 0
 	push	bc
-    if CPU_Z180
-
 	ld	b,0		;high byte port adress
+ioi_nxt:
 	ld	a,(hl)		;count
 	inc	hl
 	or	a
 	jr	z,ioi_e
-ioi_1:
+
 	ld	c,(hl)		;port address
 	inc	hl
+ioi_r:
 	outi
 	inc	b		;outi decrements b
 	dec	a
-	jr	nz,ioi_1
+	jr	nz,ioi_r
+	jr	ioi_nxt
 ioi_e:	
+	pop	bc
+	ret
+	
+     else ;(if 1/0)
+     
+	push	bc
+	jr	ioi_nxt
+ioi_l:
+	ld	c,(hl)		;port address
+	inc	hl
+	inc	c
+ioi_r:
+	dec	c		;otim increments c
+	otim
+	jr	z,ioi_r
+ioi_nxt:
+	ld	b,(hl)		;count
+	inc	hl
+	inc	b		;stop if count == 0
+	djnz	ioi_l
+	pop	bc
+	ret
+	
+     endif ;(1/0)
+
     else
+
+io.ini:
+	push	bc
 	jr	ioi_nxt
 ioi_l:
 	ld	c,(hl)		;port address
@@ -483,16 +513,28 @@ ioi_nxt:
 	pop	bc
 	ret
 
+;----------------------------------------------------------------------
+
     if CPU_Z180
-io.ini.m:
+
+	global ioiniml
+
+ioiniml:
 	push	bc
+	xor	a
+ioml_lp:
 	ld	b,(hl)
 	inc	hl
+	cp	b
+	jr	z,ioml_e
+	
 	ld	c,(hl)
 	inc	hl
 	otimr
+	jr	ioml_lp
+ioml_e:
 	pop	bc
-	ret
+	ret	z
     endif
 
 io.ini.l:
diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 5bbd088..271a446 100644
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -76,6 +76,13 @@ tcr	equ	IOBASE+10h	;Timer Control Register
 
 asext0	equ	IOBASE+12h	;ASCI Extension Control Register
 asext1	equ	IOBASE+13h	;ASCI Extension Control Register
+	b2m DCD0DIS,6		;DCD0 Disable
+	b2m CTS0DIS,5		;CTS0 Disable
+	b2m X1,4		;CKA * 1 Clock/Samle Rate Divider
+	b2m BRGMOD,3		;BRG Mode (Baud rate generator)
+	b2m BREAKEN,2		;Break Enable
+	b2m BREAK,1		;Break detected
+	b2m SENDBREAK,0		;Send Break
 
 tmdr1l	equ	IOBASE+14h	;Timer Data Register Channel 1
 tmdr1h	equ	IOBASE+15h	;
-- 
cgit v1.2.3


From 64cc220767e870fad388fb9021cf96ff2958275b Mon Sep 17 00:00:00 2001
From: Leo C
Date: Fri, 1 May 2015 23:19:32 +0200
Subject: Simplify Console I/O. Switch back to IOBYTE.

---
 z180/Makefile     |   4 +-
 z180/Tupfile      |   8 +-
 z180/conbuf-a.180 |  85 +++++---
 z180/console.180  | 143 ++++++++++---
 z180/init-80.180  | 591 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 z180/init.180     |   4 +-
 z180/msgbuf-a.180 |   6 +-
 7 files changed, 781 insertions(+), 60 deletions(-)
 create mode 100644 z180/init-80.180

(limited to 'z180/Tupfile')

diff --git a/z180/Makefile b/z180/Makefile
index 11f9093..c6727b9 100644
--- a/z180/Makefile
+++ b/z180/Makefile
@@ -1,7 +1,9 @@
 
 
 SRC :=  init.180 ddtz.180
-SRC += fifoio.180 msgbuf.180 asci1-i.180 console.180
+SRC += console.180
+SRC += msgbuf-a.180 conbuf-a.180
+SRC += asci1-p.180
 SRC += romend.180
 
 INC := config.inc z180reg.inc z180.lib
diff --git a/z180/Tupfile b/z180/Tupfile
index 23855f8..50ede98 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -4,10 +4,10 @@ PROG	= hdrom
 
 SRC 	= init.180
 SRC	+= ddtz.180
-#SRC	+= fifoio.180 msgbuf.180 asci-p.180 console.180
-SRC	+= msgbuf-a.180 conbuf-a.180 asci-p.180 bioscio.180 chario.180
-# serial (asci1) console only:
-#SRC	+= asci1-i.180 console.180
+SRC	+= msgbuf-a.180 conbuf-a.180
+#SRC	+= bioscio.180 chario.180
+SRC	+= console.180
+SRC	+= asci-p.180
 SRC	+= romend.180
 
 
diff --git a/z180/conbuf-a.180 b/z180/conbuf-a.180
index 8534f73..096bbf9 100644
--- a/z180/conbuf-a.180
+++ b/z180/conbuf-a.180
@@ -9,7 +9,9 @@
 	extrn	buf.init
 
 	include config.inc
+	if CPU_Z180
 	include	z180reg.inc
+	endif
 
 
 ;--------------------------------------------------------------
@@ -96,36 +98,69 @@ buf.full:
 	ret
 
 
+	if 1
 ff.out:
-	push	ix
-	ld	ix,co.fifo		;
+	push	ix			;15
+	ld	ix,co.fifo		;14
 
 buf.put:
-	push	hl			;
-	push	bc
-	push	ix
-	pop	hl
-	ld	a,c
-	ld	c,(ix+o.in_idx)		;
-	ld	b,0
-	add	hl,bc
-	ld	b,a
-
-	ld	a,c			;
-	inc	a
-	and	(ix+o.mask)
+	push	hl			;11
+	push	bc			;11
+	push	ix			;15
+	pop	hl			;10
+	ld	a,c			;4
+	ld	c,(ix+o.in_idx)		;19
+	ld	b,0			;7
+	add	hl,bc			;11
+	ld	(hl),a			;7
+	ld	b,a			;4
+
+	ld	a,c			;4
+	inc	a			;4
+	and	(ix+o.mask)		;19
 bp.wait:
-	cp	(ix+o.out_idx)		;
-	jr	z,bp.wait
-	ld	(hl),b
-	ld	(ix+o.in_idx),a
+	cp	(ix+o.out_idx)		;19
+	jr	z,bp.wait		;12/7
+	ld	(ix+o.in_idx),a		;19
 	
-	out	(AVRINT6),a
-	ld	a,b
-	pop	bc
-	pop	hl
-	pop	ix
-	ret
+	out	(AVRINT6),a		;11
+	ld	a,b			;4
+	pop	bc			;10
+	pop	hl			;10
+	pop	ix			;14
+	ret				;10
+
+	else
+
+ff.out:
+	push	ix			;15
+	ld	ix,co.fifo		;14
+
+buf.put:
+	push	hl			;11
+	push	ix			;15
+	pop	hl			;10
+	ld	a,(ix+o.in_idx)		;19
+	add	a,l			;4
+	ld	l,a			;4
+	jr	nc,bp.1			;12/7
+	inc	l			;4
+	ld	(hl),c			;7
+	ld	a,(ix+o.in_idx)		;19
+	inc	a			;4
+	and	(ix+o.mask)		;19
+bp.wait:
+	cp	(ix+o.out_idx)		;19
+	jr	z,bp.wait		;12/7
+	ld	(ix+o.in_idx),a		;19
+
+	out	(AVRINT6),a		;11
+	ld	a,c			;4
+	pop	hl			;10
+	pop	ix			;14
+	ret				;10		|
+
+	endif
 
 	end
 
diff --git a/z180/console.180 b/z180/console.180
index d4f4130..1241d5a 100644
--- a/z180/console.180
+++ b/z180/console.180
@@ -2,47 +2,136 @@
 	.z80
 	
 
-	global	$coninit
-	global	$cists,$ci
-	global	$co
+; iobyte:
+;		0 = console on AVR-System
+;		1 = console on SIO/ASCI
 
 
-	extrn	ser.init,ser.ist,ser.in,ser.ost,ser.out
+	extrn	iobyte
 	extrn	ff.init,ff.i.st,ff.in
 	extrn	ff.o.st,ff.out
+    if CPU_Z180
+	extrn	as0init,as0ista,as0inp,as0osta,as0out
+	extrn	as1init,as1ista,as1inp,as1osta,as1out
+    else
+	extrn	ser.init,ser.ist,ser.in,ser.ost,ser.out
+    endif
 	
+	public	charini
+	public	?const,?conin
+	public	?conos,?cono
 
 	include config.inc
+    if CPU_Z180
 	include	z180reg.inc
+    endif
 
 	cseg
-;
-;
 
-$coninit:
+    if CPU_Z180
+charini:
+	call	ff.init
+	call	as0init
+	jp	as1init
+
+?const:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.i.st
+	dec	a
+	jp	z,as0ista
+	dec	a
+	jp	z,as1ista
+	jr	nullstatus
+
+?conin:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.in
+	dec	a
+	jp	z,as0inp
+	dec	a
+	jp	z,as1inp
+	jr	nullinput
+
+?conos:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.o.st
+	dec	a
+	jp	z,as0osta
+	dec	a
+	jp	z,as1osta
+	jr	rettrue
+
+?cono:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.out
+	dec	a
+	jp	z,as0out
+	dec	a
+	jp	z,as1out
+	jr	nulloutput
+
+    else
+
+charini:
 	call	ff.init
+	ld	c,0
 	call	ser.init
+	ld	c,1
+	jp	ser.init
+
+?const:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.i.st
+	dec	a
+	ld	b,a
+	jp	ser.ist
+
+?conin:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.in
+	dec	a
+	ld	b,a
+	jp	ser.in
+
+?conos:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.o.st
+	dec	a
+	ld	b,a
+	jp	ser.ost
+
+?cono:
+	ld	a,(iobyte)
+	and	03h
+	jp	z,ff.out
+	dec	a
+	ld	b,a
+	jp	ser.out
+    endif
+
+
+nullinput:
+	ld	a,1Ah
 	ret
-	
-$cists:
-	call	ff.i.st
-	ret	nz
-	call	ser.ist
+
+nulloutput:
+	ld	a,c
 	ret
-	
-$ci:
-	call	ff.i.st
-	jp	nz,ff.in
-	call	ser.ist
-	jp	nz,ser.in
-	jr	$ci
-	
-;$costs:
-;	jp	f.o.st
-	
-$co:
-	call	ff.out
-	jp	ser.out
-	
+
+rettrue:
+	or	0FFh
+	ret
+
+nullstatus:
+	xor	a
+	ret
+
 	end
 
diff --git a/z180/init-80.180 b/z180/init-80.180
new file mode 100644
index 0000000..8b71993
--- /dev/null
+++ b/z180/init-80.180
@@ -0,0 +1,591 @@
+	page	255
+	.z80
+
+	extrn ddtz,bpent
+	extrn $stack
+	extrn charini,?const,?conin
+	extrn ?cono,?conos
+
+	extrn romend
+
+	global	iobyte
+	global	isv_sw
+
+	include config.inc
+
+
+
+
+;----------------------------------------------------------------------
+
+	cseg
+romstart equ	$
+
+	org	romstart+0
+	jp	start
+
+iobyte:	db	0
+
+; restart vectors
+
+rsti	defl	1
+	rept	7
+
+	org	8*rsti + romstart
+	 jp bpent
+rsti	 defl rsti+1
+	endm
+
+;----------------------------------------------------------------------
+	
+	org	romstart+40h
+
+	dw	0
+	db	0
+
+	cseg
+
+	if ROMSYS
+$crom:	 defb c$rom		;
+	else
+	 db	0		;
+	endif
+
+
+hwini0:
+	db	0		;count
+;	db	rcr,CREFSH	;configure DRAM refresh
+;	db	dcntl,INIWAITS	;wait states
+;	db	cbar,SYS$CBAR
+
+
+;----------------------------------------------------------------------
+
+	org	romstart+50h
+
+start:
+	jp	cstart
+	jp	wstart
+	jp	?const
+	jp	?conin
+	jp	?cono
+	jp	?conos
+	jp	charini
+
+cstart:
+	di
+
+	xor	a
+	ld	(@cbnk),a
+
+; search warm start mark
+
+	ld ix,mark_55AA		; top of common area
+	ld a,0aah		;
+	cp (ix+000h)		;
+	jr nz,kstart		;
+	cp (ix+002h)		;
+	jr nz,kstart		;
+	cpl			;
+	cp (ix+001h)		;
+	jr nz,kstart		;
+	cp (ix+003h)		;
+	jr nz,kstart		;
+	ld sp,$stack		; mark found, check
+;	call checkcrc_alv	;
+	jp z,wstart		; check ok,
+
+;
+; ram not ok, initialize    --  kstart --
+
+kstart:
+	ld	sp,$stack	;01e1
+
+; Clear RAM 
+
+; Init bank manager
+
+;----------------------------------------------------------------------
+;
+
+	ld	hl,055AAh	;set warm start mark
+	ld	(mark_55AA),hl	;
+	ld	(mark_55AA+2),hl;
+
+;
+;       --  wstart  --
+;
+wstart:
+	call	sysram_init	;027f
+	call	ivtab_init
+
+	call	charini
+	call	bufferinit
+
+	ld	c,0
+	call	selbnk
+
+
+	im 2			;?030e
+	ei			;0282
+
+	call ?const		;0284
+	call ?const		;0287
+	or a			;028a
+	call nz,?conin		;028d
+
+;;;	ld a,(banktab)		;
+;;;	ld e,a			;
+	jp ddtz			;0290
+
+
+;----------------------------------------------------------------------
+;
+
+;TODO: Make a ringbuffer module.
+
+	global	buf.init
+
+buf.init:
+	ld	(ix+o.in_idx),0
+	ld	(ix+o.out_idx),0
+	ld	(ix+o.mask),a
+	ret
+
+;----------------------------------------------------------------------
+
+
+	extrn	msginit,msg.sout
+	extrn	mtx.fifo,mrx.fifo
+	extrn	co.fifo,ci.fifo
+
+
+bufferinit:
+	call	 msginit
+
+	ld	hl,buffers
+	ld	b,buftablen
+bfi_1:
+	ld	a,(hl)
+	inc	hl
+	ld	(bufdat+0),a
+	ld	e,(hl)
+	inc	hl
+	ld	d,(hl)
+	inc	hl
+	ex	de,hl
+
+	or	a
+	jr	nz,bfi_2
+
+	ld	a,(@cbnk)
+	call	bnk2phys
+
+	ld	(40h+0),hl
+	ld	(40h+2),a
+	out	(AVRINT5),a
+	jr	bfi_3
+bfi_2:
+
+	ld	a,(@cbnk)
+	call	bnk2phys
+
+	ld	(bufdat+1),hl
+	ld	(bufdat+3),a
+	ld	hl,inimsg
+	call	msg.sout
+bfi_3:
+	ex	de,hl
+	djnz	bfi_1
+	ret
+
+
+buffers:
+	db	0
+	dw	mtx.fifo
+	db	1
+	dw	mrx.fifo
+	db	2
+	dw	co.fifo
+	db	3
+	dw	ci.fifo
+buftablen equ	($ - buffers)/3
+
+inimsg:
+	db	inimsg_e - $ -1
+	db	0AEh
+	db	inimsg_e - $ -1
+	db	0
+bufdat:
+	db	0
+	dw	0
+	db	0
+inimsg_e:
+
+
+;
+;----------------------------------------------------------------------
+;
+
+bnk2phys:
+	sla	h
+	jr	nc,b2p_1		;A15=1 --> common
+	ld	a,3
+b2p_1:
+	srl	a
+	rr	h
+	ret
+
+;
+;----------------------------------------------------------------------
+;
+
+sysram_init:
+	ld hl,sysramw
+	ld de,topcodsys
+	ld bc,sysrame-sysramw
+	ldir
+
+	ret
+
+;----------------------------------------------------------------------
+
+ivtab_init:
+	ld	hl,ivtab	;
+	ld	a,h		;
+	ld	i,a		;
+;	out0	(il),l		;
+
+; Let all vectors point to spurious int routines.
+
+	ld	d,high sp.int0
+	ld	a,low  sp.int0
+	ld	b,9
+ivt_i1:
+	ld	(hl),a
+	inc	l
+	ld	(hl),d
+	inc	l
+	add	a,sp.int.len
+	djnz	ivt_i1
+	ret
+
+;----------------------------------------------------------------------
+;
+
+	global io.ini
+	
+io.ini:
+	push	bc
+
+	if CPU_Z180
+
+	ld	b,0		;high byte port adress
+	ld	a,(hl)		;count
+	inc	hl
+	or	a
+	jr	z,ioi_e
+ioi_1:
+	ld	c,(hl)		;port address
+	inc	hl
+	outi
+	inc	b		;outi decrements b
+	dec	a
+	jr	nz,ioi_1
+
+	else
+	jr	ioi_nxt
+ioi_l:
+	ld	c,(hl)		;port address
+	inc	hl
+	otir
+ioi_nxt:
+	ld	b,(hl)		;count
+	inc	hl
+	inc	b
+	djnz	ioi_l
+	endif
+ioi_e:	
+	pop	bc
+	ret
+
+	if CPU_Z180
+io.ini.m:
+	push	bc
+	ld	b,(hl)
+	inc	hl
+	ld	c,(hl)
+	inc	hl
+	otimr
+	pop	bc
+	ret
+	endif
+
+io.ini.l:
+;
+
+
+;----------------------------------------------------------------------
+;
+;return:
+; hl = hl + a
+; Flags undefined
+;
+
+add_hl_a:
+	add a,l
+	ld l,a
+	ret nc
+	inc h
+	ret
+
+; ---------------------------------------------------------
+
+sysramw:
+
+	.phase isvsw_loc
+topcodsys:
+
+; Trampoline for interrupt routines in banked ram.
+; Switch stack pointer to "system" stack in top ram
+
+; todo: z80 bank switch
+
+isv_sw:				;
+	ex (sp),hl		; save hl, return adr in hl
+	push de			;
+	push af			;
+	ex de,hl		;
+	ld hl,0			;
+	add hl,sp		;
+	ld a,h			;
+	cp 0f8h			;
+	jr nc,isw_1		;
+	ld sp,$stack		;
+isw_1:
+	push hl			;
+				; save current bank
+;	in0 h,(cbar)		;
+	push hl			;
+				; switch to system bank
+;	ld a,SYS$CBAR		;
+;	out0 (cbar),a		; 
+	ex de,hl		;
+	ld e,(hl)		;
+	inc hl			;
+	ld d,(hl)		;
+	ex de,hl		;
+	push bc			;
+	call jphl		;
+
+	pop bc			;
+	pop hl			; restore bank
+;	out0 (cbar),h		;
+	pop hl			;
+	ld sp,hl		;
+	pop af			;
+	pop de			;
+	pop hl			;
+	ei			;
+	ret			;
+jphl:
+	jp (hl)			;
+
+; ---------------------------------------------------------
+
+sp.int0:
+	ld	a,0d0h
+	jr	sp.i.1
+sp.int.len equ	$-sp.int0
+	ld	a,0d1h
+	jr	sp.i.1
+	ld	a,0d2h
+	jr	sp.i.1
+	ld	a,0d3h
+	jr	sp.i.1
+	ld	a,0d4h
+	jr	sp.i.1
+	ld	a,0d5h
+	jr	sp.i.1
+	ld	a,0d6h
+	jr	sp.i.1
+	ld	a,0d7h
+	jr	sp.i.1
+	ld	a,0d8h
+sp.i.1:
+;	out	(80h),a
+	halt
+
+; ---------------------------------------------------------
+
+; Get IFF2
+; This routine may not be loaded in page zero
+;
+; return Carry clear, if INTs are enabled.
+;
+	global getiff
+getiff:
+	xor	a		;clear accu and carry
+	push	af		;stack bottom := 00xxh
+	pop	af
+	ld	a,i		;P flag := IFF2
+	ret	pe		;exit carry clear, if enabled
+	dec	sp
+	dec	sp		;has stack bottom been overwritten?
+	pop	af
+	and	a		;if not 00xxh, INTs were
+	ret	nz		;actually enabled
+	scf			;Otherwise, they really are disabled
+	ret
+
+;----------------------------------------------------------------------
+
+	global	selbnk
+
+; a: bank (0..2)
+
+selbnk:
+	push	bc
+	ld	c,a
+	call	getiff
+	push	af
+
+	ld	a,c
+	di
+	ld	(@cbnk),a
+	ld	a,5
+	out	(SIOAC),a
+	ld	a,(mm_sio0)
+	rla
+	srl	c
+	rra
+	out	(SIOAC),a
+	ld	(mm_sio0),a
+
+	ld	a,5
+	out	(SIOBC),a
+	ld	a,(mm_sio1)
+	rla
+	srl	c
+	rra
+	out	(SIOBC),a
+	ld	(mm_sio1),a
+	pop	af
+	pop	bc
+	ret	c			;INTs were disabled
+	ei
+	ret
+
+;----------------------------------------------------------------------
+
+; c: bank (0..2)
+
+	if 0
+
+selbnk:
+	ld	a,(@cbnk)
+	xor	c
+	and	3
+	ret	z		;no change
+
+	call	getiff
+	push	af
+	ld	a,c
+	di
+	ld	(@cbnk),a
+	ld	a,5
+	out	(SIOAC),a
+	ld	a,(mm_sio0)
+	rla
+	srl	c
+	rra
+	out	(SIOAC),a
+	ld	(mm_sio0),a
+
+	ld	a,5
+	out	(SIOBC),a
+	ld	a,(mm_sio1)
+	rla
+	srl	c
+	rra
+	out	(SIOBC),a
+	ld	(mm_sio1),a
+	pop	af
+	ret	nc			;INTs were disabled
+	ei
+	ret
+
+	endif
+
+;----------------------------------------------------------------------
+
+	if 0
+	ex	af,af'
+	push	af
+	ex	af,af'
+
+	rra
+	jr	nc,stbk1
+	ex	af,af'
+	ld	a,5
+	out	(SIOAC),a
+	ld	a,(mm_sio0)
+	rla
+	srl	c
+	rra
+	out	(SIOAC),a
+	ld	(mm_sio1),a
+	ex	af,af'
+
+stbk1:
+	rra
+	jr	nc,stbk2
+	ex	af,af'
+	ld	a,5
+	out	(SIOBC),a
+	ld	a,(mm_sio1)
+	rla
+	srl	c
+	rra
+	out	(SIOBC),a
+	ld	(mm_sio1),a
+	ex	af,af'
+
+stbk2:
+	endif
+
+	global	@cbnk
+	global	mm_sio0, mm_sio1
+
+@cbnk:	db	0		; current bank (0..2)
+mm_sio0:
+	ds	1
+mm_sio1:
+	ds	1
+
+;----------------------------------------------------------------------
+
+curph	defl	$
+	.dephase
+sysrame:
+	.phase curph
+tim_ms:	db	0
+tim_s:	dw	0
+	.dephase
+
+;-----------------------------------------------------
+
+	cseg
+
+	;.phase	0ffc0h
+;ivtab	equ	0ffc0h		; 0ffc0h	;int vector table
+	;.dephase
+
+	;.phase	0fffch
+mark_55AA equ 0fffch
+	;ds	4		; 0fffch
+	;.dephase
+
+
+	end
+
diff --git a/z180/init.180 b/z180/init.180
index 39b03fc..73a77bb 100644
--- a/z180/init.180
+++ b/z180/init.180
@@ -8,6 +8,7 @@
 	extrn romend
 
 
+	global	iobyte
 	global	isv_sw
 
 	include config.inc
@@ -27,7 +28,8 @@ romstart equ	$
 	org	romstart+0
 	jp start
 
-iobyte:	db	0
+iobyte:	db	2
+
 ; restart vectors
 
 rsti	defl	1
diff --git a/z180/msgbuf-a.180 b/z180/msgbuf-a.180
index 36e0871..1bdd826 100644
--- a/z180/msgbuf-a.180
+++ b/z180/msgbuf-a.180
@@ -9,7 +9,9 @@
 	extrn	buf.init
 
 	include config.inc
+	if CPU_Z180
 	include	z180reg.inc
+	endif
 
 ;--------------------------------------------------------------
 
@@ -122,7 +124,7 @@ bp.wait:
 	ld	(ix+o.in_idx),a
 	
 	ld	a,b
-	out0	(AVRINT5),a
+	out	(AVRINT5),a
 	pop	bc
 	pop	hl
 	pop	ix
@@ -165,7 +167,7 @@ ms.wait:
 	ld	(hl),a
 	ld	(ix+o.in_idx),c
 	djnz	ms.ol
-	out0	(AVRINT5),a
+	out	(AVRINT5),a
 	ex	de,hl
 	pop	de
 	pop	bc
-- 
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