From 23f85294a1f0ba1900bd3210965201cf73c04d6c Mon Sep 17 00:00:00 2001
From: Leo C
Date: Thu, 30 Apr 2015 20:46:39 +0200
Subject: Rename file "ser1-i.180" to "asci1-i.180" (Interrupt driver for
 ASCI1)

---
 z180/asci1-i.180 | 258 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 258 insertions(+)
 create mode 100644 z180/asci1-i.180

(limited to 'z180/asci1-i.180')

diff --git a/z180/asci1-i.180 b/z180/asci1-i.180
new file mode 100644
index 0000000..2410e38
--- /dev/null
+++ b/z180/asci1-i.180
@@ -0,0 +1,258 @@
+	page	200
+
+
+	extrn	buf.init
+	extrn	isv_sw
+
+	
+	global	ser.init
+	global	ser.ist,ser.in
+	global	ser.ost,ser.out
+
+;TODO: define a trampoline area somewhere in top ram. 
+rtxisvjmp	equ	0FF60h	;momentan frei...
+
+	include config.inc
+	include	z180reg.inc
+
+
+;-----------------------------------------------------
+
+	dseg
+	
+buf_start:
+	mkbuf	ser1.inbuf,s1.rx_len
+	mkbuf	ser1.outbuf,s1.tx_len
+buf_end:
+
+
+
+;-----------------------------------------------------
+
+	cseg
+;
+; Init Serial I/O for console input and output (ASCI1)
+;
+	
+
+ser.init:
+;	ld	a,i
+;	push	af		;save IFF
+;	di
+
+	xor	a		;
+	out0	(stat1),a	;Disable rx/tx interrupts
+		
+	ld hl,rxtx_src		;move rx and tx isv to common ram
+	ld de,rxtx_dst		;
+	ld bc,rxtx_src_e-rxtx_src ;	
+	ldir			;
+
+	ld hl,rtxisvjmp		;rx/tx int vector
+	ld (ivtab + IV$ASCI1),hl;
+	ld a,0cdh		;
+	ld (rtxisvjmp),a	;
+	ld hl,isv_sw		;
+	ld (rtxisvjmp + 1),hl	;
+	ld hl,rxtxisv		;
+	ld (rtxisvjmp + 3),hl	;
+
+; ASCI1: 8N1, highest baudrate (56700), CTS disabled
+
+	ld	a,M_MPBT 
+	out0	(cntlb1),a
+	ld	a,M_RE + M_TE + M_MOD2
+	out0	(cntla1),a
+	ld	a,M_RIE
+	out0	(stat1),a	;Enable rx interrupts
+
+	ld	ix,ser1.inbuf
+	ld	a,ser1.inbuf.mask
+	call	buf.init
+	ld	ix,ser1.outbuf
+	ld	a,ser1.outbuf.mask
+	call	buf.init
+
+;	pop	af
+;	ret	po
+;	ei
+	ret			;
+
+ser.ist:
+	push	ix
+	ld	ix,ser1.inbuf	;
+
+buf.empty:
+	ld	a,(ix+o.in_idx)	;
+	sub	(ix+o.out_idx)	;
+	pop	ix
+	ret	z
+	or	0ffh
+	ret
+	
+ser.in:
+	push	hl			;11	
+	push	de			;11
+	ld	hl,ser1.inbuf-1		; 9	hl = &rx.out_idx	
+	ld	a,(hl)			; 6	a = rx.out_idx
+	dec	hl			; 4	hl = &rx.in_idx
+	jr	bg.w1
+bg.wait:
+	halt
+bg.w1:
+	cp	(hl)			; 6	while (out_idx==in_idx) 
+	jr	z,bg.wait		; 6 (/8)	;
+
+	ld	e,a			; 4	
+	ld	d,0			; 6
+	inc	de
+	inc	de
+
+	ex	de,hl			; 3
+	add	hl,de			;10
+	ld	l,(hl)			; 6
+	ex	de,hl			; 3	
+
+	inc	a			; 4
+	dec	hl			; 4
+	and	(hl)			; 6	
+	inc	hl			; 4
+	inc	hl			; 4
+	ld	(hl),a			; 7
+	
+	ld	a,e			; 4
+	pop	de			; 9
+	pop	hl			; 9
+	ret				; 9
+					;   153 
+
+ser.ost:
+	push	ix
+	ld	ix,ser1.outbuf		;
+buf.full:
+	ld	a,(ix+o.in_idx)		;
+	inc	a
+	and	(ix+o.mask)
+	sub	(ix+o.out_idx)		;
+	pop	ix
+	ret	z
+	or	0ffh
+	ret
+
+
+ser.out:
+	push	ix
+	ld	ix,ser1.outbuf		;
+buf.put:
+	push	hl			;
+	push	bc
+	push	ix
+	pop	hl
+	ld	a,c
+	ld	c,(ix+o.in_idx)		;
+	ld	b,0
+	add	hl,bc
+	ld	(hl),a
+
+	ld	a,c			;
+	inc	a
+	and	(ix+o.mask)
+bp.wait:
+	cp	(ix+o.out_idx)		;
+	jr	z,bp.wait
+	ld	(ix+o.in_idx),a
+
+	di			;036f
+	in0	a,(stat1)	;0374
+	set	TIE,a		;0377
+	out0	(stat1),a	;0379
+	ei			;037c
+
+	ld	a,b
+	pop	bc
+	pop	hl
+	pop	ix
+	ret
+
+
+;------------------------------------------
+; ASCI 1 Transmit/Receive interupt routines
+; moved to common ram
+
+rxtx_src:
+	dseg
+rxtx_dst:				; (0c097h)  old
+
+rxtxisv:
+	inidat
+	in0 a,(stat1)			;receive flag set?
+	jp p,txisv			;
+
+	in0	d,(rdr1)		;todo: break detection
+	bit	FE,a			;framing error?
+	jr	nz,??ri_1
+	
+	push	ix
+	ld	ix,ser1.inbuf		;
+	ld	hl,ser1.inbuf		;
+	ld	c,(ix+o.in_idx)		;
+	ld	b,0
+	add	hl,bc
+
+	ld	a,c			;
+	inc	a
+	and	(ix+o.mask)
+	cp	(ix+o.out_idx)		;
+	jr	z,??ri_0
+	ld	(hl),d
+	ld	(ix+o.in_idx),a
+??ri_0:
+	pop	ix
+??ri_1:
+	in0	a,(cntla1)		;0705	c0c0
+	res	EFR,a			;0708
+	out0	(cntla1),a		;070a
+	ret
+
+	inidate
+
+txisv:
+	inidat
+	push	ix
+	ld	ix,ser1.outbuf		;
+
+	ld	a,(ix+o.out_idx)	;
+	cp	(ix+o.in_idx)		;
+	jr	z,??ti_2
+
+	ld	hl,ser1.outbuf		;
+	add	a,l
+	ld	l,a
+	jr	nc,??ti_1
+	inc	h
+??ti_1:
+	ld	l,(hl)
+	out0	(tdr1),l		;071b
+	
+	ld	a,(ix+o.out_idx)	;
+	inc	a
+	and	(ix+o.mask)
+	ld	(ix+o.out_idx),a
+	jr	??ti_3
+??ti_2:
+	in0	a,(stat1)		;0730	disable tx-int
+	res	TIE,a			;0733
+	out0	(stat1),a		;0735
+??ti_3:
+	pop	ix
+	ret
+
+	inidate
+
+	cseg
+rxtx_src_e:
+
+
+	end
+
+
-- 
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