[avrcpm.git] / avr / i2c.asm

; I2C (TWI) master interface. 
; This is part of the Z80-CP/M emulator written by Sprite_tm.
;
;    Copyright (C) 2010 Leo C.
;
;    This file is part of avrcpm.
;
;    avrcpm is free software: you can redistribute it and/or modify it
;    under the terms of the GNU General Public License as published by
;    the Free Software Foundation, either version 3 of the License, or
;    (at your option) any later version.
;
;    avrcpm is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License
;    along with avrcpm.  If not, see <http://www.gnu.org/licenses/>.
;
;    $Id$
;

#if I2C 

/* General TWI Master status codes */
#define TWI_START                  0x08  /* START has been transmitted */
#define TWI_REP_START              0x10  /* Repeated START has been transmitted */
#define TWI_ARB_LOST               0x38  /* Arbitration lost */

/* TWI Master Transmitter status codes */
#define TWI_MTX_ADR_ACK            0x18  /* SLA+W has been transmitted and ACK received */
#define TWI_MTX_ADR_NACK           0x20  /* SLA+W has been transmitted and NACK received */
#define TWI_MTX_DATA_ACK           0x28  /* Data byte has been transmitted and ACK received */
#define TWI_MTX_DATA_NACK          0x30  /* Data byte has been transmitted and NACK received */

/* TWI Master Receiver status codes */
#define TWI_MRX_ADR_ACK            0x40  /* SLA+R has been transmitted and ACK received */
#define TWI_MRX_ADR_NACK           0x48  /* SLA+R has been transmitted and NACK received */
#define TWI_MRX_DATA_ACK           0x50  /* Data byte has been received and ACK transmitted */
#define TWI_MRX_DATA_NACK          0x58  /* Data byte has been received and NACK transmitted */

/* TWI Miscellaneous status codes */
#define TWI_NO_STATE               0xF8  /* No relevant state information available */
#define TWI_BUS_ERROR              0x00  /* Bus error due to an illegal START or STOP condition */


#define I2C_BR ((F_CPU / (2 * I2C_CLOCK)) - 8) /* I2C Bit Rate */

;----------------------------------------------------------------------
;
; TWINT: TWI Interrupt Flag
; TWEA:  TWI Enable Acknowledge Bit
; TWSTA: TWI START Condition Bit
; TWSTO: TWI STOP Condition Bit
; TWEN:  TWI Enable Bit
; TWIE:  TWI Interrupt Enable
; 
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|           (1<<TWEA)
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
; 
; default:
; 	(1<<TWEN)|          (1<<TWINT)|           (1<<TWSTO)
; 
; Init:
; 	(1<<TWEN)
; 
; start read/write:
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
; 	(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
; 
; wait ready:
; 	 (1<<TWIE)|(1<<TWSTO)
;
;----------------------------------------------------------------------
;
;i2c_result	<  0	Error. 
;			-1 general/unknown error
;			-2 time out 
;		>= 0	No error
;			> 0 status tbd.
;
;----------------------------------------------------------------------

	.dseg

i2c_var:
i2ci_idx:
	.byte	1
i2c_result:
	.byte	1
i2c_bufcnt:
	.byte	1
i2c_buf:
	.byte	I2C_BUFSIZE

	.equ oi2ci_idx   = 0
	.equ oi2c_result = 1
	.equ oi2c_bufcnt = 2
	.equ oi2c_buf    = 3

;------------------------------------------------------------------

	.cseg


	INTERRUPT TWIaddr
	
	push	temp
	in	temp,sreg
	push	temp
	push	temp2
	push	zh
	push	zl

	ldiw	z,i2c_var
	ldd	temp2,z+oi2ci_idx			

	inm8	temp,TWSR
	cpi	temp,TWI_START
	breq	i2ci_START
	cpi	temp,TWI_REP_START
	breq	i2ci_REP_START
	cpi	temp,TWI_MTX_ADR_ACK
	breq	i2ci_MTX_ADR_ACK
	cpi	temp,TWI_MTX_DATA_ACK
	breq	i2ci_MTX_DATA_ACK
	cpi	temp,TWI_MRX_ADR_ACK
	breq	i2ci_MRX_ADR_ACK
	cpi	temp,TWI_MRX_DATA_ACK
	breq	i2ci_MRX_DATA_ACK
	cpi	temp,TWI_MRX_DATA_NACK
	breq	i2ci_MRX_DATA_NACK
	rjmp	i2ci_default

i2ci_START:
i2ci_REP_START:
	clr	temp2					;reset buffer pointer
i2ci_MTX_ADR_ACK:
i2ci_MTX_DATA_ACK:
	ldd	temp,z+oi2c_bufcnt
	cp	temp2,temp				;all bytes tranmited?
	brsh	i2ci_12					; yes
	add	zl,temp2
	adc	zh,_0
	inc	temp2
	ldd	temp,z+oi2c_buf				;next byte
	outm8	TWDR,temp
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
	rjmp	i2ci_end

i2ci_12:
	std	z+oi2c_result,_0			;done
	rjmp	i2ci_default				;stop transceiver

i2ci_MRX_DATA_ACK:
	add	zl,temp2
	adc	zh,_0
	inc	temp2
	inm8	temp,TWDR
	std	z+oi2c_buf,temp
i2ci_MRX_ADR_ACK:
	lds	temp,i2c_bufcnt
	dec	temp
	cp	temp2,temp
	brsh	i2ci_32
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)
	rjmp	i2ci_end
i2ci_32:
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)
	rjmp	i2ci_end

i2ci_MRX_DATA_NACK:
	std	z+oi2c_result,_0			;result = ok
	add	zl,temp2
	adc	zh,_0
	inm8	temp,TWDR
	std	z+oi2c_buf,temp
;	fall thru

i2ci_default:
	ldi	temp,(1<<TWEN)|(1<<TWINT)|(1<<TWSTO)

i2ci_end: 
	outm8	TWCR,temp
	sts	i2ci_idx,temp2
	pop	zl
	pop	zh
	pop	temp2
	pop	temp
	out	sreg,temp
	pop	temp
	reti

;------------------------------------------------------------------

i2c_init:
	ldi	temp,I2C_BR
	outm8	TWBR,temp
	outm8	TWDR,_255			;
	ldi	temp,(1<<TWEN)			;Enable TWI, disable TWI interrupt.
	outm8	TWCR,temp

	sts	i2c_result,_0
	ret

;------------------------------------------------------------------

i2c_waitready:

	ldi	temp,30
	sts	delay_timer1,temp
i2c_wrl:
	inm8	temp,TWCR
	andi	temp,(1<<TWIE)|(1<<TWSTO)
	breq	i2c_wre
	lds	temp,delay_timer1
	tst	temp
	brne	i2c_wrl

	ldi	temp,-2
	sts	i2c_result,temp
i2c_wre:
	tst	temp
	ret

;------------------------------------------------------------------
;
; 	z:	Pointer to the data to write.
;		First byte is slave address
;	temp2:	Number of bytes to write including address byte.
;

i2c_write:

	rcall	i2c_waitready
	brmi	i2c_we
	push	zh
	push	zl
	push	xh
	push	xl

	ldiw	x,i2c_result
	st	x+,_255				;result = not ok
	st	x+,temp2			;store size
	ld	temp,z+
	cbr	temp,0x01
i2c_wl:
	st	x+,temp
	dec	temp2
	breq	i2c_wle
	ld	temp,z+
	rjmp	i2c_wl
i2c_wle:
	; Enable TWI, TWI int and initiate start condition
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
	outm8	TWCR,temp

	pop	xl
	pop	xh
	pop	zl
	pop	zh
i2c_we:
	ret


;------------------------------------------------------------------
;
; 	z:	Pointer to data buffer.
;		First byte of buffer is slave address
;	temp2:	Number of bytes to write including address byte.
;
;	temp:	return (fail = 0, else succsess)

i2c_read:

	rcall	i2c_waitready
	brmi	i2c_re

	push	zh
	push	zl
	push	xh
	push	xl
	ldiw	x,i2c_result
	st	x+,_255				;result = not ok
	st	x+,temp2			;store size
	ld	temp,z
	sbr	temp,0x01
	st	x,temp

	; Enable TWI, TWI int and initiate start condition
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
	outm8	TWCR,temp

	rcall	i2c_waitready

	lds	temp,i2c_result
	sbrc	temp,7
	rjmp	i2c_ex				;
i2c_rl:
	ld	temp,x+
	st	z+,temp
	dec	temp2
	brne	i2c_rl

i2c_ex:
	pop	xl
	pop	xh
	pop	zl
	pop	zh
i2c_re:
	lds	temp,i2c_result
	ret

;------------------------------------------------------------------

	.dseg

vi2c_stat:
	.byte	1
vi2c_blen:
	.byte	1
vi2c_addr:
	.byte	2

	.cseg

vi2c_stat_get:
	lds	temp,i2c_result
	ret

vi2c_param_get:
	ldiw	z,vi2c_blen
	add	zl,temp3
	adc	zh,_0
	ld	temp,z
	ret

vi2c_param_set:
	ldiw	z,vi2c_blen
	add	zl,temp3
	adc	zh,_0
	st	z,temp
	ret

;------------------------------------------------------------------
;
; 	x:	Pointer to the data buffer.
;		First byte is slave address
;	temp3:	Number of bytes to write including address byte.
;

vi2c_read:

	rcall	i2c_waitready
	brmi	vi2c_rex

	ldiw	z,i2c_var
	std	z+oi2c_result,_255		;result = not ok
	lds	temp3,vi2c_blen
	std	z+oi2c_bufcnt,temp3		;store size
	adiw	z,oi2c_buf
	ldsw	x,vi2c_addr
	lcall	dram_read_pp
	sbr	temp,0x01
	st	z+,temp
	dec	temp3

	; Enable TWI, TWI int and initiate start condition
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
	outm8	TWCR,temp

	rcall	i2c_waitready

	lds	temp,i2c_result
	sbrc	temp,7
	rjmp	vi2c_rex				;
vi2c_rl:
	ld	temp,z+
	lcall	dram_write_pp
	dec	temp3
	brne	vi2c_rl

vi2c_rex:
	ret

;------------------------------------------------------------------
;
; 	x:	Pointer to the data to write.
;		First byte is slave address
;	temp2:	Number of bytes to write including address byte.
;

vi2c_write:

	rcall	i2c_waitready
	brmi	vi2c_wex
	ldiw	z,i2c_var
	std	z+oi2c_result,_255		;result = not ok
	lds	temp3,vi2c_blen
	std	z+oi2c_bufcnt,temp3		;store size
	adiw	z,oi2c_buf
	ldsw	x,vi2c_addr
	lcall	dram_read_pp
	cbr	temp,0x01
vi2c_wl:
	st	z+,temp
	dec	temp3
	breq	vi2c_wle
	lcall	dram_read_pp
	rjmp	vi2c_wl
vi2c_wle:
	; Enable TWI, TWI int and initiate start condition
	ldi	temp,(1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWSTA)
	outm8	TWCR,temp
vi2c_wex:
	ret

;------------------------------------------------------------------


vi2c_ctrl:
	cpi	temp,1
	brne	vi2c_c1
	rjmp	vi2c_read

vi2c_c1:
	cpi	temp,2
	brne	vi2c_c2
	rjmp	vi2c_write
vi2c_c2:
vi2c_ce:
	ret

;------------------------------------------------------------------


pcf8574_in:
	; make a buffer on stack
	push	_255			;place holder for input value
	in	zh,sph
	in	zl,spl
	ldi	temp,0x20		;pcf8574 address (7 bit)
	add	temp,temp3
	lsl	temp
	push	temp			;slave address
	ldi	temp2,2
	rcall	i2c_read
	pop	temp			;remove slave address from stack
	pop	temp			;return input value
	ret

pcf8574_out:
	; make a buffer on stack
	push	temp			;output value
	in	zh,sph
	in	zl,spl
	ldi	temp,0x20		;pcf8574 address (7 bit)
	add	temp,temp3
	lsl	temp
	push	temp			;slave address
	ldi	temp2,2
	rcall	i2c_write
	pop	temp			;remove buffer from stack
	pop	temp			;
	ret


#endif /* I2C */
;------------------------------------------------------------------
; vim:set ts=8 noet nowrap
Commit	Line	Data
d8fa6a36 L	1	; I2C (TWI) master interface.
	2	; This is part of the Z80-CP/M emulator written by Sprite_tm.
	3	;
	4	; Copyright (C) 2010 Leo C.
	5	;
	6	; This file is part of avrcpm.
	7	;
	8	; avrcpm is free software: you can redistribute it and/or modify it
	9	; under the terms of the GNU General Public License as published by
	10	; the Free Software Foundation, either version 3 of the License, or
	11	; (at your option) any later version.
	12	;
	13	; avrcpm is distributed in the hope that it will be useful,
	14	; but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	; GNU General Public License for more details.
	17	;
	18	; You should have received a copy of the GNU General Public License
	19	; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
	20	;
	21	; $Id$
	22	;
	23
	24	#if I2C
	25
	26	/* General TWI Master status codes */
	27	#define TWI_START 0x08 /* START has been transmitted */
	28	#define TWI_REP_START 0x10 /* Repeated START has been transmitted */
	29	#define TWI_ARB_LOST 0x38 /* Arbitration lost */
	30
	31	/* TWI Master Transmitter status codes */
	32	#define TWI_MTX_ADR_ACK 0x18 /* SLA+W has been transmitted and ACK received */
	33	#define TWI_MTX_ADR_NACK 0x20 /* SLA+W has been transmitted and NACK received */
	34	#define TWI_MTX_DATA_ACK 0x28 /* Data byte has been transmitted and ACK received */
	35	#define TWI_MTX_DATA_NACK 0x30 /* Data byte has been transmitted and NACK received */
	36
	37	/* TWI Master Receiver status codes */
	38	#define TWI_MRX_ADR_ACK 0x40 /* SLA+R has been transmitted and ACK received */
	39	#define TWI_MRX_ADR_NACK 0x48 /* SLA+R has been transmitted and NACK received */
	40	#define TWI_MRX_DATA_ACK 0x50 /* Data byte has been received and ACK transmitted */
	41	#define TWI_MRX_DATA_NACK 0x58 /* Data byte has been received and NACK transmitted */
	42
	43	/* TWI Miscellaneous status codes */
	44	#define TWI_NO_STATE 0xF8 /* No relevant state information available */
	45	#define TWI_BUS_ERROR 0x00 /* Bus error due to an illegal START or STOP condition */
	46
	47
	48	#define I2C_BR ((F_CPU / (2 * I2C_CLOCK)) - 8) /* I2C Bit Rate */
	49
	50	;----------------------------------------------------------------------
	51	;
	52	; TWINT: TWI Interrupt Flag
	53	; TWEA: TWI Enable Acknowledge Bit
	54	; TWSTA: TWI START Condition Bit
	55	; TWSTO: TWI STOP Condition Bit
	56	; TWEN: TWI Enable Bit
	57	; TWIE: TWI Interrupt Enable
	58	;
	59	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)
	60	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\| (1<<TWEA)
	61	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)
	62	;
	63	; default:
	64	; (1<<TWEN)\| (1<<TWINT)\| (1<<TWSTO)
65	;
66	; Init:
67	; (1<<TWEN)
68	;
69	; start read/write:
70	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
71	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
72	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
73	; (1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
74	;
75	; wait ready:
76	; (1<<TWIE)\|(1<<TWSTO)
79986122 L	77	;
	78	;----------------------------------------------------------------------
	79	;
	80	;i2c_result < 0 Error.
	81	; -1 general/unknown error
	82	; -2 time out
	83	; >= 0 No error
	84	; > 0 status tbd.
	85	;
d8fa6a36 L	86	;----------------------------------------------------------------------
	87
	88	.dseg
	89
	90	i2c_var:
	91	i2ci_idx:
	92	.byte 1
	93	i2c_result:
	94	.byte 1
	95	i2c_bufcnt:
	96	.byte 1
	97	i2c_buf:
	98	.byte I2C_BUFSIZE
	99
	100	.equ oi2ci_idx = 0
	101	.equ oi2c_result = 1
	102	.equ oi2c_bufcnt = 2
	103	.equ oi2c_buf = 3
	104
	105	;------------------------------------------------------------------
	106
	107	.cseg
	108
	109
	110	INTERRUPT TWIaddr
	111
	112	push temp
	113	in temp,sreg
	114	push temp
	115	push temp2
	116	push zh
	117	push zl
	118
	119	ldiw z,i2c_var
	120	ldd temp2,z+oi2ci_idx
	121
	122	inm8 temp,TWSR
d8fa6a36 L	123	cpi temp,TWI_START
	124	breq i2ci_START
	125	cpi temp,TWI_REP_START
	126	breq i2ci_REP_START
	127	cpi temp,TWI_MTX_ADR_ACK
	128	breq i2ci_MTX_ADR_ACK
	129	cpi temp,TWI_MTX_DATA_ACK
	130	breq i2ci_MTX_DATA_ACK
	131	cpi temp,TWI_MRX_ADR_ACK
	132	breq i2ci_MRX_ADR_ACK
	133	cpi temp,TWI_MRX_DATA_ACK
	134	breq i2ci_MRX_DATA_ACK
	135	cpi temp,TWI_MRX_DATA_NACK
	136	breq i2ci_MRX_DATA_NACK
	137	rjmp i2ci_default
	138
	139	i2ci_START:
	140	i2ci_REP_START:
	141	clr temp2 ;reset buffer pointer
	142	i2ci_MTX_ADR_ACK:
	143	i2ci_MTX_DATA_ACK:
	144	ldd temp,z+oi2c_bufcnt
79986122 L	145	cp temp2,temp ;all bytes tranmited?
79986122 L	146	brsh i2ci_12 ; yes
d8fa6a36 L	147	add zl,temp2
	148	adc zh,_0
	149	inc temp2
79986122	150	ldd temp,z+oi2c_buf ;next byte
d8fa6a36 L	151	outm8 TWDR,temp
	152	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)
	153	rjmp i2ci_end
	154
	155	i2ci_12:
79986122 L	156	std z+oi2c_result,_0 ;done
79986122 L	157	rjmp i2ci_default ;stop transceiver
d8fa6a36 L	158
	159	i2ci_MRX_DATA_ACK:
	160	add zl,temp2
	161	adc zh,_0
	162	inc temp2
	163	inm8 temp,TWDR
	164	std z+oi2c_buf,temp
	165	i2ci_MRX_ADR_ACK:
	166	lds temp,i2c_bufcnt
	167	dec temp
	168	cp temp2,temp
	169	brsh i2ci_32
	170	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWEA)
	171	rjmp i2ci_end
	172	i2ci_32:
	173	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)
	174	rjmp i2ci_end
	175
	176	i2ci_MRX_DATA_NACK:
79986122	177	std z+oi2c_result,_0 ;result = ok
d8fa6a36 L	178	add zl,temp2
	179	adc zh,_0
	180	inm8 temp,TWDR
	181	std z+oi2c_buf,temp
	182	; fall thru
	183
	184	i2ci_default:
	185	ldi temp,(1<<TWEN)\|(1<<TWINT)\|(1<<TWSTO)
	186
	187	i2ci_end:
	188	outm8 TWCR,temp
	189	sts i2ci_idx,temp2
	190	pop zl
	191	pop zh
	192	pop temp2
	193	pop temp
	194	out sreg,temp
	195	pop temp
	196	reti
	197
	198	;------------------------------------------------------------------
	199
	200	i2c_init:
	201	ldi temp,I2C_BR
	202	outm8 TWBR,temp
	203	outm8 TWDR,_255 ;
79986122	204	ldi temp,(1<<TWEN) ;Enable TWI, disable TWI interrupt.
d8fa6a36 L	205	outm8 TWCR,temp
d8fa6a36 L	206
79986122	207	sts i2c_result,_0
d8fa6a36 L	208	ret
	209
	210	;------------------------------------------------------------------
	211
	212	i2c_waitready:
79986122 L	213
	214	ldi temp,30
	215	sts delay_timer1,temp
	216	i2c_wrl:
d8fa6a36 L	217	inm8 temp,TWCR
d8fa6a36 L	218	andi temp,(1<<TWIE)\|(1<<TWSTO)
79986122 L	219	breq i2c_wre
	220	lds temp,delay_timer1
	221	tst temp
	222	brne i2c_wrl
	223
	224	ldi temp,-2
	225	sts i2c_result,temp
	226	i2c_wre:
	227	tst temp
d8fa6a36 L	228	ret
	229
	230	;------------------------------------------------------------------
	231	;
	232	; z: Pointer to the data to write.
	233	; First byte is slave address
	234	; temp2: Number of bytes to write including address byte.
	235	;
	236
	237	i2c_write:
d8fa6a36	238
79986122 L	239	rcall i2c_waitready
79986122 L	240	brmi i2c_we
d8fa6a36 L	241	push zh
	242	push zl
	243	push xh
	244	push xl
	245
d8fa6a36	246	ldiw x,i2c_result
79986122	247	st x+,_255 ;result = not ok
d8fa6a36 L	248	st x+,temp2 ;store size
	249	ld temp,z+
	250	cbr temp,0x01
	251	i2c_wl:
	252	st x+,temp
	253	dec temp2
	254	breq i2c_wle
	255	ld temp,z+
	256	rjmp i2c_wl
	257	i2c_wle:
	258	; Enable TWI, TWI int and initiate start condition
	259	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	260	outm8 TWCR,temp
	261
	262	pop xl
	263	pop xh
	264	pop zl
	265	pop zh
79986122	266	i2c_we:
d8fa6a36 L	267	ret
	268
	269
	270	;------------------------------------------------------------------
	271	;
	272	; z: Pointer to data buffer.
	273	; First byte of buffer is slave address
	274	; temp2: Number of bytes to write including address byte.
	275	;
	276	; temp: return (fail = 0, else succsess)
	277
	278	i2c_read:
79986122	279
d8fa6a36	280	rcall i2c_waitready
79986122	281	brmi i2c_re
d8fa6a36 L	282
	283	push zh
	284	push zl
	285	push xh
	286	push xl
	287	ldiw x,i2c_result
79986122	288	st x+,_255 ;result = not ok
d8fa6a36 L	289	st x+,temp2 ;store size
	290	ld temp,z
	291	sbr temp,0x01
	292	st x,temp
	293
	294	; Enable TWI, TWI int and initiate start condition
	295	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	296	outm8 TWCR,temp
	297
	298	rcall i2c_waitready
	299
d8fa6a36	300	lds temp,i2c_result
79986122 L	301	sbrc temp,7
79986122 L	302	rjmp i2c_ex ;
d8fa6a36 L	303	i2c_rl:
	304	ld temp,x+
	305	st z+,temp
	306	dec temp2
	307	brne i2c_rl
	308
	309	i2c_ex:
d8fa6a36 L	310	pop xl
	311	pop xh
	312	pop zl
	313	pop zh
79986122 L	314	i2c_re:
79986122 L	315	lds temp,i2c_result
d8fa6a36 L	316	ret
	317
	318	;------------------------------------------------------------------
	319
	320	.dseg
	321
	322	vi2c_stat:
	323	.byte 1
	324	vi2c_blen:
	325	.byte 1
	326	vi2c_addr:
	327	.byte 2
	328
	329	.cseg
	330
	331	vi2c_stat_get:
79986122	332	lds temp,i2c_result
d8fa6a36 L	333	ret
	334
	335	vi2c_param_get:
	336	ldiw z,vi2c_blen
	337	add zl,temp3
	338	adc zh,_0
	339	ld temp,z
	340	ret
	341
	342	vi2c_param_set:
	343	ldiw z,vi2c_blen
	344	add zl,temp3
	345	adc zh,_0
	346	st z,temp
	347	ret
	348
	349	;------------------------------------------------------------------
	350	;
	351	; x: Pointer to the data buffer.
	352	; First byte is slave address
	353	; temp3: Number of bytes to write including address byte.
	354	;
	355
	356	vi2c_read:
79986122	357
d8fa6a36	358	rcall i2c_waitready
79986122	359	brmi vi2c_rex
d8fa6a36 L	360
d8fa6a36 L	361	ldiw z,i2c_var
79986122	362	std z+oi2c_result,_255 ;result = not ok
d8fa6a36 L	363	lds temp3,vi2c_blen
	364	std z+oi2c_bufcnt,temp3 ;store size
	365	adiw z,oi2c_buf
	366	ldsw x,vi2c_addr
	367	lcall dram_read_pp
	368	sbr temp,0x01
	369	st z+,temp
	370	dec temp3
	371
	372	; Enable TWI, TWI int and initiate start condition
	373	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	374	outm8 TWCR,temp
	375
	376	rcall i2c_waitready
	377
	378	lds temp,i2c_result
79986122 L	379	sbrc temp,7
79986122 L	380	rjmp vi2c_rex ;
d8fa6a36 L	381	vi2c_rl:
	382	ld temp,z+
	383	lcall dram_write_pp
	384	dec temp3
	385	brne vi2c_rl
	386
79986122	387	vi2c_rex:
d8fa6a36 L	388	ret
	389
	390	;------------------------------------------------------------------
	391	;
	392	; x: Pointer to the data to write.
	393	; First byte is slave address
	394	; temp2: Number of bytes to write including address byte.
	395	;
	396
	397	vi2c_write:
79986122	398
d8fa6a36	399	rcall i2c_waitready
79986122	400	brmi vi2c_wex
d8fa6a36	401	ldiw z,i2c_var
79986122	402	std z+oi2c_result,_255 ;result = not ok
d8fa6a36 L	403	lds temp3,vi2c_blen
	404	std z+oi2c_bufcnt,temp3 ;store size
	405	adiw z,oi2c_buf
	406	ldsw x,vi2c_addr
	407	lcall dram_read_pp
	408	cbr temp,0x01
	409	vi2c_wl:
	410	st z+,temp
	411	dec temp3
	412	breq vi2c_wle
	413	lcall dram_read_pp
	414	rjmp vi2c_wl
	415	vi2c_wle:
	416	; Enable TWI, TWI int and initiate start condition
	417	ldi temp,(1<<TWEN)\|(1<<TWIE)\|(1<<TWINT)\|(1<<TWSTA)
	418	outm8 TWCR,temp
79986122	419	vi2c_wex:
d8fa6a36 L	420	ret
d8fa6a36 L	421
79986122 L	422	;------------------------------------------------------------------
79986122 L	423
d8fa6a36 L	424
	425	vi2c_ctrl:
	426	cpi temp,1
	427	brne vi2c_c1
79986122 L	428	rjmp vi2c_read
79986122 L	429
d8fa6a36 L	430	vi2c_c1:
d8fa6a36 L	431	cpi temp,2
79986122 L	432	brne vi2c_c2
79986122 L	433	rjmp vi2c_write
d8fa6a36	434	vi2c_c2:
d8fa6a36	435	vi2c_ce:
d8fa6a36 L	436	ret
	437
	438	;------------------------------------------------------------------
	439
	440
	441	pcf8574_in:
	442	; make a buffer on stack
	443	push _255 ;place holder for input value
	444	in zh,sph
	445	in zl,spl
	446	ldi temp,0x20 ;pcf8574 address (7 bit)
	447	add temp,temp3
	448	lsl temp
	449	push temp ;slave address
	450	ldi temp2,2
	451	rcall i2c_read
	452	pop temp ;remove slave address from stack
	453	pop temp ;return input value
	454	ret
	455
	456	pcf8574_out:
	457	; make a buffer on stack
	458	push temp ;output value
	459	in zh,sph
	460	in zl,spl
	461	ldi temp,0x20 ;pcf8574 address (7 bit)
	462	add temp,temp3
	463	lsl temp
	464	push temp ;slave address
	465	ldi temp2,2
	466	rcall i2c_write
	467	pop temp ;remove buffer from stack
	468	pop temp ;
	469	ret
	470
	471
	472	#endif /* I2C */
	473	;------------------------------------------------------------------
	474	; vim:set ts=8 noet nowrap
	475