projects / avrcpm.git / blame
| Commit | Line | Data |
|---|---|---|
| 9c15f366 L |
1 | ; Configuration, hardware definition, ... |
| 2 | ; | |
| 3 | ; Copyright (C) 2010 Sprite_tm | |
| 4 | ; Copyright (C) 2010 Leo C. | |
| 5 | ; | |
| 6 | ; This file is part of avrcpm. | |
| 7 | ; | |
| 8 | ; avrcpm is free software: you can redistribute it and/or modify it | |
| 9 | ; under the terms of the GNU General Public License as published by | |
| 10 | ; the Free Software Foundation, either version 3 of the License, or | |
| 11 | ; (at your option) any later version. | |
| 12 | ; | |
| 13 | ; avrcpm is distributed in the hope that it will be useful, | |
| 14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | ; GNU General Public License for more details. | |
| 17 | ; | |
| 18 | ; You should have received a copy of the GNU General Public License | |
| 19 | ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>. | |
| 20 | ; | |
| 21 | ; $Id$ | |
| 22 | ; | |
| 23 | ||
| 24 | ||
| 25 | #define VMAJOR 2 /* Version number */ | |
| cf6e81d8 | 26 | #define VMINOR 2 |
| 9c15f366 L |
27 | |
| 28 | #ifndef DRAM_8BIT | |
| 678fc0b0 | 29 | #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */ |
| 9c15f366 L |
30 | #endif |
| 31 | #ifndef F_CPU | |
| 32 | #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ | |
| 33 | #endif | |
| 34 | #ifndef BAUD | |
| 35 | #define BAUD 38400 /* console baud rate */ | |
| 36 | #endif | |
| 37 | ||
| 9c15f366 | 38 | #define K 1024 |
| 637689de | 39 | #define M 1024*K |
| 9c15f366 L |
40 | |
| 41 | ;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */ | |
| 42 | #define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */ | |
| 43 | ||
| 3f75a0d3 L |
44 | #ifndef FAT16_SUPPORT |
| 45 | #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */ | |
| 46 | #endif /* which may contain CP/M image files. */ | |
| b741422e L |
47 | #define RAMDISKCNT 0 /* Number of RAM disks */ |
| 48 | #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */ | |
| 9c15f366 L |
49 | |
| 50 | #define PARTID 0x52 /* Partition table id */ | |
| 51 | /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */ | |
| 52 | #define IPLADDR 0x2000 /* Bootloader load address */ | |
| 53 | ||
| 54 | #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */ | |
| 55 | #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */ | |
| 56 | /* Most drams need 1/15.6µs. */ | |
| 57 | #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */ | |
| 58 | #define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */ | |
| 59 | ||
| 60 | ||
| 61 | ||
| 62 | #define EM_Z80 0 /* we don't have any z80 instructions yet */ | |
| 63 | ||
| dd7aea8c L |
64 | .equ BOOTWAIT = 1 |
| 65 | .equ MEMTEST = 1 | |
| 66 | .equ MEMFILL = 1 | |
| e832c81a L |
67 | .equ MMC_DEBUG = 0 /* Increase for more debugging */ |
| 68 | .equ FAT16_DEBUG = 0 | |
| a5b2e36e | 69 | .equ FAT16_RWDEBUG = 0 |
| b2017655 | 70 | .equ FAT16_DBG_FAT = 0 |
| e832c81a L |
71 | .equ DISK_DEBUG = 0 /* Increase for more debugging */ |
| 72 | .equ HOSTRW_DEBUG = 0 | |
| dd7aea8c L |
73 | .equ HEAP_DEBUG = 0 |
| 74 | .equ PORT_DEBUG = 0 | |
| 75 | .equ INS_DEBUG = 0 | |
| e832c81a L |
76 | .equ STACK_DBG = 0 |
| 77 | .equ PRINT_PC = 0 | |
| 9c15f366 L |
78 | |
| 79 | #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */ | |
| 80 | ||
| 81 | #define MEMFILL_VAL 0xCB /* Fill ram with cbs, which will trigger an invalid opcode error. */ | |
| 82 | #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */ | |
| 83 | #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */ | |
| 84 | ||
| 85 | ;----------------------------------------------------------------------- | |
| 86 | ; Port declarations | |
| 87 | ||
| 88 | #if DRAM_8BIT /* Implies software uart */ | |
| 89 | ||
| 90 | ;Port D | |
| 91 | .equ RAM_D0 = 0 | |
| 92 | .equ RAM_D1 = 1 | |
| 93 | .equ RAM_D2 = 2 | |
| 94 | .equ RAM_D3 = 3 | |
| 95 | .equ RAM_D4 = 4 | |
| 96 | .equ RAM_D5 = 5 | |
| 97 | .equ RAM_D6 = 6 | |
| 98 | .equ RAM_D7 = 7 | |
| 99 | .equ RAM_A0 = 0 | |
| 100 | .equ RAM_A1 = 1 | |
| 101 | .equ RAM_A2 = 2 | |
| 102 | .equ RAM_A3 = 3 | |
| 103 | .equ RAM_A4 = 4 | |
| 104 | .equ RAM_A5 = 5 | |
| 105 | .equ RAM_A6 = 6 | |
| 106 | .equ RAM_A7 = 7 | |
| 107 | ||
| 108 | ;Port B | |
| 109 | .equ MMC_MOSI = 3 | |
| 110 | .equ MMC_MISO = 4 | |
| 111 | .equ MMC_SCK = 5 | |
| 112 | .equ RAM_A8 = 3 | |
| 113 | .equ RAM_A9 = 4 | |
| 114 | .equ RAM_A10 = 5 | |
| 115 | ||
| 116 | .equ RXD = 0 | |
| 117 | .equ TXD = 1 | |
| 118 | .equ MMC_CS = 2 | |
| 119 | ||
| 120 | .equ P_MMC_CS = PORTB | |
| 121 | .equ P_A8 = PORTB | |
| 122 | .equ P_RXD = PORTB | |
| 123 | ||
| 124 | ;Port C | |
| 125 | .equ RAM_RAS = 0 | |
| 126 | .equ RAM_CAS = 1 | |
| 127 | .equ RAM_OE = 2 | |
| 128 | .equ RAM_W = 3 | |
| 129 | ||
| 130 | .equ P_RAS = PORTC | |
| 131 | .equ P_CAS = PORTC | |
| 132 | .equ P_OE = PORTC | |
| 133 | .equ P_W = PORTC | |
| 134 | ||
| 135 | ||
| 136 | #else /* 4 bit RAM, hardware uart */ | |
| 137 | ||
| 138 | ; Port D | |
| 139 | .equ RXD = 0 | |
| 140 | .equ TXD = 1 | |
| 141 | .equ RAM_OE = 2 | |
| 142 | .equ RAM_A8 = 3 | |
| 143 | .equ MMC_CS = 4 | |
| 144 | .equ RAM_A5 = 5 | |
| 145 | .equ RAM_A6 = 6 | |
| 146 | .equ RAM_A7 = 7 | |
| 147 | ||
| 148 | .equ P_RXD = PORTD | |
| 149 | .equ P_OE = PORTD | |
| 150 | .equ P_A8 = PORTD | |
| 151 | .equ P_MMC_CS = PORTD | |
| 152 | .equ P_AH = PORTD | |
| 153 | ; RAM_A[7..5] | |
| 154 | .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5) | |
| 155 | .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK | |
| 156 | ||
| 157 | ||
| 158 | ;Port B | |
| 159 | .equ RAM_A4 = 0 | |
| 160 | .equ RAM_A3 = 1 | |
| 161 | .equ RAM_A2 = 2 | |
| 162 | .equ RAM_A1 = 3 | |
| 163 | .equ MMC_MOSI = 3 | |
| 164 | .equ RAM_A0 = 4 | |
| 165 | .equ MMC_MISO = 4 | |
| 166 | .equ RAM_RAS = 5 | |
| 167 | .equ MMC_SCK = 5 | |
| 168 | ||
| 169 | .equ P_RAS = PORTB | |
| 170 | .equ P_AL = PORTB | |
| 171 | ; RAM_A[4..0] | |
| 172 | .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0) | |
| 173 | .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK | |
| 174 | ||
| 175 | ;Port C | |
| 176 | .equ RAM_D0 = 0 | |
| 177 | .equ RAM_D1 = 1 | |
| 178 | .equ RAM_D2 = 2 | |
| 179 | .equ RAM_D3 = 3 | |
| 180 | .equ RAM_W = 4 | |
| 181 | .equ RAM_CAS = 5 | |
| 182 | ||
| 183 | .equ P_DQ = PORTC | |
| 184 | .equ P_W = PORTC | |
| 185 | .equ P_CAS = PORTC | |
| 186 | ||
| 187 | .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0) | |
| 188 | .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W) | |
| 189 | ||
| 190 | #endif /* DRAM_8BIT */ | |
| 191 | ||
| 192 | ||
| 193 | ;----------------------------------------------------------------------- | |
| 194 | ;Register definitions | |
| 195 | ||
| 196 | .def _tmp0 = r0 | |
| 197 | .def _tmp1 = r1 | |
| 198 | ||
| 199 | .def _RAS0 = r2 | |
| 200 | .def _CAS0 = r3 | |
| 201 | .def _OE = r4 | |
| 202 | .def _WE = r5 | |
| 203 | .def _255 = r6 | |
| 204 | .def _0 = r7 | |
| 205 | .def z_a = r9 | |
| 206 | ;.def stx_bitcount = r9 | |
| 207 | ;.def stx_dr = r10 | |
| 208 | .def srx_lastedgel = r10 | |
| 209 | .def srx_lastedgeh = r11 | |
| 210 | ||
| 211 | .def insstore= r8 ; | |
| 212 | ;.def insop = r13 ; | |
| 213 | .def insdecl = r12 ; | |
| 214 | .def insdech = r13 ; | |
| 215 | .def z_spl = r14 | |
| 216 | .def z_sph = r15 ; | |
| 217 | .def temp = r16 ; | |
| 218 | .def temp2 = r17 ; | |
| 219 | .def temp3 = r18 | |
| 220 | .def temp4 = r19 | |
| 221 | .def z_flags = r20 ; | |
| 222 | ; | |
| 223 | .def opl = r22 ; | |
| 224 | .def oph = r23 ; | |
| 225 | .def z_pcl = r24 ; | |
| 226 | .def z_pch = r25 ; | |
| 227 | ; xl ;r26 | |
| 228 | ; xh ;r27 | |
| 229 | ; yl ;r28 | |
| 230 | ; yh ;r29 | |
| 231 | ; zl ;r30 ; | |
| 232 | ; zh ;r31 ; | |
| 233 | ||
| 234 | ||
| 235 | ||
| 236 | #if defined __ATmega8__ | |
| 237 | .equ flags = TWBR | |
| 238 | .equ P_PUD = SFIOR | |
| 239 | #else | |
| 240 | .equ flags = GPIOR0 | |
| 241 | .equ P_PUD = MCUCR | |
| 242 | #endif | |
| 243 | ||
| 244 | ; Flags: | |
| 245 | .equ hostact = 7 ;host active flag | |
| 246 | .equ hostwrt = 6 ;host written flag | |
| 247 | .equ rsflag = 5 ;read sector flag | |
| 248 | .equ readop = 4 ;1 if read operation | |
| 249 | .equ trace = 0 | |
| 250 | ||
| 251 | ; This is the base z80 port address for clock access | |
| 252 | #define TIMERPORT 0x40 | |
| 253 | #define TIMER_CTL TIMERPORT | |
| 254 | #define TIMER_MSECS TIMERPORT+1 | |
| 255 | #define TIMER_SECS TIMER_MSECS+2 | |
| 256 | ||
| 257 | #define starttimercmd 1 | |
| 258 | #define quitTimerCmd 2 | |
| 259 | #define printTimerCmd 15 | |
| 260 | #define uptimeCmd 16 | |
| 261 | ||
| 262 | #if defined __ATmega8__ | |
| 263 | .equ RXTXDR0 = UDR | |
| 264 | .equ UCSR0A = UCSRA | |
| 265 | .equ UDRE0 = UDRE | |
| 266 | .equ UCSR0B = UCSRB | |
| 267 | .equ RXCIE0 = RXCIE | |
| 268 | .equ UDRIE0 = UDRIE | |
| 269 | .equ RXEN0 = RXEN | |
| 270 | .equ TXEN0 = TXEN | |
| 271 | .equ UCSR0C = UCSRC | |
| 272 | .equ UCSZ00 = UCSZ0 | |
| 273 | .equ UCSZ01 = UCSZ1 | |
| 274 | .equ UBRR0H = UBRRH | |
| 275 | .equ UBRR0L = UBRRL | |
| 276 | .equ OCR2A = OCR2 | |
| 277 | .equ OC2Aaddr= OC2addr | |
| 278 | .equ TCCR2A = TCCR2 | |
| 279 | .equ TCCR2B = TCCR2 | |
| 280 | .equ TIMSK1 = TIMSK | |
| 281 | .equ TIMSK2 = TIMSK | |
| 282 | .equ OCIE2A = OCIE2 | |
| 283 | .equ TIFR1 = TIFR | |
| 284 | .equ ICIE1 = TICIE1 | |
| 285 | #else | |
| 286 | .equ RXTXDR0 = UDR0 | |
| 287 | #endif | |
| 288 | ||
| 289 | ; vim:set ts=8 noet nowrap | |
| 290 | ||
| 291 |