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1 | ; Configuration and common defs for avrcpm BIOS and IPL\r | |
2 | \r | |
3 | ; Copyright (C) 2010 Leo C.\r | |
4 | ;\r | |
5 | ; This program is free software: you can redistribute it and/or modify\r | |
6 | ; it under the terms of the GNU General Public License as published by\r | |
7 | ; the Free Software Foundation, either version 3 of the License, or\r | |
8 | ; (at your option) any later version.\r | |
9 | ;\r | |
10 | ; This program is distributed in the hope that it will be useful,\r | |
11 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of\r | |
12 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r | |
13 | ; GNU General Public License for more details.\r | |
14 | ;\r | |
15 | ; You should have received a copy of the GNU General Public License\r | |
16 | ; along with this program. If not, see <http://www.gnu.org/licenses/>.\r | |
17 | ;\r | |
18 | ; $Id:$\r | |
19 | ;\r | |
20 | \r | |
21 | msize equ 62 ;size of available RAM in k\r | |
22 | \r | |
23 | bias equ (msize-20) * 1024 \r | |
24 | ccp equ 3400h+bias ;base of cpm ccp\r | |
25 | bdos equ ccp+806h ;base of bdos\r | |
26 | bios equ ccp+1600h ;base of bios\r | |
27 | cdisk equ 0004h ;current disk number (0 ... 15)\r | |
28 | iobyte equ 0003h ;intel iobyte\r | |
29 | buff equ 0080h ;default buffer address\r | |
30 | retry equ 3 ;max retries on disk i/o before error\r | |
31 | \r | |
32 | \r | |
33 | ;copy from avr/virt_ports.asm:\r | |
34 | ;\r | |
35 | ; Port Direction Function\r | |
36 | ;hex dez\r | |
37 | ;-------------------------------------------------------------------------\r | |
38 | ;00 0 in - Con status. (deprecated)\r | |
39 | ; Returns 0xFF if the UART has a byte, 0 otherwise.\r | |
40 | ;01 1 in/out - Console input, aka UDR. / Console Output\r | |
41 | ;02 2 out - Console Output (deprecated)\r | |
42 | ;03 3 in - "UART" status: bit 0 = rx (UARTRXRDY) \r | |
43 | ; bit 1 = tx (UARTTXRDY)\r | |
44 | ;03 3 out - "UART" control (tbd)\r | |
45 | ;04 4 in/out - "UART" data register, no wait\r | |
46 | ;\r | |
47 | ;------------------------ Virtual I2C interface --------------------------\r | |
48 | ;05 5 out - Control Port: 1 = Start read operation\r | |
49 | ; 2 = Start write operation \r | |
50 | ;05 5 in - Status of last Transfer: 0 = ok, else fail\r | |
51 | ;06 6 in/out - Number of bytes to transfer, including Slave address\r | |
52 | ;07,08 7,8 in/out - Read/Write address low/high\r | |
53 | ;\r | |
54 | ;------------------------ Disk I/O ---------------------------------------\r | |
55 | ;0D,0E 13,14 in/out - Set address of Bios Controll Block\r | |
56 | ;0F 15 in/out - Disk select\r | |
57 | ;10,11 16,17 in/out - Track select\r | |
58 | ;12,13 18,19 in/out - Sector select\r | |
59 | ;14,15 20,21 in/out - Write addr\r | |
60 | ; \r | |
61 | ;16 22 out - Trigger disk i/o operations\r | |
62 | ; Bit 7 = 1: Read sector\r | |
63 | ; Bit 6 = 1: Write sector\r | |
64 | ; Bit 5 = 1: BIOS WBOOT\r | |
65 | ; Bit 4 = 1: BIOS Home\r | |
66 | ; Only one of bits 4..7 may be set.\r | |
67 | ; If Write function (bit 6=1):\r | |
68 | ; Bits 0..2: 0 - write to allocated\r | |
69 | ; 1 - write to directory\r | |
70 | ; 2 - write unallocated\r | |
71 | ; 3 - write to directory \r | |
72 | ;\r | |
73 | ;16 22 in - Result of last read/write operation.\r | |
74 | ; 0x00 = ok, 0xff = error (--> Bad Sector)\r | |
75 | ;\r | |
76 | ;\r | |
77 | ;------------------------ ADC Interface ----------------------------------\r | |
78 | ;17-19 23,25 in - ADC Channels 6,7 and 8 (Temp-Sensor) \r | |
79 | ; ADC 6,7 only Devices in 32 pin Case (TQFP/MLF)\r | |
80 | ; 8 Bit only\r | |
81 | ; Fixed ADC clock (FCPU/128, 156KHz at 20MHz CPU)\r | |
82 | ; Vref = VCC\r | |
83 | ;20,21 in - ADC: Measure VCC\r | |
84 | ;\r | |
85 | ;------------------------ Wall Clock and Timers --------------------------\r | |
86 | ;40 64-71 in/out - Timer/Clock control. \r | |
87 | ;41-46\r | |
88 | ;\r | |
89 | ;47-4D clock - BCD format: ss, mm, hh, DD, MM, YYl, YYh\r | |
90 | ;\r | |
91 | ;4F debug - start/stop trace, print stack, ...\r | |
92 | ;\r | |
93 | ;------------------------ Ports ------------------------------------------\r | |
94 | ;80-87 in/out - Port-Expander PCF8574 (max. 8 Chips)\r | |
95 | ;88-8F in/out - Port-Expander PCF8574A (not implemented yet!)\r | |
96 | \r | |
97 | ;-----------------------------------------------------------------------\r | |
98 | ; Z80/8080 Virtual Ports\r | |
99 | \r | |
100 | UARTDR equ 1 ;UART Data Register\r | |
101 | UARTCSR equ 3 ;UART Control/Status Register\r | |
102 | UARTRXRDY equ 01h ;RxReady Status Bit Mask\r | |
103 | UARTTXRDY equ 02h ;TxReady Status Bit Mask\r | |
104 | \r | |
105 | READ_FUNC equ 7\r | |
106 | WRITE_FUNC equ 6\r | |
107 | BOOT_FUNC equ 5\r | |
108 | HOME_FUNC equ 4\r | |
109 | \r | |
110 | TIMERCTL equ 040h\r | |
111 | TIMER_MSECS equ TIMERCTL+1\r | |
112 | TIMER_SECS equ TIMER_MSECS+2\r | |
113 | starttimercmd equ 1\r | |
114 | quitTimerCmd equ 2\r | |
115 | printTimerCmd equ 15\r | |
116 | uptimeCmd equ 16\r | |
117 | \r | |
118 | CLOCKPORT equ TIMERCTL+7\r | |
119 | \r | |
120 | DEBUGPORT equ 04FH\r | |
121 | StartTraceCmd equ 1\r | |
122 | StopTraceCmd equ 0\r | |
123 | \r |