avr/config.inc

   1 ;    Configuration, hardware definition, ...
   2 ;
   3 ;    Copyright (C) 2010 Sprite_tm
   4 ;    Copyright (C) 2010 Leo C.
   5 ;
   6 ;    This file is part of avrcpm.
   7 ;
   8 ;    avrcpm is free software: you can redistribute it and/or modify it
   9 ;    under the terms of the GNU General Public License as published by
  10 ;    the Free Software Foundation, either version 3 of the License, or
  11 ;    (at your option) any later version.
  12 ;
  13 ;    avrcpm is distributed in the hope that it will be useful,
  14 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;    GNU General Public License for more details.
  17 ;
  18 ;    You should have received a copy of the GNU General Public License
  19 ;    along with avrcpm.  If not, see <http://www.gnu.org/licenses/>.
  20 ;
  21 ;    $Id$
  22 ;
  23
  24
  25 #define VMAJOR 3                /* Version number */
  26 #define VMINOR 1
  27
  28 #ifndef DRAM_8BIT
  29   #define DRAM_8BIT 1           /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/
  30 #endif                          /* 0 = only one 4 bit wide DRAM chip */
  31 #ifndef F_CPU
  32   #define F_CPU  20000000       /* system clock in Hz; defaults to 20MHz */
  33 #endif
  34 #ifndef BAUD
  35   #define BAUD   38400          /* console baud rate */
  36 #endif
  37 #ifndef I2C
  38     #define I2C  0              /* I2C requires 8 bit DRAM */
  39 #endif
  40 #if I2C && !DRAM_8BIT
  41   #error "I2C requires 8 bit DRAM (DRAM_8BIT=1)!"
  42 #endif
  43
  44 #define EM_Z80  1               /* Emulate Z80 if true, else 8080 */
  45
  46 #ifndef FAT16_SUPPORT
  47   #define FAT16_SUPPORT 1       /* Include Support for FAT16 Partitions */
  48 #endif                          /*  which may contain CP/M image files. */
  49 #define RAMDISKCNT    4         /* Number of RAM disks */
  50 #define RAMDISKNR     'I'-'A'   /* Drive "letter" for first RAM disk */
  51
  52 #define PARTID 0x52             /* Partition table id */
  53                                 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
  54 #define IPLADDR 0x2000          /* Bootloader load address */
  55
  56 #define DRAM_WAITSTATES 1       /* Number of additional clock cycles for dram read access */
  57 #define REFR_RATE   64000       /* dram refresh rate in cycles/s. */
  58                                 /* Most drams need 1/15.6µs. */
  59 #define RXBUFSIZE 128           /* USART recieve buffer size. Must be power of 2 */
  60 #define TXBUFSIZE 128           /* USART transmit buffer size. Must be power of 2 */
  61
  62 #define I2C_CLOCK  100000       /* 100kHz */
  63 #define I2C_BUFSIZE    17       /* largest message size including address byte (SLA) */
  64
  65
  66 .equ BOOTWAIT      = 1
  67 .equ MEMTEST       = 1
  68 .equ MEMFILL       = 1
  69 .equ MMC_DEBUG     = 0          /* Increase for more debugging */
  70 .equ FAT16_DEBUG   = 0
  71 .equ FAT16_RWDEBUG = 0
  72 .equ FAT16_DBG_FAT = 0
  73 .equ DISK_DEBUG    = 0          /* Increase for more debugging */
  74 .equ HOSTRW_DEBUG  = 0
  75 .equ HEAP_DEBUG    = 0
  76 .equ PORT_DEBUG    = 0
  77 .equ INS_DEBUG     = 0
  78 .equ STACK_DBG     = 0
  79 .equ PRINT_PC      = 0
  80 .equ TIMER_DEBUG   = 0
  81
  82 #define MMC_SPI2X  1            /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
  83
  84 #define MEMFILL_VAL      0x76   /* Fill ram with HALT opcode. */
  85 #define DBG_TRACE_BOTTOM 0x01   /* Page boundaries for INS_DEBUG and PRINT_PC  */
  86 #define DBG_TRACE_TOP    0xdc   /* Trace is off, below bottom page and above top page. */
  87
  88 ;-----------------------------------------------------------------------
  89 ; Port declarations
  90
  91 #if DRAM_8BIT   /* Implies software uart */
  92
  93 ;Port D
  94 .equ RAM_D0     = 0
  95 .equ RAM_D1     = 1
  96 .equ RAM_D2     = 2
  97 .equ RAM_D3     = 3
  98 .equ RAM_D4     = 4
  99 .equ RAM_D5     = 5
 100 .equ RAM_D6     = 6
 101 .equ RAM_D7     = 7
 102 .equ RAM_A0     = 0
 103 .equ RAM_A1     = 1
 104 .equ RAM_A2     = 2
 105 .equ RAM_A3     = 3
 106 .equ RAM_A4     = 4
 107 .equ RAM_A5     = 5
 108 .equ RAM_A6     = 6
 109 .equ RAM_A7     = 7
 110
 111 ;Port B
 112 .equ MMC_MOSI   = 3
 113 .equ MMC_MISO   = 4
 114 .equ MMC_SCK    = 5
 115 .equ RAM_A8     = 3
 116 .equ RAM_A9     = 4
 117 .equ RAM_A10    = 5
 118
 119 .equ RXD        = 0
 120 .equ TXD        = 1
 121 .equ MMC_CS     = 2
 122
 123 .equ P_MMC_CS   = PORTB
 124 .equ P_A8       = PORTB
 125 .equ P_RXD      = PORTB
 126 .equ P_TXD      = PORTB
 127
 128 ;Port C
 129 .equ RAM_RAS    = 0
 130 .equ RAM_CAS    = 1
 131 .equ RAM_OE     = 2
 132 .equ RAM_W      = 3
 133
 134 .equ P_RAS      = PORTC
 135 .equ P_CAS      = PORTC
 136 .equ P_OE       = PORTC
 137 .equ P_W        = PORTC
 138
 139
 140 #else   /* 4 bit RAM, hardware uart */
 141
 142 ; Port D
 143 .equ RXD        = 0
 144 .equ TXD        = 1
 145 .equ RAM_OE     = 2
 146 .equ RAM_A8     = 3
 147 .equ MMC_CS     = 4
 148 .equ RAM_A5     = 5
 149 .equ RAM_A6     = 6
 150 .equ RAM_A7     = 7
 151
 152 .equ P_RXD      = PORTD
 153 .equ P_OE       = PORTD
 154 .equ P_A8       = PORTD
 155 .equ P_MMC_CS   = PORTD
 156 .equ P_AH       = PORTD
 157                      ; RAM_A[7..5]
 158 .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
 159 .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK
 160
 161
 162 ;Port B
 163 .equ RAM_A4     = 0
 164 .equ RAM_A3     = 1
 165 .equ RAM_A2     = 2
 166 .equ RAM_A1     = 3
 167 .equ MMC_MOSI   = 3
 168 .equ RAM_A0     = 4
 169 .equ MMC_MISO   = 4
 170 .equ RAM_RAS    = 5
 171 .equ MMC_SCK    = 5
 172
 173 .equ P_RAS      = PORTB
 174 .equ P_AL       = PORTB
 175                         ; RAM_A[4..0]
 176 .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
 177 .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK
 178
 179 ;Port C
 180 .equ RAM_D0     = 0
 181 .equ RAM_D1     = 1
 182 .equ RAM_D2     = 2
 183 .equ RAM_D3     = 3
 184 .equ RAM_W      = 4
 185 .equ RAM_CAS    = 5
 186
 187 .equ P_DQ       = PORTC
 188 .equ P_W        = PORTC
 189 .equ P_CAS      = PORTC
 190
 191 .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
 192 .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)
 193
 194 #endif  /* DRAM_8BIT */
 195
 196
 197 ;-----------------------------------------------------------------------
 198 ;Register definitions
 199
 200 .def    _tmp0   = r0
 201 .def    _tmp1   = r1
 202
 203 .def    _RAS0   = r2
 204 .def    _CAS0   = r3
 205 .def    _OE     = r4
 206 .def    _WE     = r5
 207 .def    _255    = r6
 208 .def    _0      = r7
 209 .def    z_a     = r9
 210 ;.def   stx_bitcount  = r9
 211 ;.def   stx_dr        = r10
 212
 213 .def    srx_lastedgel = r10
 214 .def    srx_lastedgeh = r11
 215 ;.def   insstore= r8    ;
 216 ;.def   insop   = r13   ;
 217
 218 .def    insdecl = r12   ;
 219 .def    insdech = r13   ;
 220 .def    z_spl   = r14
 221 .def    z_sph   = r15   ;
 222 .def    temp    = r16   ;
 223 .def    temp2   = r17   ;
 224 .def    temp3   = r18
 225 .def    temp4   = r19
 226 .def    z_flags = r20   ;
 227 .def    intstat = r21   ; interpreter status / interrupt status
 228 .def    opl     = r22   ;
 229 .def    oph     = r23   ;
 230 .def    z_pcl   = r24   ;
 231 .def    z_pch   = r25   ;
 232 ; xl            ;r26
 233 ; xh            ;r27
 234 ; yl            ;r28
 235 ; yh            ;r29
 236 ; zl            ;r30    ;
 237 ; zh            ;r31    ;
 238
 239
 240 .equ    i_break = 0                     ;break detected flag
 241 .equ    i_trace = 1                     ;cpu interpreter trace flag
 242 .equ    i_halt  = 2                     ;executing halt instruction
 243
 244 #if defined __ATmega8__
 245 .equ    flags   = TWBR
 246 .equ    P_PUD   = SFIOR
 247 #else
 248 .equ    flags   = GPIOR0
 249 .equ    P_PUD   = MCUCR
 250 #endif
 251
 252 ; Flags:
 253         .equ    hostact = 7             ;host active flag
 254         .equ    hostwrt = 6             ;host written flag
 255         .equ    rsflag  = 5             ;read sector flag
 256         .equ    readop  = 4             ;1 if read operation
 257
 258         .equ    prefixfd = 1            ;Opcode prefix DD=0, FD=1
 259         .equ    trace    = 0
 260
 261 ; This is the base z80 port address for clock access
 262 #define TIMERPORT   0x40
 263 #define TIMER_CTL   TIMERPORT
 264 #define TIMER_MSECS TIMERPORT+1
 265 #define TIMER_SECS  TIMER_MSECS+2
 266 #define CLOCKPORT   TIMERPORT+7
 267
 268 #define starttimercmd   1
 269 #define quitTimerCmd    2
 270 #define printTimerCmd   15
 271 #define uptimeCmd       16
 272
 273 #define DEBUGPORT   0x4F
 274
 275 #define startTraceCmd 1
 276 #define stopTraceCmd  0
 277
 278 ; Virtual I2C Interface
 279 #define I2CSTAT 0x05
 280 #define I2CCTRL 0x05
 281 #define I2CBLEN 0x06
 282 #define I2CADR  0x07
 283 #define I2CADRL 0x07
 284 #define I2CADRH 0x08
 285
 286 ; Port-Expander PCF8574
 287 #define PORT    0x80
 288 #define PORT0   0x80
 289 #define PORT1   0x81
 290 #define PORT2   0x82
 291 #define PORT3   0x83
 292 #define PORT4   0x84
 293 #define PORT5   0x85
 294 #define PORT6   0x86
 295 #define PORT7   0x87
 296
 297
 298 #if EM_Z80
 299   #define CPUSTR "Z80"
 300 #else
 301   #define CPUSTR "8080"
 302 #endif
 303
 304 #if defined __ATmega8__
 305 .equ    RXTXDR0 = UDR
 306 .equ    UCSR0A  = UCSRA
 307 .equ     UDRE0  = UDRE
 308 .equ    UCSR0B  = UCSRB
 309 .equ     RXCIE0 = RXCIE
 310 .equ     UDRIE0 = UDRIE
 311 .equ     RXEN0  = RXEN
 312 .equ     TXEN0  = TXEN
 313 .equ    UCSR0C  = UCSRC
 314 .equ     UCSZ00 = UCSZ0
 315 .equ     UCSZ01 = UCSZ1
 316 .equ    UBRR0H  = UBRRH
 317 .equ    UBRR0L  = UBRRL
 318 .equ    OCR2A   = OCR2
 319 .equ    OC2Aaddr= OC2addr
 320 .equ    TCCR2A  = TCCR2
 321 .equ    TCCR2B  = TCCR2
 322 .equ    TIMSK1  = TIMSK
 323 .equ    TIMSK2  = TIMSK
 324 .equ    OCIE2A  = OCIE2
 325 .equ    TIFR1   = TIFR
 326 .equ    ICIE1   = TICIE1
 327 #else
 328 .equ    RXTXDR0 = UDR0
 329 #endif
 330
 331 ; vim:set ts=8 noet nowrap
 332