VERS	EQU	02
	.Z80
;	NAME	AVRCLK		; Change this to no more than 6-char
				; name for the REL driver module

;---------------------------------------------------------------------
; Time format (6 bytes packed BCD)
; 
; TIME+0	last 2 digits of year (prefix 19 assumed for 78 to 99, else 20 assumed)
; TIME+1	month [1..12]
; TIME+2	day [1..31]
; TIME+3	hour [0..23]
; TIME+4	minute [0..59]
; TIME+5	second [0..59]
; 

; This first section contains identification information for the driver
; The information is not placed in the clock driver code section, but are
; located in a different area located by the _CLKID Named Common directive.

	COMMON	/_CLKID/

DESCST:	DEFW	0000		; Add label here if a static year byte
				; is used by your clock driver.  The
				; label should point to the year byte

		;123456789012345678901234
CLKNAM:	DEFB	'AVRCPM Clock            '	; Exactly 24 chars in name
	DEFB	VERS/10+'0','.',VERS MOD 10 +'0',0

DESCR:	DEFB	'This is the AVRCPM clock',0


;---------------------------------------------------------------------
; This section contains any configurable parameters needed for the
; clock driver.  They must be structured in the manner shown in order
; for the loader to properly match and set the values.
; The values in this section are not loaded in the same code section
; as the actual driver code, but are located in another base referenced
; by the _PARM_ Named Common directive.

	COMMON	/_PARM_/

PARBAS:	DEFW	0		; # of parameters (Set to 00 if none)
	DEFW    0		; Pointer to STRS (Set to 00 if none)

;------------------------------------------------------------------
; This section should contain the actual Clock Driver code, and all
; entries here are located in the CSEG, or Code Segment.

	CSEG

MHZ     equ	2               ; Base Processor speed
CLOCKPORT equ	47h

;-----------------------------------------------------------
;	    Z S D O S    C L O C K    H E A D E R
;-----------------------------------------------------------
; Enter: HL points to a 6-byte buffer to Get/Set time
; Exit :  A=1 on Success, A=FFH if error
;	 HL points to last char in buffer
;	E contains original seconds (HL+5)
; NOTE: If clock Set is not included, comment these two jumps
;	out to save a few bytes.  The loader, SETUPZST, uses
;	these two jumps to recognize a full ZSDOS clock and
;	modify the interface code.

PRGBAS:	JP	GETTIM		; Jump to Read Clock
	JP	WRCLK		; Jump to Set Clock

;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;		R e a d    T h e    C l o c k
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

GETTIM:				; The work of reading the clock
				; goes here.  Values needing to be set
				; during installation are referenced as:
	ld	bc,5
	add	hl,bc
	push	hl
	ld	b,6
	ld	c,CLOCKPORT
	ld	e,(hl)
GETT_l:
	in	a,(c)
	ld	(hl),a
	inc	c
	dec	hl
	djnz	GETT_l
	pop	hl
	ld	a,1
	ret
	

;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;		S e t    T h e    C l o c k
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

WRCLK:
	ld	a,(hl)
	cp	78h
	ld	a,19h
	jr	nc,WRC_1
	ld	a,20h
WRC_1:
	out	(CLOCKPORT+6),a
	ld	b,6
	ld	c,CLOCKPORT+5
WRC_l:
	ld	a,(hl)
	out	(c),a	
	dec	c
	inc	hl
	djnz	WRC_l
	dec	hl
	ld	a,1
	ret


;-------------------------------------------------------------
; This code installs configurable items into the clock module
; Enter with DE pointing to the physical base address of the
;	 relocatable module.  DE MUST BE USED TO SET VALUES IN
;	 THE CSEG PORTION OF CODE!
; NOTE: Code in this section is not added to the actual clock
;	driver, but placed in a different area referenced to
;	the common base _POST_.

	COMMON	/_POST_/

; Values in the _PARM_, _POST_ and _PRE_ sections may be loaded
; and saved directly, since their addresses are constant from
; linkage through execution.  Setting or reading values in the
; CSEG must be indirect based on the value in the DE register
; pair.  The following examples show how to access the various
; sections.
;
;	LD	A,(XYR)		; EXAMPLE - Get byte from _PARM_ directly
;	LD	HL,YYR		;    "    - Begin offset into CSEG indirectly
;	ADD	HL,DE		;    "    - HL now addresses relocated loc'n
;	LD	(HL),A		;    "    - ..so value can be stored
;
; Likewise, 16-bit values must be accessed indirectly, and may use
; the BC register pair as transfer storage.
;
;	LD	BC,(XPORT)	; EXAMPLE - Get word from _PARM_ directly
;	LD	HL,YPORT1	;    "    - Begin offset into CSEG indirectly
;	ADD	HL,DE		;    "    - HL now addresses relocated loc'n
;	LD	(HL),C		;    "    - ..so value can be saved..
;	INC	HL		;    "    - ...a byte..
;	LD	(HL),B		;    "    - ....at a time..
;
;	LD	(YPORT2),BC	; EXAMPLE - Values can be stored directly into
;				     "    - other sections such as _PRE_

	RET		; This RETURN MUST be present even if no other
			; code is included in this section


;----------------------------------------------------------------
; This module is executed just prior to installing the module to
;   insure that a valid clock is present
; Enter with DE pointing to base of relocated clock code segment
;---------------------------------------------------------------
; Read clock and wait for seconds to roll - watchdog protected
; Enter with: DE pointing to relocated clock read routine
;	HL pointing to base of high module

	COMMON	/_PRE_/

; Optional final setup of the clock module may go here.  Examples of such
; code would be installation-dependant items such as physical RAM location
; for the driver module.  If any code is added here, the DE register pair
; MUST be preserved to properly inter PRECLOCK code (If included).

;YPORT2	EQU	$+1		; EXAMPLE - just to show accessing method
;	LD	BC,0000		;    "    - ..from _POST_ code.

	INCLUDE	PRECLOCK.LIB	; This section of code merely calls the
				; clock and waits an arbitrary period of
				; time (>> 1 second) to see if the time
				; changes.  It returns an error if not.
	if 0
TSTRD:	JR	TSTRD0	; Jump around address store

	DEFW    TSTRD	; Org location of the code
TSTRD0:	SCF
	LD      A,1
	RET
	endif



	END