; Configuration, hardware definition, ... ; ; Copyright (C) 2010 Sprite_tm ; Copyright (C) 2010 Leo C. ; ; This file is part of avrcpm. ; ; avrcpm is free software: you can redistribute it and/or modify it ; under the terms of the GNU General Public License as published by ; the Free Software Foundation, either version 3 of the License, or ; (at your option) any later version. ; ; avrcpm is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with avrcpm. If not, see . ; ; $Id$ ; #define VMAJOR 3 /* Version number */ #define VMINOR 0 #ifndef DRAM_8BIT #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */ #endif #ifndef F_CPU #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ #endif #ifndef BAUD #define BAUD 38400 /* console baud rate */ #endif #define K 1024 #define M 1024*K ;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */ #define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */ #define EM_Z80 1 /* Emulate Z80 if true */ #ifndef FAT16_SUPPORT #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */ #endif /* which may contain CP/M image files. */ #define RAMDISKCNT 0 /* Number of RAM disks */ #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */ #define PARTID 0x52 /* Partition table id */ /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */ #define IPLADDR 0x2000 /* Bootloader load address */ #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */ #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */ /* Most drams need 1/15.6µs. */ #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */ #define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */ #if EM_Z80 #define CPUSTR "Z80" #else #define CPUSTR "8080" #endif .equ BOOTWAIT = 1 .equ MEMTEST = 1 .equ MEMFILL = 1 .equ MMC_DEBUG = 0 /* Increase for more debugging */ .equ FAT16_DEBUG = 0 .equ FAT16_RWDEBUG = 0 .equ FAT16_DBG_FAT = 0 .equ DISK_DEBUG = 0 /* Increase for more debugging */ .equ HOSTRW_DEBUG = 0 .equ HEAP_DEBUG = 0 .equ PORT_DEBUG = 0 .equ INS_DEBUG = 0 .equ STACK_DBG = 0 .equ PRINT_PC = 0 #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */ #define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */ #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */ #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */ ;----------------------------------------------------------------------- ; Port declarations #if DRAM_8BIT /* Implies software uart */ ;Port D .equ RAM_D0 = 0 .equ RAM_D1 = 1 .equ RAM_D2 = 2 .equ RAM_D3 = 3 .equ RAM_D4 = 4 .equ RAM_D5 = 5 .equ RAM_D6 = 6 .equ RAM_D7 = 7 .equ RAM_A0 = 0 .equ RAM_A1 = 1 .equ RAM_A2 = 2 .equ RAM_A3 = 3 .equ RAM_A4 = 4 .equ RAM_A5 = 5 .equ RAM_A6 = 6 .equ RAM_A7 = 7 ;Port B .equ MMC_MOSI = 3 .equ MMC_MISO = 4 .equ MMC_SCK = 5 .equ RAM_A8 = 3 .equ RAM_A9 = 4 .equ RAM_A10 = 5 .equ RXD = 0 .equ TXD = 1 .equ MMC_CS = 2 .equ P_MMC_CS = PORTB .equ P_A8 = PORTB .equ P_RXD = PORTB ;Port C .equ RAM_RAS = 0 .equ RAM_CAS = 1 .equ RAM_OE = 2 .equ RAM_W = 3 .equ P_RAS = PORTC .equ P_CAS = PORTC .equ P_OE = PORTC .equ P_W = PORTC #else /* 4 bit RAM, hardware uart */ ; Port D .equ RXD = 0 .equ TXD = 1 .equ RAM_OE = 2 .equ RAM_A8 = 3 .equ MMC_CS = 4 .equ RAM_A5 = 5 .equ RAM_A6 = 6 .equ RAM_A7 = 7 .equ P_RXD = PORTD .equ P_OE = PORTD .equ P_A8 = PORTD .equ P_MMC_CS = PORTD .equ P_AH = PORTD ; RAM_A[7..5] .equ RAM_AH_MASK = (1<