\r
maclib CFGACPM.LIB\r
\r
+cr equ 0dh\r
+lf equ 0ah\r
+\r
aseg\r
org 100h\r
.phase bios\r
.z80\r
\r
-nsects equ ($-ccp)/128 ;warm start sector count\r
+nsects equ ($-ccp)/128 ;warm start sector count\r
\r
- jp boot\r
+ jp boot\r
wboote: \r
- jp wboot\r
- jp const\r
- jp conin\r
- jp conout\r
- jp list\r
- jp punch\r
- jp reader\r
- jp home\r
- jp seldsk\r
- jp settrk\r
- jp setsec\r
- jp setdma\r
- jp read\r
- jp write\r
- jp listst\r
- jp sectran\r
+ jp wboot\r
+ jp const\r
+ jp conin\r
+ jp conout\r
+ jp list\r
+ jp punch\r
+ jp reader\r
+ jp home\r
+ jp seldsk\r
+ jp settrk\r
+ jp setsec\r
+ jp setdma\r
+ jp read\r
+ jp write\r
+ jp listst\r
+ jp sectran\r
+ jp 0 ;zsdos (?)\r
+ jp 0 ;zsdos (?)\r
+ jp 0 ;zsdos (?)\r
+ jp clock ;zsdos compatible clock set/get\r
+\r
\r
.8080\r
maclib AVRCPM.LIB\r
db cr,lf,0\r
\r
const:\r
- in a,(0)\r
+ in a,(0)\r
ret\r
\r
conin:\r
- in a,(0)\r
- cp 0ffh\r
- jp nz,conin\r
+ in a,(0)\r
+ cp 0ffh\r
+ jp nz,conin\r
\r
- in a,(1)\r
+ in a,(1)\r
ret\r
\r
conout:\r
- ld a,c\r
- out (1),a\r
+ ld a,c\r
+ out (1),a\r
ret\r
\r
list:\r
ret\r
\r
listst:\r
- ld a,0\r
+ ld a,0\r
ret\r
\r
punch:\r
ret\r
\r
reader:\r
- ld a,01Fh\r
+ ld a,01Fh\r
ret\r
\r
prmsg:\r
ld h,0\r
ret\r
\r
+;------------------------------------------------------------------------\r
+; ZSDOS clock drivers may use registers BC and D without restoring them, \r
+; but must preserve the Z80's alternate and index registers. \r
+; Other registers must be used exactly as follows:\r
+;\r
+; Enter: C = 00H to Read the Clock, 01H to Set the Clock\r
+; DE = Address of a 6-byte field to Receive or from which \r
+; to Set time in DateStamper format (BCD digits as: \r
+; YY MM DD HH MM SS). 24-hour operation is assumed.\r
+;\r
+; Exit : A = 01H for a successful operation,\r
+; 0FFH for a failure of any sort (Can't set, etc.)\r
+;\r
+; When Reading the Clock:\r
+; E = Original contents of Entry value of DE plus 5\r
+; HL = Entry value of DE plus 5 (Seconds field)\r
+\r
+clock:\r
+ dec c\r
+ jr z,clk_set\r
+ inc c\r
+ ret nz\r
+\r
+clk_read:\r
+ ex de,hl\r
+ ld bc,5*256 + CLOCKPORT-1\r
+clkg_l:\r
+ inc c\r
+ ini\r
+ jr nz,clkg_l\r
+ ld e,(hl)\r
+ in a,(CLOCKPORT+5)\r
+ ld (hl),a\r
+ jr clk_e\r
+\r
+clk_set:\r
+ ld hl,5\r
+ add hl,de\r
+ ld bc,6*256 + CLOCKPORT+6\r
+clks_l:\r
+ dec c\r
+ outd\r
+ jr nz,clks_l\r
+clk_e:\r
+ ld a,1\r
+ ret\r
+\r
+;------------------------------------------------------------------------\r
+\r
bcb: dw drvtbl\r
dw dirbuf\r
dw enddat\r