; 8080/Z80 Interpreter.
; This is part of the Z80-CP/M emulator written by Sprite_tm.
-;
+;
; Copyright (C) 2010 Sprite_tm
-; Copyright (C) 2010 Leo C.
+; Copyright (C) 2010-2013 Leo C.
; Copyright (C) 2010 Horst S.
; This file is part of avrcpm.
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: Z80int-jmp.asm 93 2014-01-03 16:32:32Z rapid $
;
- .dseg
-z_regs:
-z_b: .byte 1
-z_c: .byte 1
-z_d: .byte 1
-z_e: .byte 1
-z_h: .byte 1
-z_l: .byte 1
-
- .equ oz_b = 0
- .equ oz_c = 1
- .equ oz_d = 2
- .equ oz_e = 3
- .equ oz_h = 4
- .equ oz_l = 5
-
-
#if EM_Z80
-z_b2: .byte 1
-z_c2: .byte 1
-z_d2: .byte 1
-z_e2: .byte 1
-z_h2: .byte 1
-z_l2: .byte 1
-z_f2: .byte 1
-z_a2: .byte 1
- .equ r2ofs = z_b2-z_b
- .equ oz_b2 = 6
- .equ oz_c2 = 7
- .equ oz_d2 = 8
- .equ oz_e2 = 9
- .equ oz_h2 = 10
- .equ oz_l2 = 11
- .equ oz_f2 = 12
- .equ oz_a2 = 13
-
-z_xh: .byte 1
-z_xl: .byte 1
-z_yh: .byte 1
-z_yl: .byte 1
-
-z_i: .byte 1
-z_r: .byte 1
- .equ oz_xh = 14
- .equ oz_xl = 15
- .equ oz_yh = 16
- .equ oz_yl = 17
- .equ oz_i = 18
- .equ oz_r = 19
-
-z_istat: .byte 1
- .equ oz_istat = 20
+
+ .dseg
+z_regs:
+z_c2:
+ .equ oz_c2 = z_c2 - z_regs
+ .byte 1
+z_b2:
+ .equ oz_b2 = z_b2 - z_regs
+ .byte 1
+z_e2:
+ .equ oz_e2 = z_e2 - z_regs
+ .byte 1
+z_d2:
+ .equ oz_d2 = z_d2 - z_regs
+ .byte 1
+z_l2:
+ .equ oz_l2 = z_l2 - z_regs
+ .byte 1
+z_h2:
+ .equ oz_h2 = z_h2 - z_regs
+ .byte 1
+z_f2:
+ .equ oz_f2 = z_f2 - z_regs
+ .byte 1
+z_a2:
+ .equ oz_a2 = z_a2 - z_regs
+ .byte 1
+
+z_xl:
+ .equ oz_xl = z_xl - z_regs
+ .byte 1
+z_xh:
+ .equ oz_xh = z_xh - z_regs
+ .byte 1
+z_yl:
+ .equ oz_yl = z_yl - z_regs
+ .byte 1
+z_yh:
+ .equ oz_yh = z_yh - z_regs
+ .byte 1
+z_i:
+ .equ oz_i = z_i - z_regs
+ .byte 1
+z_r:
+ .equ oz_r = z_r - z_regs
+ .byte 1
+
+z_istat:
+ .equ oz_istat = z_istat - z_regs
+ .byte 1
.equ IM_MASK = 0x03 ;Mask IM 0..2
.equ IM0 = 0
.equ IFF1 = 2 ;IFF1 Flag
.equ IFF2 = 3 ;IFF2 Flag
-
#endif
.cseg
-
+
;Init z80
z80_init:
ldiw z_pc,IPLADDR
ldiw y,z_regs
- cbi flags,trace
clr intstat
printnewline
;TODO: hier kommt die Interruptbehandlung rein
- cpse intstat,_0 ;Fast path if no trace, int, break, ...
+ cpse intstat,_0 ; 2 Fast path if no trace, int, break, ...
rjmp int_test
int_instr:
- mem_read_ds zl,z_pc ;zl = memReadByte(z_pc)
- adiw z_pcl,1 ;++z_pc
- ldi zh,high(opcjmp) ;
- icall
- rjmp main ;
-
+ mem_read_ds zl,z_pc ;11 zl = memReadByte(z_pc)
+ adiw z_pcl,1 ; 2 ++z_pc
+ ldi zh,high(opcjmp) ; 1
+ icall ; 3 (+4 ret)
+ rjmp main ; 2
+ ; / 25 cycles minimum (NOP)
int_test:
sbrs intstat,i_trace
rjmp int_notrace
+ sbrc intstat,i_halt
+ rjmp int_notrace
cpi z_pch,DBG_TRACE_BOTTOM
brlo int_notrace
cpi z_pch,DBG_TRACE_TOP
;--------------------------------------------------
-; init opcode table
+; init opcode table
;
; opctable opc_name, pos
;
.set opc_tablen_1 = 256
;.message "add tab_1"
.endif
- .else
+ .else
.if (opc_tablow_1 + opc_tablen_1) == opcjmp_table_pos_
.set opc_tablen_1 = opc_tablen_1 + 256
;.message "tab_1++"
.endm
;--------------------------------------------------
-;
+;
; checkspace frompos, size
;
.macro checkspace
;
; instr fetch, op, store
;
-.macro instr
+.macro instr
.set fetch_ = (do_@0 != do_fetch_nop) ; must call or jump to fetch action
.set op_ = (do_@1 != do_op_nop) ; must call or jump to op action
.org l_@0_@1_@2
.if fetch_ ; must fetch
- .if op_ || store_
+ .if op_ || store_
.if do_@0 == 0
m_do_@0
.else
.else
ljmp do_@2 ; store is allways last
.endif
- .endif
+ .endif
.endif
.endif
; ret
.macro m_do_fetch_b
- ldd opl,y+oz_b
+ mov opl,z_b
.endm
.equ do_fetch_b = 0
+; mov opl,z_b
; ldd opl,y+oz_b
; ret
.macro m_do_fetch_c
- ldd opl,y+oz_c
+ mov opl,z_c
.endm
.equ do_fetch_c = 0
+; mov opl,z_c
; ldd opl,y+oz_c
; ret
.macro m_do_fetch_d
- ldd opl,y+oz_d
+ mov opl,z_d
.endm
.equ do_fetch_d = 0
; ret
.macro m_do_fetch_e
- ldd opl,y+oz_e
+ mov opl,z_e
.endm
.equ do_fetch_e = 0
; ret
.macro m_do_fetch_h
- ldd opl,y+oz_h
+ mov opl,z_h
.endm
.equ do_fetch_h = 0
-; ldd opl,y+oz_h
+; mov opl,z_h
; ret
.macro m_do_fetch_l
- ldd opl,y+oz_l
+ mov opl,z_l
.endm
.equ do_fetch_l = 0
-; ldd opl,y+oz_l
+; mov opl,z_l
; ret
-do_fetch_af:
- mov opl,z_flags
- mov oph,z_a
- ret
+.macro m_do_fetch_af
+ movw opl,z_flags
+.endm
-do_fetch_bc:
- ldd opl,y+oz_c
- ldd oph,y+oz_b
- ret
+.equ do_fetch_af = 0
+; movw opl,z_flags
+; ret
-do_fetch_de:
- ldd opl,y+oz_e
- ldd oph,y+oz_d
- ret
+.macro m_do_fetch_bc
+ movw opl,z_c
+.endm
-do_fetch_hl:
- ldd opl,y+oz_l
- ldd oph,y+oz_h
- ret
+.equ do_fetch_bc = 0
+; movw opl,z_c
+; ret
+
+.macro m_do_fetch_de
+ movw opl,z_e
+.endm
+
+.equ do_fetch_de = 0
+; movw opl,z_e
+; ret
+
+.macro m_do_fetch_hl
+ movw opl,z_l
+.endm
+
+.equ do_fetch_hl = 0
+; movw opl,z_l
+; ret
.macro m_do_fetch_sp
movw opl,z_spl
; ret
do_fetch_mbc:
- ldd xh,y+oz_b
- ldd xl,y+oz_c
- mem_read_d z_a
+; movw x,z_c
+ mem_read_ds z_a, z_bc
ret
do_fetch_mde:
- ldd xh,y+oz_d
- ldd xl,y+oz_e
- mem_read_d z_a
+; movw x,z_e
+ mem_read_ds z_a, z_de
ret
do_fetch_mhl:
- ldd xh,y+oz_h
- ldd xl,y+oz_l
- mem_read_d opl
+; movw x,z_l
+ mem_read_ds opl, z_hl
ret
do_fetch_msp:
store_ops:
.equ do_store_nop = do_x_nop
-
+
do_store_a:
mov z_a,opl
ret
-;.macro m_do_store_b
+;.macro m_do_store_b
; std y+oz_b,opl
;.endm
;.equ do_store_b = 0
do_store_b:
- std y+oz_b,opl
+ mov z_b,opl
ret
do_store_c:
- std y+oz_c,opl
+ mov z_c,opl
ret
do_store_d:
- std y+oz_d,opl
+ mov z_d,opl
ret
do_store_e:
- std y+oz_e,opl
+ mov z_e,opl
ret
do_store_h:
- std y+oz_h,opl
+ mov z_h,opl
ret
do_store_l:
- std y+oz_l,opl
+ mov z_l,opl
ret
do_store_af:
- mov z_a,oph
- mov z_flags,opl
+ movw z_flags,opl
ret
do_store_bc:
- std y+oz_b,oph
- std y+oz_c,opl
+ movw z_c,opl
ret
do_store_de:
- std y+oz_d,oph
- std y+oz_e,opl
+ movw z_e,opl
+; std y+oz_d,oph
+; std y+oz_e,opl
ret
do_store_hl:
- std y+oz_h,oph
- std y+oz_l,opl
+ movw z_l,opl
ret
do_store_mbc:
- ldd xh,y+oz_b
- ldd xl,y+oz_c
- mem_write_s z_a
+; movw x,z_c
+ mem_write_ds z_bc, z_a
ret
do_store_mde:
- ldd xh,y+oz_d
- ldd xl,y+oz_e
- mem_write_s z_a
+; movw x,z_e
+ mem_write_ds z_de, z_a
ret
do_store_mhl:
- ldd xh,y+oz_h
- ldd xl,y+oz_l
- mem_write_s opl
+; movw x,z_l
+ mem_write_ds z_hl, opl
ret
do_store_msp:
do_store_pcrel: ;add displacement to PC
#if EM_Z80
- clr oph
- tst opl ;sign extend
- brpl stpcr1
- com oph
-stpcr1:
+ mov oph,opl ;sign extend
+ lsl oph
+ sbc oph,oph
add z_pcl,opl
adc z_pch,oph
ret
.macro ldpmx
ldi zh,high(@1*2) ; table must be page aligned
- mov zl,@2
- lpm @0,z
+ mov zl,@2
+ lpm @0,z
.endm
.macro do_z80_flags_V
#endif
.endm
-
+
.macro do_z80_flags_copy_HC
#if EM_Z80
bmov z_flags, ZFL_H, z_flags, ZFL_C
;
do_op_ina: ; in a,(opl)
.if PORT_DEBUG
- push opl
+ push opl
cp opl,_0 ; don't debug port 0 (con stat)
breq dbg_op_ina_1
printnewline
do_op_inc:
#if EM_Z80
+#if 1
+ andi z_flags,(1<<ZFL_C) ; preserve C-, Clear N-flag
+ subi opl,-1
+ in temp,sreg
+ sbrc temp,AVR_N
+ sbr z_flags,(1<<ZFL_S)
+ sbrc temp,AVR_Z
+ sbr z_flags,(1<<ZFL_Z)
+ sbrs temp,AVR_H
+ sbr z_flags,(1<<ZFL_H)
+ sbrc temp,AVR_V
+ sbr z_flags,(1<<ZFL_P)
+#else
andi z_flags,(1<<ZFL_C) ; preserve C-, Clear N-flag
ldi temp,1
add opl,temp
bmov z_flags,ZFL_Z, temp,AVR_Z
bmov z_flags,ZFL_H, temp,AVR_H
bmov z_flags,ZFL_P, temp,AVR_V
+#endif
#else /* 8080 */
andi z_flags,(1<<ZFL_C)|(1<<ZFL_H) ; preserve C- and H-flag
inc opl
#endif
ret
+#if 0
+ bst z_flags,ZFL_C ; save C flag
+ subi opl,-1
+ in temp,sreg
+ ldpmx z_flags,flagmap_tab,temp
+ bld z_flags,ZFL_C
+ ret
+#endif
+
do_op_inca:
#if EM_Z80
andi z_flags,(1<<ZFL_C) ; preserve C-, Clear N-flag
- ldi temp,1
- add z_a,temp
+ subi z_a,-1
in temp,sreg
bmov z_flags,ZFL_S, temp,AVR_N
bmov z_flags,ZFL_Z, temp,AVR_Z
- bmov z_flags,ZFL_H, temp,AVR_H
+ sbrs temp,AVR_H
+ sbr z_flags,(1<<ZFL_H)
bmov z_flags,ZFL_P, temp,AVR_V
#else /* 8080 */
andi z_flags,(1<<ZFL_C)|(1<<ZFL_H) ; preserve C- and H-flag
;|Mnemonic |SZHPNC|Description |Notes |
;----------------------------------------------------------------
;|DEC r |***V1-|Decrement |s=s-1 |
-;|DEC [HL] |***V0-|Increment |[HL]=[HL]-1 |
-;|DEC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]-1 |
+;|DEC [HL] |***V1-|Increment |[HL]=[HL]-1 |
+;|DEC [xx+d]|***V1-|Increment |[xx+d]=[xx+d]-1 |
;|----------|SZHP C|---------- 8080 ----------------------------|
;|DEC r |**-P -|Increment |r=r-1 |
;|DEC [HL] |**-P -|Increment |[HL]=[HL]-1 |
do_op_deca:
#if EM_Z80
- ldi temp,1
- sub z_a,temp
+ subi z_a,1
in temp,sreg
bmov z_flags,ZFL_S, temp,AVR_N
bmov z_flags,ZFL_Z, temp,AVR_Z
;|INC xx |------|Increment |xx=xx+1 |
;|INC ss |------|Increment |ss=ss+1 |
;
-;
+;
do_op_inc16:
subi opl,low(-1)
sbci oph,high(-1)
ret
+do_op_incHL:
+ sub z_l,_255
+ sbc z_h,_255
+ ret
+
+do_op_incDE:
+ sub z_e,_255
+ sbc z_d,_255
+ ret
+
+do_op_incBC:
+ sub z_c,_255
+ sbc z_b,_255
+ ret
+
;----------------------------------------------------------------
;|Mnemonic |SZHPNC|Description |Notes |
;----------------------------------------------------------------
;|DEC xx |------|Decrement |xx=xx-1 |
;|DEC ss |------|Decrement |ss=ss-1 |
;
-;
+;
do_op_dec16:
subi opl, 1
sbci oph, 0
ret
+do_op_decHL:
+ add z_l,_255
+ adc z_h,_255
+ ret
+
+do_op_decDE:
+ add z_e,_255
+ adc z_d,_255
+ ret
+
+do_op_decBC:
+ add z_c,_255
+ adc z_b,_255
+ ret
+
;----------------------------------------------------------------
;|Mnemonic |SZHPNC|Description |Notes |
;----------------------------------------------------------------
;
;
do_op_rlca:
- ;Rotate Left Cyclical. All bits move 1 to the
+ ;Rotate Left Cyclical. All bits move 1 to the
;left, the msb becomes c and lsb.
do_z80_flags_op_rotate
lsl z_a
;|RRCA |---- *|Rotate Right Circular|A=->A |
;
;
-do_op_rrca:
- ;Rotate Right Cyclical. All bits move 1 to the
+do_op_rrca:
+ ;Rotate Right Cyclical. All bits move 1 to the
;right, the lsb becomes c and msb.
do_z80_flags_op_rotate
lsr z_a
;|----------|SZHP C|---------- 8080 ----------------------------|
;|RRA |---- *|Rotate Right Acc. |A=->{CY,A} |
;
-;
-do_op_rra:
- ;Rotate Right. All bits move 1 to the right, the lsb
+;
+do_op_rra:
+ ;Rotate Right. All bits move 1 to the right, the lsb
;becomes c, c becomes msb.
clc ; get z80 carry to avr carry
sbrc z_flags,ZFL_C
;|----------|SZHP C|---------- 8080 ----------------------------|
;|RLA |---- *|Rotate Left Acc. |A={CY,A}<- |
;
-;
+;
do_op_rla:
- ;Rotate Left. All bits move 1 to the left, the msb
+ ;Rotate Left. All bits move 1 to the left, the msb
;becomes c, c becomes lsb.
clc
sbrc z_flags,ZFL_C
;
;
do_op_addhl:
- ldd temp,y+oz_l
- ldd temp2,y+oz_h
- add opl,temp
- adc oph,temp2
- std y+oz_l,opl
- std y+oz_h,oph
+ add z_l,opl
+ adc z_h,oph
in temp,sreg
bmov z_flags,ZFL_C, temp,AVR_C
do_z80_flags_H
;
do_op_sthl: ;store hl to mem loc in opl:h
movw xl,opl
- ldd temp,y+oz_l
- mem_write
+ mem_write_s z_l
adiw xl,1
- ldd temp,y+oz_h
- mem_write
+ mem_write_s z_h
ret
;----------------------------------------------------------------
;----------------------------------------------------------------
;|LD dst,src|------|Load |dst=src |
;
-;
+;
do_op_rmem16:
movw xl,opl
mem_read_d opl
;
; ---------------------
; | N | H | low |H' |
-; | | |nibble | |
+; | | |nibble | |
; |---+---+-------+---|
-; | 0 | * | 0-9 | 0 |
-; | 0 | * | a-f | 1 |
-; | 1 | 0 | * | 0 |
-; | 1 | 1 | 6-f | 0 |
-; | 1 | 1 | 0-5 | 1 |
+; | 0 | * | 0-9 | 0 |
+; | 0 | * | a-f | 1 |
+; | 1 | 0 | * | 0 |
+; | 1 | 1 | 6-f | 0 |
+; | 1 | 1 | 0-5 | 1 |
; ---------------------
;
; Ohter flags:
#if 0
#if EM_Z80
- sbrc z_flags,ZFL_N ;if add-op
+ sbrc z_flags,ZFL_N ;if add-op
rjmp op_da_sub ;then
#endif
brlo op_da_a10 ; |
op_da_a01: ; then
ldi oph,0x06 ; add 6 to lower nibble
- add opl,oph ;
- brhc op_da_02 ; if
+ add opl,oph ;
+ brhc op_da_02 ; if
ori temp2,(1<<ZFL_H) ; set new H flag
op_da_02: ;
brcc op_da_a10 ; if
sbrc z_flags,ZFL_C ; |
rjmp op_da_a12 ; if (C flag ...
cpi opl,0xA0 ; |... or upper nibble >= 0xA0)
- brlo op_da_a13 ;
+ brlo op_da_a13 ;
op_da_a12: ;
ldi oph,0x60 ; add 6 to lower nibble
add opl,oph ;
brlo op_da_s10 ; |
op_da_s01: ; then
ldi oph,0x06 ; add 6 to lower nibble
- sub opl,oph ;
- brhc PC+2 ; if
+ sub opl,oph ;
+ brhc PC+2 ; if
ori temp2,(1<<ZFL_H) ; set new H flag
brcc op_da_s10 ; if
ori temp2,(1<<ZFL_C) ; set new C flag
sbrc z_flags,ZFL_C ; |
rjmp op_da_s12 ; if (C flag ...
cpi opl,0x90 ; |... or upper nibble >= 0xA0)
- brlo op_da_s13 ;
+ brlo op_da_s13 ;
op_da_s12: ;
ldi oph,0x60 ; add 6 to lower nibble
sub opl,oph ;
ldi oph,0 ;oph: what to add
#if EM_Z80
- sbrc z_flags,ZFL_N ;if add-op
+ sbrc z_flags,ZFL_N ;if add-op
rjmp op_da_sub ;then
#endif
rjmp op_da_a02 ; if (C flag ...
cpi opl,0x90 ; |... or upper nibble >= 0x90)
brlo op_da_a03 ; |
-op_da_a02:
+op_da_a02:
ori oph,0x60 ; add 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_a03: ; endif
sbrc z_flags,ZFL_C ; |
rjmp op_da_a12 ; if (C flag ...
cpi opl,0xA0 ; |... or upper nibble >= 0xA0)
- brlo op_da_a13 ;
-op_da_a12:
+ brlo op_da_a13 ;
+op_da_a12:
ori oph,0x60 ; add 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_a13:
rjmp op_da_s02 ; if (C flag ...
cpi opl,0x90 ; |... or upper nibble >= 0x90)
brlo op_da_s03 ; |
-op_da_s02:
+op_da_s02:
ori oph,0x60 ; sub 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_s03: ; endif
sbrc z_flags,ZFL_C ; |
rjmp op_da_s12 ; if (C flag ...
cpi opl,0xA0 ; |... or upper nibble >= 0xA0)
- brlo op_da_s13 ;
-op_da_s12:
+ brlo op_da_s13 ;
+op_da_s12:
ori oph,0x60 ; sub 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_s13:
;|EX [SP],HL|------|Exchange |[SP]<->HL |
;|EX DE,HL |------|Exchange |DE<->HL |
;-----------------------------Z80--------------------------------
-;
+;
do_op_exhl:
- ldd temp,y+oz_l
- ldd temp2,y+oz_h
- std y+oz_l,opl
- std y+oz_h,oph
- movw opl,temp
+ movw temp,z_l
+ movw z_l,opl
+ movw opl,temp
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_Z
ret
pop temp ; nix tun
- pop temp ; direkt zurueck zu main
+ pop temp ; direkt zurueck zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_Z
ret
pop temp ; nix tun
- pop temp ; direkt zurueck zu main
+ pop temp ; direkt zurueck zu main
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_C
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_C
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_P
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_P
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_S
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_S
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
; (Joe G.)
do_op_DJNZ: ; decremt B, jump B=0
- ldd temp,y+oz_b ; B in temp
- dec temp ; temp decrementieren
- std y+oz_b,temp ; temp in B
+ dec z_b ; B decrementieren
breq do_op_DJNZ_Z ; bei B=0
subi opl, 0x80 ; z_pc + e im Zweierkomplement
subi z_pcl,0x80
#else
do_op_djnz:
- ldd temp,y+oz_b
- dec temp
- std y+oz_b,temp
+ dec z_b
brne opdjnze
pop temp ; nix tun
- pop temp ; direkt zurueck zu main
+ pop temp ; direkt zurueck zu main
opdjnze:
ret
;|EXX |------|Exchange |qq<->qq' (except AF)|
+#if 1
+
+do_op_EXX:
+ ldd temp ,y+oz_c2
+ ldd temp2,y+oz_b2
+ std y+oz_c2,z_c
+ std y+oz_b2,z_b
+ movw z_c,temp
+
+ ldd temp ,y+oz_e2
+ ldd temp2,y+oz_d2
+ std y+oz_e2,z_e
+ std y+oz_d2,z_d
+ movw z_e,temp
+
+ ldd temp ,y+oz_l2
+ ldd temp2,y+oz_h2
+ std y+oz_l2,z_l
+ std y+oz_h2,z_h
+ movw z_l,temp
+ ret
+#else
+
do_op_EXX:
ldiw z,z_b
ldi temp3,6
brne opexx_loop
ret
+#endif
+
#else
do_op_djnz:
do_op_EXAF:
mem_read_ds zl,z_pc ;zl = memReadByte(z_pc)
adiw z_pcl,1 ;++z_pc
ldi zh,high(EDjmp) ;
-;;; ldi zh,high(0) ;
ijmp
opprxcb_1:
mem_read_s z_pc ;get displacement
adiw z_pcl,1 ;++z_pc
- clr temp2 ;sign extend
- tst temp
- brpl PC+2
- com temp2
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_read_d opl
; Lookup table for Z80 opcodes. Translates the first byte of the instruction word into three
; operations: fetch, do something, store.
-; The table is made of 256 words.
+; The table is made of 256 words.
opctable opcjmp, PC ;+3*256
-
+
instr fetch_nop, op_nop, store_nop ;00 ;NOP
instr fetch_DIR16, op_nop, store_BC ;01 nn nn ;LD BC,nn
instr fetch_nop, op_nop, store_MBC ;02 ;LD (BC),A
-instr fetch_BC, op_INC16, store_BC ;03 ;INC BC
+;instr fetch_BC, op_INC16, store_BC ;03 ;INC BC
+instr fetch_nop, op_INCBC, store_nop ;03 ;INC BC
instr fetch_B, op_INC, store_B ;04 ;INC B
instr fetch_B, op_DEC, store_B ;05 ;DEC B
instr fetch_DIR8, op_nop, store_B ;06 ;LD B,n
instr fetch_nop, op_EXAF, store_nop ;08 ;EX AF,AF'
instr fetch_BC, op_ADDHL, store_nop ;09 ;ADD HL,BC
instr fetch_MBC, op_nop, store_nop ;0A ;LD A,(BC)
-instr fetch_BC, op_DEC16, store_BC ;0B ;DEC BC
+;instr fetch_BC, op_DEC16, store_BC ;0B ;DEC BC
+instr fetch_nop, op_DECBC, store_nop ;0B ;DEC BC
instr fetch_C, op_INC, store_C ;0C ;INC C
instr fetch_C, op_DEC, store_C ;0D ;DEC C
instr fetch_DIR8, op_nop, store_C ;0E nn ;LD C,n
instr fetch_DIR8, op_DJNZ, store_nop ;10 oo ;DJNZ o
instr fetch_DIR16, op_nop, store_DE ;11 nn nn ;LD DE,nn
instr fetch_nop, op_nop, store_MDE ;12 ;LD (DE),A
-instr fetch_DE, op_INC16, store_DE ;13 ;INC DE
+;instr fetch_DE, op_INC16, store_DE ;13 ;INC DE
+instr fetch_nop, op_INCDE, store_nop ;13 ;INC DE
instr fetch_D, op_INC, store_D ;14 ;INC D
instr fetch_D, op_DEC, store_D ;15 ;DEC D
instr fetch_DIR8, op_nop, store_D ;16 nn ;LD D,n
instr fetch_DIR8, op_nop, store_pcrel ;18 oo ;JR o
instr fetch_DE, op_ADDHL, store_nop ;19 ;ADD HL,DE
instr fetch_MDE, op_nop, store_nop ;1A ;LD A,(DE)
-instr fetch_DE, op_DEC16, store_DE ;1B ;DEC DE
+;instr fetch_DE, op_DEC16, store_DE ;1B ;DEC DE
+instr fetch_nop, op_DECDE, store_nop ;1B ;DEC DE
instr fetch_E, op_INC, store_E ;1C ;INC E
instr fetch_E, op_DEC, store_E ;1D ;DEC E
instr fetch_DIR8, op_nop, store_E ;1E nn ;LD E,n
instr fetch_DIR8, op_IFNZ, store_pcrel ;20 oo ;JR NZ,o
instr fetch_DIR16, op_nop, store_HL ;21 nn nn ;LD HL,nn
instr fetch_DIR16, op_STHL, store_nop ;22 nn nn ;LD (nn),HL
-instr fetch_HL, op_INC16, store_HL ;23 ;INC HL
+;instr fetch_HL, op_INC16, store_HL ;23 ;INC HL
+instr fetch_nop, op_INCHL, store_nop ;23 ;INC HL
instr fetch_H, op_INC, store_H ;24 ;INC H
instr fetch_H, op_DEC, store_H ;25 ;DEC H
instr fetch_DIR8, op_nop, store_H ;26 nn ;LD H,n
instr fetch_DIR8, op_IFZ, store_pcrel ;28 oo ;JR Z,o
instr fetch_HL, op_ADDHL, store_nop ;29 ;ADD HL,HL
instr fetch_DIR16, op_RMEM16, store_HL ;2A nn nn ;LD HL,(nn)
-instr fetch_HL, op_DEC16, store_HL ;2B ;DEC HL
+;instr fetch_HL, op_DEC16, store_HL ;2B ;DEC HL
+instr fetch_nop, op_DECHL, store_nop ;2B ;DEC HL
instr fetch_L, op_INC, store_L ;2C ;INC L
instr fetch_L, op_DEC, store_L ;2D ;DEC L
instr fetch_DIR8, op_nop, store_L ;2E nn ;LD L,n
fetchmxx1:
mem_read_ds opl, z_pc ;get displacement
adiw z_pcl,1
- clr oph ;sign extend
- tst opl
- brpl fetchmxx2
- com oph
-fetchmxx2:
+ mov oph,opl ;sign extend
+ lsl oph
+ sbc oph,oph
add xl,opl ;add displacement
adc xh,oph
mem_read_d opl ;get operand
storemxx1:
mem_read_s z_pc ;get displacement
adiw z_pcl,1
- clr temp2 ;sign extend
- tst temp
- brpl storemxx2
- com temp2
-storemxx2:
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_write_s opl ;store operand
mem_read_s z_pc ;get displacement
adiw z_pcl,1
adiw z_pcl,1
- clr temp2 ;sign extend
- tst temp
- brpl storemxx22
- com temp2
-storemxx22:
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_write_s opl ;store operand
;----------------------------------------------------------------
;|EX [SP],IX|------|Exchange |[SP]<->IX |
;|EX [SP],IY|------|Exchange |[SP]<->IY |
-;
+;
checkspace PC, 13
do_op_EXxx:
checkspace PC, 9
do_op_rlc:
- ;Rotate Left Cyclical. All bits move 1 to the
+ ;Rotate Left Cyclical. All bits move 1 to the
;left, the msb becomes c and lsb.
clr temp
lsl opl
adc temp,_0
or opl,temp
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
or z_flags,temp
ret
checkspace PC, 9
-do_op_rrc:
- ;Rotate Right Cyclical. All bits move 1 to the
+do_op_rrc:
+ ;Rotate Right Cyclical. All bits move 1 to the
;right, the lsb becomes c and msb.
lsr opl
brcc PC+2
ori opl,0x80
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, opl,7
ret
checkspace PC, 11
do_op_rl:
- ;Rotate Left. All bits move 1 to the left, the msb
+ ;Rotate Left. All bits move 1 to the left, the msb
;becomes c, c becomes lsb.
clc
sbrc z_flags,ZFL_C
sec
rol opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C
ret
- checkspace PC, 9
+ checkspace PC, 10
do_op_rr:
- ;Rotate Right. All bits move 1 to the right, the lsb
+ ;Rotate Right. All bits move 1 to the right, the lsb
;becomes c, c becomes msb.
ror opl
in temp,sreg ;CY
bmov opl,7, z_flags,ZFL_C ;old CY --> Bit 7
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
- checkspace PC, 8
+ checkspace PC, 9
do_op_sla:
lsl opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
- checkspace PC, 9
+ checkspace PC, 11
do_op_sra:
lsr opl
in temp,sreg
bmov opl,7, opl,6 ;old CY --> Bit 7
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
sec
rol opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
do_op_srl:
lsr opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
;|SET b,m |------|Set bit |m=mv{2^b} |
+ checkspace PC, 2
do_op_BIT7:
ldi temp,0x80
rjmp opbit
+ checkspace PC, 2
do_op_BIT6:
ldi temp,0x40
rjmp opbit
+ checkspace PC, 2
do_op_BIT5:
ldi temp,0x20
rjmp opbit
+ checkspace PC, 2
do_op_BIT4:
ldi temp,0x10
rjmp opbit
+ checkspace PC, 2
do_op_BIT3:
ldi temp,0x08
rjmp opbit
+ checkspace PC, 2
do_op_BIT2:
ldi temp,0x04
rjmp opbit
+ checkspace PC, 2
do_op_BIT1:
ldi temp,0x02
rjmp opbit
+
+ checkspace PC, 7
do_op_BIT0:
ldi temp,0x01
opbit:
- and temp,opl
- in temp,sreg
+ andi z_flags,~((1<<ZFL_N)|(1<<ZFL_Z))
ori z_flags,(1<<ZFL_H)
- andi z_flags,~(1<<ZFL_N)
- bmov z_flags,ZFL_Z, temp,AVR_Z
+ and temp,opl
+ brne opbite
+ ori z_flags,(1<<ZFL_Z)
+opbite:
ret
; ret
-;.macro m_do_store_b
+;.macro m_do_store_b
; std y+oz_b,opl
;.endm
;.equ do_store_b = 0
+ checkspace PC, 2
do_store2_b:
- std y+oz_b,opl
+ mov z_b,opl
ret
+ checkspace PC, 2
do_store2_c:
- std y+oz_c,opl
+ mov z_c,opl
ret
+ checkspace PC, 2
do_store2_d:
- std y+oz_d,opl
+ mov z_d,opl
ret
+ checkspace PC, 2
do_store2_e:
- std y+oz_e,opl
+ mov z_e,opl
ret
+ checkspace PC, 2
do_store2_h:
- std y+oz_h,opl
+ mov z_h,opl
ret
+ checkspace PC, 2
do_store2_l:
- std y+oz_l,opl
+ mov z_l,opl
ret
+ checkspace PC, 2
do_store2_a:
mov z_a,opl
ret
+ checkspace PC, 4
do_fetch2_mhl:
- ldd xh,y+oz_h
- ldd xl,y+oz_l
- mem_read_d opl
+; movw x,z_l
+ mem_read_ds opl, z_hl
ret
opctable CBjmp, PC ;+256
instr fetch_H, op_BIT0, store_nop ;44 ;BIT 0,H
instr fetch_L, op_BIT0, store_nop ;45 ;BIT 0,L
instr fetch2_mhl, op_BIT0, store_nop ;46 ;BIT 0,(HL)
-instr fetch_A, op_BIT0, store_nop ;47 ;BIT 0,A
+instr fetch_A, op_BIT0, store_nop ;47 ;BIT 0,A
instr fetch_B, op_BIT1, store_nop ;48 ;BIT 1,B
instr fetch_C, op_BIT1, store_nop ;49 ;BIT 1,C
instr fetch_D, op_BIT1, store_nop ;4A ;BIT 1,D
instr fetch_nop, op_RLC, store2_E ;03 ;RLC (Ix+d),E
instr fetch_nop, op_RLC, store2_H ;04 ;RLC (Ix+d),H
instr fetch_nop, op_RLC, store2_L ;05 ;RLC (Ix+d),L
-instr fetch_nop, op_RLC, store_nop ;06 ;RLC (Ix+d)
+instr fetch_nop, op_RLC, store_nop ;06 ;RLC (Ix+d)
instr fetch_nop, op_RLC, store2_A ;07 ;RLC (Ix+d),A
instr fetch_nop, op_RRC, store2_B ;08 ;RRC (Ix+d),B
instr fetch_nop, op_RRC, store2_C ;09 ;RRC (Ix+d),C
instr fetch_nop, op_RRC, store2_E ;0B ;RRC (Ix+d),E
instr fetch_nop, op_RRC, store2_H ;0C ;RRC (Ix+d),H
instr fetch_nop, op_RRC, store2_L ;0D ;RRC (Ix+d),L
-instr fetch_nop, op_RRC, store_nop ;0E ;RRC (Ix+d)
+instr fetch_nop, op_RRC, store_nop ;0E ;RRC (Ix+d)
instr fetch_nop, op_RRC, store2_A ;0F ;RRC (Ix+d),A
instr fetch_nop, op_RL, store2_B ;10 ;RL (Ix+d),B
instr fetch_nop, op_RL, store2_C ;11 ;RL (Ix+d),C
instr fetch_nop, op_RL, store2_E ;13 ;RL (Ix+d),E
instr fetch_nop, op_RL, store2_H ;14 ;RL (Ix+d),H
instr fetch_nop, op_RL, store2_L ;15 ;RL (Ix+d),L
-instr fetch_nop, op_RL, store_nop ;16 ;RL (Ix+d)
+instr fetch_nop, op_RL, store_nop ;16 ;RL (Ix+d)
instr fetch_nop, op_RL, store2_A ;17 ;RL (Ix+d),A
instr fetch_nop, op_RR, store2_B ;18 ;RR (Ix+d),B
instr fetch_nop, op_RR, store2_C ;19 ;RR (Ix+d),C
instr fetch_nop, op_RR, store2_E ;1B ;RR (Ix+d),E
instr fetch_nop, op_RR, store2_H ;1C ;RR (Ix+d),H
instr fetch_nop, op_RR, store2_L ;1D ;RR (Ix+d),L
-instr fetch_nop, op_RR, store_nop ;1E ;RR (Ix+d)
+instr fetch_nop, op_RR, store_nop ;1E ;RR (Ix+d)
instr fetch_nop, op_RR, store2_A ;1F ;RR (Ix+d),A
instr fetch_nop, op_SLA, store2_B ;20 ;SLA (Ix+d),B
instr fetch_nop, op_SLA, store2_C ;21 ;SLA (Ix+d),C
instr fetch_nop, op_SLA, store2_E ;23 ;SLA (Ix+d),E
instr fetch_nop, op_SLA, store2_H ;24 ;SLA (Ix+d),H
instr fetch_nop, op_SLA, store2_L ;25 ;SLA (Ix+d),L
-instr fetch_nop, op_SLA, store_nop ;26 ;SLA (Ix+d)
+instr fetch_nop, op_SLA, store_nop ;26 ;SLA (Ix+d)
instr fetch_nop, op_SLA, store2_A ;27 ;SLA (Ix+d),A
instr fetch_nop, op_SRA, store2_B ;28 ;SRA (Ix+d),B
instr fetch_nop, op_SRA, store2_C ;29 ;SRA (Ix+d),C
instr fetch_nop, op_SRA, store2_E ;2B ;SRA (Ix+d),E
instr fetch_nop, op_SRA, store2_H ;2C ;SRA (Ix+d),H
instr fetch_nop, op_SRA, store2_L ;2D ;SRA (Ix+d),L
-instr fetch_nop, op_SRA, store_nop ;2E ;SRA (Ix+d)
+instr fetch_nop, op_SRA, store_nop ;2E ;SRA (Ix+d)
instr fetch_nop, op_SRA, store2_A ;2F ;SRA (Ix+d),A
instr fetch_nop, op_SLL, store2_B ;30 ;SLL (Ix+d),B
instr fetch_nop, op_SLL, store2_C ;31 ;SLL (Ix+d),C
instr fetch_nop, op_SLL, store2_E ;33 ;SLL (Ix+d),E
instr fetch_nop, op_SLL, store2_H ;34 ;SLL (Ix+d),H
instr fetch_nop, op_SLL, store2_L ;35 ;SLL (Ix+d),L
-instr fetch_nop, op_SLL, store_nop ;36 ;SLL (Ix+d)
+instr fetch_nop, op_SLL, store_nop ;36 ;SLL (Ix+d)
instr fetch_nop, op_SLL, store2_A ;37 ;SLL (Ix+d),A
instr fetch_nop, op_SRL, store2_B ;38 ;SRL (Ix+d),B
instr fetch_nop, op_SRL, store2_C ;39 ;SRL (Ix+d),C
instr fetch_nop, op_SRL, store2_E ;3B ;SRL (Ix+d),E
instr fetch_nop, op_SRL, store2_H ;3C ;SRL (Ix+d),H
instr fetch_nop, op_SRL, store2_L ;3D ;SRL (Ix+d),L
-instr fetch_nop, op_SRL, store_nop ;3E ;SRL (Ix+d)
+instr fetch_nop, op_SRL, store_nop ;3E ;SRL (Ix+d)
instr fetch_nop, op_SRL, store2_A ;3F ;SRL (Ix+d),A
instr fetch_nop, op_BIT0, store_nop ;40 ;BIT 0,(Ix+d),B
instr fetch_nop, op_BIT0, store_nop ;41 ;BIT 0,(Ix+d),C
instr fetch_nop, op_BIT0, store_nop ;44 ;BIT 0,(Ix+d),H
instr fetch_nop, op_BIT0, store_nop ;45 ;BIT 0,(Ix+d),L
instr fetch_nop, op_BIT0, store_nop ;46 ;BIT 0,(Ix+d)
-instr fetch_nop, op_BIT0, store_nop ;47 ;BIT 0,(Ix+d),A
+instr fetch_nop, op_BIT0, store_nop ;47 ;BIT 0,(Ix+d),A
instr fetch_nop, op_BIT1, store_nop ;48 ;BIT 1,(Ix+d),B
instr fetch_nop, op_BIT1, store_nop ;49 ;BIT 1,(Ix+d),C
instr fetch_nop, op_BIT1, store_nop ;4A ;BIT 1,(Ix+d),D
instr fetch_nop, op_SET7, store_nop ;FE ;SET 7,(Ix+d)
instr fetch_nop, op_SET7, store2_A ;FF ;SET 7,(Ix+d),A
-do_fetch_0:
+.macro m_do_fetch_0
ldi opl,0
- ret
+.endm
+.equ do_fetch_0 = 0
+; ldi opl,0
+; ret
;----------------------------------------------------------------
;|Mnemonic |SZHPNC|Description |Notes |
do_op_in: ; in opl,(opl)
.if PORT_DEBUG
- push opl
+ push opl
cp opl,_0 ; don't debug port 0 (con stat)
breq dbg_op_in_1
printnewline
mov temp,opl
lcall printhex
printstring " -> ("
- ldd temp,y+oz_c
+ mov temp,z_c
lcall printhex
printstring ") "
.endif
mov temp,opl
- ldd temp2,y+oz_c
+ mov temp2,z_c
lcall portWrite
ret
do_op_stbc: ;store bc to mem loc in opl:h
movw xl,opl
- ldd temp,y+oz_c
- mem_write
+ mem_write_s z_c
adiw xl,1
- ldd temp,y+oz_b
- mem_write
+ mem_write_s z_b
ret
;----------------------------------------------------------------
;
do_op_stde: ;store de to mem loc in opl:h
movw xl,opl
- ldd temp,y+oz_e
- mem_write
+ mem_write_s z_e
adiw xl,1
- ldd temp,y+oz_d
- mem_write
+ mem_write_s z_d
ret
;----------------------------------------------------------------
;
do_op_ADCHL:
- ldd temp,y+oz_l
- ldd temp2,y+oz_h
- clc
- sbrc z_flags,ZFL_C
- sec
- adc opl,temp
- in temp,sreg ; save lower Z
- adc oph,temp2
- in temp2,sreg
- std y+oz_l,opl
- std y+oz_h,oph
- and temp,temp2 ; 16bit Z
+ lsr z_flags ; ZFL_C --> Carry
ldi z_flags,0 ; clear N
+ adc z_l,opl
+ in temp,sreg ; save lower Z
+ adc z_h,oph
+ in temp2,sreg
+
+ and temp,temp2 ; 16bit Z
bmov z_flags,ZFL_C, temp2,AVR_C
bmov z_flags,ZFL_P, temp2,AVR_V
bmov z_flags,ZFL_H, temp2,AVR_H
checkspace PC, 24
do_op_sbchl:
- ldd temp,y+oz_l
- ldd temp2,y+oz_h
- cp temp,opl ; set z
- clc
- sbrc z_flags,ZFL_C
- sec
- sbc temp,opl
- sbc temp2,oph
- std y+oz_l,temp
- std y+oz_h,temp2
+ lsr z_flags ; get Z80 carry
+ sez ; set z
+ sbc z_l,opl
+ sbc z_h,oph
in temp,sreg
- ldi z_flags,(1<<ZFL_N) ; set N
+ ldi z_flags,(1<<ZFL_N) ; set N
bmov z_flags,ZFL_C, temp,AVR_C
bmov z_flags,ZFL_P, temp,AVR_V
bmov z_flags,ZFL_H, temp,AVR_H
ldd z_a,y+oz_r
op_ldar1:
bst z_flags,ZFL_C ;save C
- ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
bld z_flags,ZFL_C ;
ldd temp,y+oz_istat
bmov z_flags,ZFL_P, temp,IFF2
or temp,oph
mov z_a,temp
bst z_flags,ZFL_C ;save C
- ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
bld z_flags,ZFL_C ;
ret
or temp,oph
mov z_a,temp
bst z_flags,ZFL_C ;save C
- ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
bld z_flags,ZFL_C ;
ret
;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
;
- checkspace PC, 19
+ checkspace PC, 13
op_LDxx_common:
- ldd xh,y+oz_h ;H
- ldd xl,y+oz_l ;L
-; mem_read_ds temp, z
- lcall dram_read ; temp = (HL)
- movw z,x
-
- ldd xh,y+oz_d ;D
- ldd xl,y+oz_e ;E
-; mem_write_ds x, temp
- lcall dram_write ; (DE) = temp
-
- ldd oph,y+oz_b ;B
- ldd opl,y+oz_c ;C
+; movw x,z_l ;
+; lcall dram_read ; temp = (HL)
+ mem_read_ds temp, z_hl
+; movw x,z_e ;
+; lcall dram_write ; (DE) = temp
+ mem_write_ds z_de, temp
cbr z_flags,(1<<ZFL_H) | (1<<ZFL_P) | (1<<ZFL_N)
- subi opl,1
- sbci oph,0
+
+ movw x,z_c
+ sbiw x,1 ;BC--
+ movw z_c,x
breq PC+2
sbr z_flags,(1<<ZFL_P)
- std y+oz_c,opl ;C
- std y+oz_b,oph ;B
ret
- checkspace PC, 8
+ checkspace PC, 6
do_op_LDI:
rcall op_LDxx_common
- adiw z,1
- adiw x,1
- std y+oz_e,xl ;E
- std y+oz_d,xh ;D
- std y+oz_l,zl ;L
- std y+oz_h,zh ;H
+ sub z_e,_255 ;-low(-1) DE++
+ sbc z_d,_255 ;-high(-1)
+ sub z_l,_255 ;-low(-1) HL++
+ sbc z_h,_255 ;-high(-1)
ret
- checkspace PC, 8
+ checkspace PC, 6
do_op_LDD:
rcall op_LDxx_common
- sbiw z,1
- sbiw x,1
- std y+oz_e,xl ;E
- std y+oz_d,xh ;D
- std y+oz_l,zl ;L
- std y+oz_h,zh ;H
+ add z_e,_255 ;+low(-1) DE--
+ adc z_d,_255 ;+high(-1)
+ add z_l,_255 ;+low(-1) HL--
+ adc z_h,_255 ;+high(-1)
ret
checkspace PC, 5
do_op_LDDR:
rcall do_op_LDD
+#if 1
+ sbrc z_flags,ZFL_P
+ rjmp do_op_LDDR
+ ret
+#else
sbrs z_flags,ZFL_P
ret
sbiw z_pcl,2
ret
+#endif
;----------------------------------------------------------------
;|Mnemonic |SZHPNC|Description |Notes |
checkspace PC, 21
op_CPxx_common:
- ldd xh,y+oz_h ; H
- ldd xl,y+oz_l ; L
- ldd zh,y+oz_b ; B
- ldd zl,y+oz_c ; C
+ movw x,z_l ; HL
+
+ movw z,z_c ;BC
cbr z_flags,(1<<ZFL_S)|(1<<ZFL_Z)|(1<<ZFL_H)|(1<<ZFL_P)
sbr z_flags,(1<<ZFL_N)
lcall dram_read ; temp = (HL)
-; mov temp2,z_a
-; sub temp2,temp ; A - (HL)
- cp z_a,temp
+ cp z_a,temp ; A - (HL)
brpl PC+2
sbr z_flags,(1<<ZFL_S)
sbiw z,1 ; BC--
breq PC+2
sbr z_flags,(1<<ZFL_P)
- std y+oz_c,zl ; C
- std y+oz_b,zh ; B
+ movw z_c,z ;BC
ret
checkspace PC, 5
do_op_CPI:
rcall op_CPxx_common
adiw x,1 ; HL++
- std y+oz_l,xl ; L
- std y+oz_h,xh ; H
+ movw z_l,x ; HL
ret
do_op_CPD:
rcall op_CPxx_common
sbiw x,1 ; HL--
- std y+oz_l,xl ; L
- std y+oz_h,xh ; H
+ movw z_l,x ; HL
ret
checkspace PC, 7
;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
- checkspace PC, 15
+ checkspace PC, 12
op_INxx_common:
cbr z_flags,(1<<ZFL_Z)
sbr z_flags,(1<<ZFL_N)
- ldd temp2,y+oz_c ;C
+ mov temp2,z_c ;C
lcall portRead
- ldd xh,y+oz_h ;H
- ldd xl,y+oz_l ;L
+ movw x,z_l ;HL
lcall dram_write
- ldd temp,y+oz_b ;B
- dec temp
- std y+oz_b,temp ;B
+ dec z_b ;B
brne PC+2
sbr z_flags,(1<<ZFL_Z)
ret
- checkspace PC, 5
+ checkspace PC, 4
do_op_INI:
rcall op_INxx_common
adiw x,1
- std y+oz_l,xl ;L
- std y+oz_h,xh ;H
+ movw z_l,x ;HL
ret
- checkspace PC, 5
+ checkspace PC, 4
do_op_IND:
rcall op_INxx_common
sbiw x,1
- std y+oz_l,xl ;L
- std y+oz_h,xh ;H
+ movw z_l,x ;HL
ret
checkspace PC, 5
;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |
;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |
- checkspace PC, 13
+ checkspace PC, 12
op_OUTxx_common:
- cbr z_flags,(1<<ZFL_Z)
- sbr z_flags,(1<<ZFL_N)
+ movw x,z_l ;HL
lcall dram_read ;temp = (z)
- ldd temp2,y+oz_c ;C
+ mov temp2,z_c ;C
lcall portWrite
- ldd temp,y+oz_b ;B
- dec temp
- std y+oz_b,temp ;B
+ cbr z_flags,(1<<ZFL_Z)
+ sbr z_flags,(1<<ZFL_N)
+ dec z_b ;B
brne PC+2
sbr z_flags,(1<<ZFL_Z)
ret
- checkspace PC, 8
+ checkspace PC, 4
do_op_OUTI:
- ldd xh,y+oz_h ;H
- ldd xl,y+oz_l ;L
- adiw x,1
- std y+oz_l,xl ;L
- std y+oz_h,xh ;H
- sbiw x,1
rcall op_OUTxx_common
+ sub z_l,_255 ;-low(-1)
+ sbc z_h,_255 ;-high(-1)
ret
- checkspace PC, 8
+ checkspace PC, 4
do_op_OUTD:
- ldd xh,y+oz_h ;H
- ldd xl,y+oz_l ;L
- sbiw x,1
- std y+oz_l,xl ;L
- std y+oz_h,xh ;H
- adiw x,1
rcall op_OUTxx_common
+ add z_l,_255 ;+low(-1)
+ adc z_h,_255 ;+high(-1)
ret
checkspace PC, 5
; Lookup table, stolen from z80ex, Z80 emulation library.
; http://z80ex.sourceforge.net/
-; The S, Z, 5 and 3 bits and the parity of the lookup value
+; The S, Z, 5 and 3 bits and the parity of the lookup value
- checkspace PC, 128
+ checkspace PC, 256
.org (PC+255) & 0xff00
; .org opcjmp + 256
-; .org sz53p_table_pos
; .org FLASHEND & 0xff00
-; .org 0x1fff & 0xff00
sz53p_tab:
.db 0x44,0x00,0x00,0x04,0x00,0x04,0x04,0x00
.db 0xac,0xa8,0xa8,0xac,0xa8,0xac,0xac,0xa8
.db 0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0
.db 0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac
-
-; vim:set ts=8 noet nowrap
+; vim:set ts=8 noet nowrap
projects / avrcpm.git / blobdiff