; along with this program. If not, see <http://www.gnu.org/licenses/>.
-;FUSE_H=0xDF
-;FUSE_L=0xF7
-.include "m88def.inc"
-;device ATmega88
+#if defined atmega8
+ .include "m8def.inc"
+
+#elif defined atmega48
+ .include "m48def.inc"
+#else /* default */
+ .include "m88def.inc"
+ ;FUSE_H=0xDF
+ ;FUSE_L=0xF7
+#endif
+
+#ifndef F_CPU
+ #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
+#endif
+#ifndef BAUD
+ #define BAUD 38400 /* console baud rate */
+#endif
+
+;
+.equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; clever rounding
+
+#define REFR_RATE 64000 /* dram refresh rate. most drams need 1/15.6µs */
+#define REFR_PRE 8 /* timer prescale factor */
+#define REFR_CS 0x02 /* timer clock select for 1/8 */
+#define REFR_CNT F_CPU / REFR_RATE / REFR_PRE
+
+
+#if defined __ATmega8__
+ .equ refr_vect = OC2addr
+#else
+ .equ refr_vect = OC2Aaddr
+#endif
+
.equ MMC_DEBUG = 0
.equ INS_DEBUG = 0
.equ ram_a6 = 6
.equ ram_a7 = 7
+
;Port B
.equ ram_a4 = 0
.equ ram_a3 = 1
;SRAM
+.dseg
;Sector buffer for 512 byte reads/writes from/to SD-card
-.equ sectbuff = 0x200
+sectbuff:
+ .byte 512
+
+
+.cseg
.org 0
rjmp start ; reset vector
- nop ; ext int 0
- nop ; ext int 1
- nop ; pcint0
- nop ; pcint1
- nop ; pcint2
- nop ; wdt
+.org refr_vect
rjmp refrint ; tim2cmpa
- nop ; tim2cmpb
- nop ; tim2ovf
+.org INT_VECTORS_SIZE
start:
ldi temp,low(RAMEND) ; top of memory
out SPL,temp ; init stack pointer
; - Kill wdt
wdr
+#if defined __ATmega8__
+ ldi temp,0
+ out MCUCSR,temp
+
+ ldi temp,(1<<WDCE) | (1<<WDE)
+ out WDTCSR,temp
+ ldi temp,(1<<WDCE)
+ out WDTCSR,temp
+#else
ldi temp,0
out MCUSR,temp
- ldi temp,0x18
+
+ ldi temp,(1<<WDCE) | (1<<WDE)
sts WDTCSR,temp
- ldi temp,0x10
+ ldi temp,(1<<WDCE)
sts WDTCSR,temp
-
+#endif
; - Setup Ports
ldi temp,$3F
ldi temp,$22
out DDRC,temp
- sbi portc,ram_w
- sbi portc,ram_cas
- sbi portb,ram_ras
- sbi portd,ram_oe
- sbi portd,mmc_cs
+ sbi PORTC,ram_w
+ sbi PORTC,ram_cas
+ sbi PORTB,ram_ras
+ sbi PORTD,ram_oe
+ sbi PORTD,mmc_cs
; - Init serial port
- ldi temp,$18
- sts ucsr0b,temp
- ldi temp,$6
- sts ucsr0c,temp
- ldi temp,32
- sts ubrr0l,temp
- ldi temp,0
- sts ubrr0h,temp
+#if defined __ATmega8__
+ ldi temp, (1<<TXEN) | (1<<RXEN)
+ out UCSRB,temp
+ ldi temp, (1<<URSEL) | (1<<UCSZ1) | (1<<UCSZ0)
+ out UCSRC,temp
+ ldi temp, HIGH(UBRR_VAL)
+ out UBRRH,temp
+ ldi temp, LOW(UBRR_VAL)
+ out UBRRL,temp
+#else
+ ldi temp, (1<<TXEN0) | (1<<RXEN0)
+ sts UCSR0B,temp
+ ldi temp, (1<<UCSZ01) | (1<<UCSZ00)
+ sts UCSR0C,temp
+ ldi temp, HIGH(UBRR_VAL)
+ sts UBRR0H,temp
+ ldi temp, LOW(UBRR_VAL)
+ sts UBRR0L,temp
+#endif
;Init timer2. Refresh-call should happen every (8ms/512)=312 cycles.
- ldi temp,2
- sts tccr2a,temp
- ldi temp,2 ;clk/8
- sts tccr2b,temp
- ldi temp,39 ;=312 cycles
- sts ocr2a,temp
- ldi temp,2
- sts timsk2,temp
+
+#ifdef __ATmega8__
+ ldi temp,REFR_CNT
+ out OCR2,temp
+ ldi temp,(1<<WGM21) | REFR_CS ;CTC, clk/REFR_PRE
+ out TCCR2,temp
+ ldi temp, (1<<OCIE2)
+ out TIMSK,temp
+#else
+ ldi temp,REFR_CNT ;=312 cycles
+ sts OCR2A,temp
+ ldi temp, (1<<WGM21)
+ sts TCCR2A,temp
+ ldi temp, REFR_CS ;clk/REFR_PRE
+ sts TCCR2B,temp
+ ldi temp,(1<<OCIE2A)
+ sts TIMSK2,temp
+#endif
sei
+
.if BOOTWAIT
push temp
ldi temp,0
conStatus:
- lds temp2,UCSR0A
ldi temp,0
- sbrc temp2,7
+#if defined __ATmega8__
+ sbic UCSRA,RXC
+#else
+ lds temp2,UCSR0A
+ sbrc temp2,RXC0
+#endif
ldi temp,0xff
ret
out SPCR,temp
;Init start: send 80 clocks with cs disabled
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
ldi temp2,20
mmcInitLoop:
dec temp2
brne mmcInitLoop
- cbi portd,mmc_cs
+ cbi PORTD,mmc_cs
rcall mmcByteNoSend
rcall mmcByteNoSend
rcall mmcByteNoSend
rcall mmcByteNoSend
rcall mmcByteNoSend
rcall mmcByteNoSend
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
rcall mmcByteNoSend
rcall mmcByteNoSend
rcall mmcByteNoSend
rcall mmcByteNoSend
;Send init command
- cbi portd,mmc_cs
+ cbi PORTD,mmc_cs
ldi temp,0xff ;dummy
rcall mmcByte
ldi temp,0xff ;dummy
ldi temp2,0
rcall mmcWaitResp
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
rcall mmcByteNoSend
mmcInitOcrLoop:
push temp2
- cbi portd,mmc_cs
+ cbi PORTD,mmc_cs
ldi temp,0xff ;dummy
rcall mmcByte
ldi temp,0x41 ;cmd
cpi temp,0
breq mmcInitOcrLoopDone
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
rcall mmcByteNoSend
pop temp2
mmcInitOcrLoopDone:
pop temp2
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
rcall mmcByteNoSend
ldi temp,0
ldi temp,0x50
out SPCR,temp
- cbi portd,mmc_cs
+ cbi PORTD,mmc_cs
rcall mmcByteNoSend
ldi temp,0x51 ;cmd (read sector)
rcall mmcByte
rcall mmcByteNoSend
rcall mmcByteNoSend
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
rcall mmcByteNoSend
ldi temp,0
ldi temp,0x50
out SPCR,temp
- cbi portd,mmc_cs
+ cbi PORTD,mmc_cs
rcall mmcByteNoSend
ldi temp,0x58 ;cmd (write sector)
cpi temp,0xff
brne mmcwaitwritten
- sbi portd,mmc_cs
+ sbi PORTD,mmc_cs
rcall mmcByteNoSend
ldi temp,0
;Set up wdt to time out after 1 sec.
resetAVR:
cli
- ldi temp,0x10
+#if defined __ATmega8__
+ ldi temp,(1<<WDCE)
+ out WDTCSR,temp
+ ldi temp,(1<<WDCE) | (1<<WDE) | (110<<WDP0)
+ out WDTCSR,temp
+#else
+ ldi temp,(1<<WDCE)
sts WDTCSR,temp
- ldi temp,0x1f
+ ldi temp,(1<<WDCE) | (1<<WDE) | (110<<WDP0)
sts WDTCSR,temp
+#endif
resetwait:
rjmp resetwait
+
; ------------------ DRAM routines -------------
;Sends the address in zh:zl to the ram
dram_setaddr:
push temp
- in temp,portd
+ in temp,PORTD
andi temp,0x17
- out portd,temp
- in temp,portb
+ out PORTD,temp
+ in temp,PORTB
andi temp,0xE0
- out portb,temp
+ out PORTB,temp
sbrc zl,0
- sbi portb,ram_a0
+ sbi PORTB,ram_a0
sbrc zl,1
- sbi portb,ram_a1
+ sbi PORTB,ram_a1
sbrc zl,2
- sbi portb,ram_a2
+ sbi PORTB,ram_a2
sbrc zl,3
- sbi portb,ram_a3
+ sbi PORTB,ram_a3
sbrc zl,4
- sbi portb,ram_a4
+ sbi PORTB,ram_a4
sbrc zl,5
- sbi portd,ram_a5
+ sbi PORTD,ram_a5
sbrc zl,6
- sbi portd,ram_a6
+ sbi PORTD,ram_a6
sbrc zl,7
- sbi portd,ram_a7
+ sbi PORTD,ram_a7
sbrc zh,0
- sbi portd,ram_a8
+ sbi PORTD,ram_a8
pop temp
ret
dram_sendnibble:
push temp2
- in temp2,portc
+ in temp2,PORTC
andi temp2,0xE2
sbrc temp,0
sbrc temp,3
ori temp2,(1<<ram_d4)
- out portc,temp2
+ out PORTC,temp2
pop temp2
ret
rol zh
;z=addr[15-7]
rcall dram_setaddr
- cbi portb,ram_ras
+ cbi PORTB,ram_ras
ldi zh,0
mov zl,adrl
andi zl,0x7F
rcall dram_setaddr
nop
- cbi portc,ram_cas
+ cbi PORTC,ram_cas
nop
nop
- cbi portd,ram_oe
+ cbi PORTD,ram_oe
nop
rcall dram_getnibble
- sbi portd,ram_oe
+ sbi PORTD,ram_oe
swap temp
- sbi portc,ram_cas
+ sbi PORTC,ram_cas
ldi zh,0
mov zl,adrl
ori zl,0x80
rcall dram_setaddr
nop
- cbi portc,ram_cas
+ cbi PORTC,ram_cas
nop
- cbi portd,ram_oe
+ cbi PORTD,ram_oe
nop
nop
rcall dram_getnibble
- sbi portd,ram_oe
- sbi portc,ram_cas
- sbi portb,ram_ras
+ sbi PORTD,ram_oe
+ sbi PORTC,ram_cas
+ sbi PORTB,ram_ras
sei
ret
rcall dram_setaddr
nop
nop
- cbi portb,ram_ras
+ cbi PORTB,ram_ras
ldi zh,0
mov zl,adrl
rcall dram_setaddr
nop
nop
- cbi portc,ram_cas
+ cbi PORTC,ram_cas
nop
nop
- cbi portc,ram_w
+ cbi PORTC,ram_w
nop
nop
nop
- sbi portc,ram_w
- sbi portc,ram_cas
+ sbi PORTC,ram_w
+ sbi PORTC,ram_cas
ldi zh,0
rcall dram_setaddr
swap temp
rcall dram_sendnibble
- cbi portc,ram_cas
+ cbi PORTC,ram_cas
nop
nop
- cbi portc,ram_w
+ cbi PORTC,ram_w
nop
nop
- sbi portc,ram_w
+ sbi PORTC,ram_w
nop
nop
- sbi portc,ram_cas
- sbi portb,ram_ras
+ sbi PORTC,ram_cas
+ sbi PORTB,ram_ras
in temp,ddrc
andi temp,0xE2
out ddrc,temp
- in temp,portc
+ in temp,PORTC
andi temp,0xE2
- out portc,temp
+ out PORTC,temp
sei
ret
refrint:
nop
+; nop
+; nop
+ cbi PORTC,ram_cas
+; nop
+; nop
+; nop
+; nop
+ cbi PORTB,ram_ras
nop
- nop
- cbi portc,ram_cas
- nop
- nop
- nop
- nop
- cbi portb,ram_ras
- nop
- nop
- nop
- nop
- sbi portc,ram_cas
- nop
- nop
- nop
- nop
- sbi portb,ram_ras
- nop
- nop
- nop
- nop
- nop
+; nop
+; nop
+; nop
+ sbi PORTC,ram_cas
+; nop
+; nop
+; nop
+; nop
+ sbi PORTB,ram_ras
+; nop
+; nop
+; nop
+; nop
+; nop
reti
;Fetches a char from the uart to temp. If none available, waits till one is.
uartgetc:
- lds temp,ucsr0a
- sbrs temp,7
+#if defined __ATmega8__
+ sbis UCSRA,RXC
rjmp uartgetc
- lds temp,udr0
+ in temp,UDR
+#else
+ lds temp,UCSR0A
+ sbrs temp,RXC0
+ rjmp uartgetc
+ lds temp,UDR0
+#endif
ret
;Sends a char from temp to the uart.
uartputc:
+#if defined __ATmega8__
+uartputc_l:
+ sbis UCSRA,UDRE
+ rjmp uartputc_l
+ out UDR,temp
+#else
push temp
uartputc_l:
- lds temp,ucsr0a
- sbrs temp,5
+ lds temp,UCSR0A
+ sbrs temp,UDRE0
rjmp uartputc_l
pop temp
- sts udr0,temp
+ sts UDR0,temp
+#endif
ret
; ------------ Fetch phase stuff -----------------
;
;I sure hope I got the mapping between flags and instructions correct...
-;----------------------------------------------------------------\r
-;| |\r
-;| Zilog |\r
-;| |\r
-;| ZZZZZZZ 88888 000 |\r
-;| Z 8 8 0 0 |\r
-;| Z 8 8 0 0 0 |\r
-;| Z 88888 0 0 0 |\r
-;| Z 8 8 0 0 0 |\r
-;| Z 8 8 0 0 |\r
-;| ZZZZZZZ 88888 000 |\r
-;| |\r
-;| Z80 MICROPROCESSOR Instruction Set Summary |\r
-;| |\r
-;----------------------------------------------------------------\r
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;|----------+------+---------------------+----------------------|\r
-;|ADC A,s |***V0*|Add with Carry |A=A+s+CY |\r
-;|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |\r
-;|ADD A,s |***V0*|Add |A=A+s |\r
-;|ADD HL,ss |--?-0*|Add |HL=HL+ss |\r
-;|ADD IX,pp |--?-0*|Add |IX=IX+pp |\r
-;|ADD IY,rr |--?-0*|Add |IY=IY+rr |\r
-;|AND s |***P00|Logical AND |A=A&s |\r
-;|BIT b,m |?*1?0-|Test Bit |m&{2^b} |\r
-;|CALL cc,nn|------|Conditional Call |If cc CALL |\r
-;|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |\r
-;|CCF |--?-0*|Complement Carry Flag|CY=~CY |\r
-;|CP s |***V1*|Compare |A-s |\r
-;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|\r
-;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|\r
-;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|\r
-;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|\r
-;|CPL |--1-1-|Complement |A=~A |\r
-;|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |\r
-;|DEC s |***V1-|Decrement |s=s-1 |\r
-;|DEC xx |------|Decrement |xx=xx-1 |\r
-;|DEC ss |------|Decrement |ss=ss-1 |\r
-;|DI |------|Disable Interrupts | |\r
-;|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |\r
-;|EI |------|Enable Interrupts | |\r
-;|EX [SP],HL|------|Exchange |[SP]<->HL |\r
-;|EX [SP],xx|------|Exchange |[SP]<->xx |\r
-;|EX AF,AF' |------|Exchange |AF<->AF' |\r
-;|EX DE,HL |------|Exchange |DE<->HL |\r
-;|EXX |------|Exchange |qq<->qq' (except AF)|\r
-;|HALT |------|Halt | |\r
-;|IM n |------|Interrupt Mode | (n=0,1,2)|\r
-;|IN A,[n] |------|Input |A=[n] |\r
-;|IN r,[C] |***P0-|Input |r=[C] |\r
-;|INC r |***V0-|Increment |r=r+1 |\r
-;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |\r
-;|INC xx |------|Increment |xx=xx+1 |\r
-;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |\r
-;|INC ss |------|Increment |ss=ss+1 |\r
-;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|\r
-;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |\r
-;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|\r
-;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |\r
-;|JP [HL] |------|Unconditional Jump |PC=[HL] |\r
-;|JP [xx] |------|Unconditional Jump |PC=[xx] |\r
-;|JP nn |------|Unconditional Jump |PC=nn |\r
-;|JP cc,nn |------|Conditional Jump |If cc JP |\r
-;|JR e |------|Unconditional Jump |PC=PC+e |\r
-;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|\r
-;|LD dst,src|------|Load |dst=src |\r
-;|LD A,i |**0*0-|Load |A=i (i=I,R)|\r
-;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |\r
-;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |\r
-;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |\r
-;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |\r
-;|NEG |***V1*|Negate |A=-A |\r
-;|NOP |------|No Operation | |\r
-;|OR s |***P00|Logical inclusive OR |A=Avs |\r
-;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |\r
-;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |\r
-;|OUT [C],r |------|Output |[C]=r |\r
-;|OUT [n],A |------|Output |[n]=A |\r
-;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|\r
-;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|\r
-;|POP xx |------|Pop |xx=[SP]+ |\r
-;|POP qq |------|Pop |qq=[SP]+ |\r
-;|PUSH xx |------|Push |-[SP]=xx |\r
-;|PUSH qq |------|Push |-[SP]=qq |\r
-;|RES b,m |------|Reset bit |m=m&{~2^b} |\r
-;|RET |------|Return |PC=[SP]+ |\r
-;|RET cc |------|Conditional Return |If cc RET |\r
-;|RETI |------|Return from Interrupt|PC=[SP]+ |\r
-;|RETN |------|Return from NMI |PC=[SP]+ |\r
-;|RL m |**0P0*|Rotate Left |m={CY,m}<- |\r
-;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |\r
-;|RLC m |**0P0*|Rotate Left Circular |m=m<- |\r
-;|RLCA |--0-0*|Rotate Left Circular |A=A<- |\r
-;----------------------------------------------------------------\r
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;|----------+------+---------------------+----------------------|\r
-;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|\r
-;|RR m |**0P0*|Rotate Right |m=->{CY,m} |\r
-;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |\r
-;|RRC m |**0P0*|Rotate Right Circular|m=->m |\r
-;|RRCA |--0-0*|Rotate Right Circular|A=->A |\r
-;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|\r
-;|RST p |------|Restart | (p=0H,8H,10H,...,38H)|\r
-;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |\r
-;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |\r
-;|SCF |--0-01|Set Carry Flag |CY=1 |\r
-;|SET b,m |------|Set bit |m=mv{2^b} |\r
-;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |\r
-;|SRA m |**0P0*|Shift Right Arith. |m=m/2 |\r
-;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |\r
-;|SUB s |***V1*|Subtract |A=A-s |\r
-;|XOR s |***P00|Logical Exclusive OR |A=Axs |\r
-;|----------+------+--------------------------------------------|\r
-;| F |-*01? |Flag unaffected/affected/reset/set/unknown |\r
-;| S |S |Sign flag (Bit 7) |\r
-;| Z | Z |Zero flag (Bit 6) |\r
-;| HC | H |Half Carry flag (Bit 4) |\r
-;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) |\r
-;| N | N |Add/Subtract flag (Bit 1) |\r
-;| CY | C|Carry flag (Bit 0) |\r
-;|-----------------+--------------------------------------------|\r
-;| n |Immediate addressing |\r
-;| nn |Immediate extended addressing |\r
-;| e |Relative addressing (PC=PC+2+offset) |\r
-;| [nn] |Extended addressing |\r
-;| [xx+d] |Indexed addressing |\r
-;| r |Register addressing |\r
-;| [rr] |Register indirect addressing |\r
-;| |Implied addressing |\r
-;| b |Bit addressing |\r
-;| p |Modified page zero addressing (see RST) |\r
-;|-----------------+--------------------------------------------|\r
-;|DEFB n(,...) |Define Byte(s) |\r
-;|DEFB 'str'(,...) |Define Byte ASCII string(s) |\r
-;|DEFS nn |Define Storage Block |\r
-;|DEFW nn(,...) |Define Word(s) |\r
-;|-----------------+--------------------------------------------|\r
-;| A B C D E |Registers (8-bit) |\r
-;| AF BC DE HL |Register pairs (16-bit) |\r
-;| F |Flag register (8-bit) |\r
-;| I |Interrupt page address register (8-bit) |\r
-;| IX IY |Index registers (16-bit) |\r
-;| PC |Program Counter register (16-bit) |\r
-;| R |Memory Refresh register |\r
-;| SP |Stack Pointer register (16-bit) |\r
-;|-----------------+--------------------------------------------|\r
-;| b |One bit (0 to 7) |\r
-;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |\r
-;| d |One-byte expression (-128 to +127) |\r
-;| dst |Destination s, ss, [BC], [DE], [HL], [nn] |\r
-;| e |One-byte expression (-126 to +129) |\r
-;| m |Any register r, [HL] or [xx+d] |\r
-;| n |One-byte expression (0 to 255) |\r
-;| nn |Two-byte expression (0 to 65535) |\r
-;| pp |Register pair BC, DE, IX or SP |\r
-;| qq |Register pair AF, BC, DE or HL |\r
-;| qq' |Alternative register pair AF, BC, DE or HL |\r
-;| r |Register A, B, C, D, E, H or L |\r
-;| rr |Register pair BC, DE, IY or SP |\r
-;| s |Any register r, value n, [HL] or [xx+d] |\r
-;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] |\r
-;| ss |Register pair BC, DE, HL or SP |\r
-;| xx |Index register IX or IY |\r
-;|-----------------+--------------------------------------------|\r
-;| + - * / ^ |Add/subtract/multiply/divide/exponent |\r
-;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |\r
-;| <- -> |Rotate left/right |\r
-;| [ ] |Indirect addressing |\r
-;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|\r
-;| { } |Combination of operands |\r
-;| # |Also BC=BC-1,DE=DE-1 |\r
-;| ## |Only lower 4 bits of accumulator A used |\r
-;----------------------------------------------------------------\r
-\r
+;----------------------------------------------------------------
+;| |
+;| Zilog |
+;| |
+;| ZZZZZZZ 88888 000 |
+;| Z 8 8 0 0 |
+;| Z 8 8 0 0 0 |
+;| Z 88888 0 0 0 |
+;| Z 8 8 0 0 0 |
+;| Z 8 8 0 0 |
+;| ZZZZZZZ 88888 000 |
+;| |
+;| Z80 MICROPROCESSOR Instruction Set Summary |
+;| |
+;----------------------------------------------------------------
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;|----------+------+---------------------+----------------------|
+;|ADC A,s |***V0*|Add with Carry |A=A+s+CY |
+;|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |
+;|ADD A,s |***V0*|Add |A=A+s |
+;|ADD HL,ss |--?-0*|Add |HL=HL+ss |
+;|ADD IX,pp |--?-0*|Add |IX=IX+pp |
+;|ADD IY,rr |--?-0*|Add |IY=IY+rr |
+;|AND s |***P00|Logical AND |A=A&s |
+;|BIT b,m |?*1?0-|Test Bit |m&{2^b} |
+;|CALL cc,nn|------|Conditional Call |If cc CALL |
+;|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |
+;|CCF |--?-0*|Complement Carry Flag|CY=~CY |
+;|CP s |***V1*|Compare |A-s |
+;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
+;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
+;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
+;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
+;|CPL |--1-1-|Complement |A=~A |
+;|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |
+;|DEC s |***V1-|Decrement |s=s-1 |
+;|DEC xx |------|Decrement |xx=xx-1 |
+;|DEC ss |------|Decrement |ss=ss-1 |
+;|DI |------|Disable Interrupts | |
+;|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |
+;|EI |------|Enable Interrupts | |
+;|EX [SP],HL|------|Exchange |[SP]<->HL |
+;|EX [SP],xx|------|Exchange |[SP]<->xx |
+;|EX AF,AF' |------|Exchange |AF<->AF' |
+;|EX DE,HL |------|Exchange |DE<->HL |
+;|EXX |------|Exchange |qq<->qq' (except AF)|
+;|HALT |------|Halt | |
+;|IM n |------|Interrupt Mode | (n=0,1,2)|
+;|IN A,[n] |------|Input |A=[n] |
+;|IN r,[C] |***P0-|Input |r=[C] |
+;|INC r |***V0-|Increment |r=r+1 |
+;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |
+;|INC xx |------|Increment |xx=xx+1 |
+;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |
+;|INC ss |------|Increment |ss=ss+1 |
+;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|
+;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
+;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|
+;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
+;|JP [HL] |------|Unconditional Jump |PC=[HL] |
+;|JP [xx] |------|Unconditional Jump |PC=[xx] |
+;|JP nn |------|Unconditional Jump |PC=nn |
+;|JP cc,nn |------|Conditional Jump |If cc JP |
+;|JR e |------|Unconditional Jump |PC=PC+e |
+;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|
+;|LD dst,src|------|Load |dst=src |
+;|LD A,i |**0*0-|Load |A=i (i=I,R)|
+;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |
+;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |
+;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |
+;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
+;|NEG |***V1*|Negate |A=-A |
+;|NOP |------|No Operation | |
+;|OR s |***P00|Logical inclusive OR |A=Avs |
+;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |
+;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |
+;|OUT [C],r |------|Output |[C]=r |
+;|OUT [n],A |------|Output |[n]=A |
+;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|
+;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|
+;|POP xx |------|Pop |xx=[SP]+ |
+;|POP qq |------|Pop |qq=[SP]+ |
+;|PUSH xx |------|Push |-[SP]=xx |
+;|PUSH qq |------|Push |-[SP]=qq |
+;|RES b,m |------|Reset bit |m=m&{~2^b} |
+;|RET |------|Return |PC=[SP]+ |
+;|RET cc |------|Conditional Return |If cc RET |
+;|RETI |------|Return from Interrupt|PC=[SP]+ |
+;|RETN |------|Return from NMI |PC=[SP]+ |
+;|RL m |**0P0*|Rotate Left |m={CY,m}<- |
+;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |
+;|RLC m |**0P0*|Rotate Left Circular |m=m<- |
+;|RLCA |--0-0*|Rotate Left Circular |A=A<- |
+;----------------------------------------------------------------
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;|----------+------+---------------------+----------------------|
+;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|
+;|RR m |**0P0*|Rotate Right |m=->{CY,m} |
+;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |
+;|RRC m |**0P0*|Rotate Right Circular|m=->m |
+;|RRCA |--0-0*|Rotate Right Circular|A=->A |
+;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|
+;|RST p |------|Restart | (p=0H,8H,10H,...,38H)|
+;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |
+;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |
+;|SCF |--0-01|Set Carry Flag |CY=1 |
+;|SET b,m |------|Set bit |m=mv{2^b} |
+;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |
+;|SRA m |**0P0*|Shift Right Arith. |m=m/2 |
+;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |
+;|SUB s |***V1*|Subtract |A=A-s |
+;|XOR s |***P00|Logical Exclusive OR |A=Axs |
+;|----------+------+--------------------------------------------|
+;| F |-*01? |Flag unaffected/affected/reset/set/unknown |
+;| S |S |Sign flag (Bit 7) |
+;| Z | Z |Zero flag (Bit 6) |
+;| HC | H |Half Carry flag (Bit 4) |
+;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) |
+;| N | N |Add/Subtract flag (Bit 1) |
+;| CY | C|Carry flag (Bit 0) |
+;|-----------------+--------------------------------------------|
+;| n |Immediate addressing |
+;| nn |Immediate extended addressing |
+;| e |Relative addressing (PC=PC+2+offset) |
+;| [nn] |Extended addressing |
+;| [xx+d] |Indexed addressing |
+;| r |Register addressing |
+;| [rr] |Register indirect addressing |
+;| |Implied addressing |
+;| b |Bit addressing |
+;| p |Modified page zero addressing (see RST) |
+;|-----------------+--------------------------------------------|
+;|DEFB n(,...) |Define Byte(s) |
+;|DEFB 'str'(,...) |Define Byte ASCII string(s) |
+;|DEFS nn |Define Storage Block |
+;|DEFW nn(,...) |Define Word(s) |
+;|-----------------+--------------------------------------------|
+;| A B C D E |Registers (8-bit) |
+;| AF BC DE HL |Register pairs (16-bit) |
+;| F |Flag register (8-bit) |
+;| I |Interrupt page address register (8-bit) |
+;| IX IY |Index registers (16-bit) |
+;| PC |Program Counter register (16-bit) |
+;| R |Memory Refresh register |
+;| SP |Stack Pointer register (16-bit) |
+;|-----------------+--------------------------------------------|
+;| b |One bit (0 to 7) |
+;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |
+;| d |One-byte expression (-128 to +127) |
+;| dst |Destination s, ss, [BC], [DE], [HL], [nn] |
+;| e |One-byte expression (-126 to +129) |
+;| m |Any register r, [HL] or [xx+d] |
+;| n |One-byte expression (0 to 255) |
+;| nn |Two-byte expression (0 to 65535) |
+;| pp |Register pair BC, DE, IX or SP |
+;| qq |Register pair AF, BC, DE or HL |
+;| qq' |Alternative register pair AF, BC, DE or HL |
+;| r |Register A, B, C, D, E, H or L |
+;| rr |Register pair BC, DE, IY or SP |
+;| s |Any register r, value n, [HL] or [xx+d] |
+;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] |
+;| ss |Register pair BC, DE, HL or SP |
+;| xx |Index register IX or IY |
+;|-----------------+--------------------------------------------|
+;| + - * / ^ |Add/subtract/multiply/divide/exponent |
+;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |
+;| <- -> |Rotate left/right |
+;| [ ] |Indirect addressing |
+;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|
+;| { } |Combination of operands |
+;| # |Also BC=BC-1,DE=DE-1 |
+;| ## |Only lower 4 bits of accumulator A used |
+;----------------------------------------------------------------
+
;ToDo: Parity at more instructions...
do_op_nop:
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|INC r |***V0-|Increment |r=r+1 |\r
-;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |\r
-;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |\r
-;\r
-; OK\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|INC r |***V0-|Increment |r=r+1 |
+;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |
+;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |
+;
+; OK
do_op_inc:
andi z_flags, (1<<ZFL_C) ; bis auf Carry alles auf 0
ldi temp, 1
sbrc opl, 7 ; Sign
ori z_flags, (1<<ZFL_S)
bst temp, AVR_H ; Half Sign
- bld z_flags, ZFL_H\r
- bst temp, AVR_C ; Overflow\r
- bld z_flags, ZFL_P\r
+ bld z_flags, ZFL_H
+ bst temp, AVR_C ; Overflow
+ bld z_flags, ZFL_P
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|DEC s |***V1-|Decrement |s=s-1 |\r
-;\r
-; OK\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|DEC s |***V1-|Decrement |s=s-1 |
+;
+; OK
do_op_dec:
andi z_flags, (1<<ZFL_C) ; bis auf Carry alles auf 0
ori z_flags, (1<<ZFL_N) ; Negation auf 1
bld z_flags, ZFL_S
bst temp, AVR_H ; Half Sign
bld z_flags, ZFL_H
- bst temp, AVR_C ; Underflow\r
- bld z_flags, ZFL_P\r
- ret
-\r
-\r
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|INC xx |------|Increment |xx=xx+1 |\r
-;|INC ss |------|Increment |ss=ss+1 |\r
-;\r
-; OK\r
+ bst temp, AVR_C ; Underflow
+ bld z_flags, ZFL_P
+ ret
+
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|INC xx |------|Increment |xx=xx+1 |
+;|INC ss |------|Increment |ss=ss+1 |
+;
+; OK
do_op_inc16:
ldi temp, 1
ldi temp2, 0
adc oph, temp2
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|DEC xx |------|Decrement |xx=xx-1 |\r
-;|DEC ss |------|Decrement |ss=ss-1 |\r
-;\r
-; OK\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|DEC xx |------|Decrement |xx=xx-1 |
+;|DEC ss |------|Decrement |ss=ss-1 |
+;
+; OK
do_op_dec16:
ldi temp, 1
ldi temp2, 0
sbc oph, temp2
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|RLCA |--0-0*|Rotate Left Circular |A=A<- |\r
-;\r
-; OK\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|RLCA |--0-0*|Rotate Left Circular |A=A<- |
+;
+; OK
do_op_rlc:
;Rotate Left Cyclical. All bits move 1 to the
;left, the msb becomes c and lsb.
do_op_rlc_noc:
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|RRCA |--0-0*|Rotate Right Circular|A=->A |\r
-;\r
-; OK\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|RRCA |--0-0*|Rotate Right Circular|A=->A |
+;
+; OK
do_op_rrc:
;Rotate Right Cyclical. All bits move 1 to the
;right, the lsb becomes c and msb.
do_op_rrc_noc:
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |\r
-;\r
-; OK\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |
+;
+; OK
do_op_rr:
;Rotate Right. All bits move 1 to the right, the lsb
;becomes c, c becomes msb.
bld z_flags,ZFL_C
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_rl:
;Rotate Left. All bits move 1 to the left, the msb
;becomes c, c becomes lsb.
bld z_flags,ZFL_C
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_adda:
ldi z_flags,0
add opl,z_a
bld z_flags,ZFL_C
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_adca:
clc
sbrc z_flags,ZFL_C
andi z_flags,~(1<<ZFL_N)
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_subfa:
mov temp,z_a
sub temp,opl
ori z_flags,(1<<ZFL_N)
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_sbcfa:
mov temp,z_a
clc
ori z_flags,(1<<ZFL_N)
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_anda:
ldi z_flags,0
and opl,z_a
mov temp,opl
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ora:
ldi z_flags,0
or opl,z_a
mov temp,opl
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_xora:
ldi z_flags,0
eor opl,z_a
mov temp,opl
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_addhl:
add opl,z_l
adc oph,z_h
andi z_flags,~(1<<ZFL_N)
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_sthl: ;store hl to mem loc in opl
;ToDo: check flags
mov adrl,opl
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_rmem16:
mov adrl,opl
mov adrh,oph
mov oph,temp
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_rmem8:
mov adrl,opl
mov adrh,oph
mov opl,temp
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_da:
;DAA -> todo
rcall do_op_inv
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_scf:
ori z_flags,(1<<ZFL_C)
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ccf:
ldi temp,(1<<ZFL_C)
eor z_flags,temp
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_cpl:
com opl
ori z_flags,(1<<ZFL_N)|(1<<ZFL_H)
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_push16:
ldi temp,1
ldi temp2,0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_pop16:
mov adrl,z_spl
mov adrh,z_sph
.endif
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_exhl:
mov temp,z_h
mov z_h,oph
mov opl,temp
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_di:
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ei:
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifnz:
sbrs z_flags, ZFL_Z
ret
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifz:
sbrc z_flags, ZFL_Z
ret
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifnc:
sbrs z_flags, ZFL_C
ret
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifc:
sbrc z_flags, ZFL_C
ret
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifpo:
rcall do_op_calcparity
sbrs temp2, 0
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifpe:
rcall do_op_calcparity
sbrc temp2, 0
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifp: ;sign positive, aka s=0
sbrs z_flags, ZFL_S
ret
ldi insdecl,0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_ifm: ;sign negative, aka s=1
sbrc z_flags, ZFL_S
ret
ldi insdecl, 0
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
;Interface with peripherials goes here :)
do_op_outa: ; out (opl),a
.if PORT_DEBUG
rcall portWrite
ret
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;----------------------------------------------------------------\r
-;\r
-; Not yet checked\r
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;
+; Not yet checked
do_op_in: ; in a,(opl)
.if PORT_DEBUG
rcall printstr
.endif
ret
-;----------------------------------------------------------------\r
+;----------------------------------------------------------------
do_op_calcparity:
ldi temp2,1
sbrc parityb,0
andi temp2,1
ret
-;----------------------------------------------------------------\r
+;----------------------------------------------------------------
do_op_inv:
rcall printstr
.db "Invalid opcode @ PC=",0,0
rcall printhex
mov temp,z_pcl
rcall printhex
-\r
-;----------------------------------------------------------------\r
+
+;----------------------------------------------------------------
haltinv:
rjmp haltinv
projects / avrcpm.git / blobdiff