+instr fetch_nop, op_noni, store_nop ;FA ;
+instr fetch_nop, op_noni, store_nop ;FB ;
+instr fetch_nop, op_noni, store_nop ;FC ;
+instr fetch_nop, op_noni, store_nop ;FD ;
+instr fetch_nop, op_noni, store_nop ;FE ;
+instr fetch_nop, op_noni, store_nop ;FF ;
+
+
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|RLC m |**0P0*|Rotate Left Circular |m=m<- |
+;|RRC m |**0P0*|Rotate Right Circular|m=->m |
+;|RL m |**0P0*|Rotate Left |m={CY,m}<- |
+;|RR m |**0P0*|Rotate Right |m=->{CY,m} |
+;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |
+;|SRA m |**0P0*|Shift Right Arith. |m=m/2 |
+;|SLL m |**0P0*|Shift Right Logical |
+;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |
+
+
+ checkspace PC, 9
+
+do_op_rlc:
+ ;Rotate Left Cyclical. All bits move 1 to the
+ ;left, the msb becomes c and lsb.
+ clr temp
+ lsl opl
+ adc temp,_0
+ or opl,temp
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ or z_flags,temp
+ ret
+
+ checkspace PC, 9
+
+do_op_rrc:
+ ;Rotate Right Cyclical. All bits move 1 to the
+ ;right, the lsb becomes c and msb.
+ lsr opl
+ brcc PC+2
+ ori opl,0x80
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, opl,7
+ ret
+
+
+ checkspace PC, 11
+
+do_op_rl:
+ ;Rotate Left. All bits move 1 to the left, the msb
+ ;becomes c, c becomes lsb.
+ clc
+ sbrc z_flags,ZFL_C
+ sec
+ rol opl
+ in temp,sreg
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, temp,AVR_C
+ ret
+
+
+ checkspace PC, 10
+
+do_op_rr:
+ ;Rotate Right. All bits move 1 to the right, the lsb
+ ;becomes c, c becomes msb.
+
+ ror opl
+ in temp,sreg ;CY
+ bmov opl,7, z_flags,ZFL_C ;old CY --> Bit 7
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, temp,AVR_C ;
+ ret
+
+ checkspace PC, 9
+
+do_op_sla:
+ lsl opl
+ in temp,sreg
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, temp,AVR_C ;
+ ret
+
+ checkspace PC, 11
+
+do_op_sra:
+ lsr opl
+ in temp,sreg
+ bmov opl,7, opl,6 ;old CY --> Bit 7
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, temp,AVR_C ;
+ ret
+
+ checkspace PC, 9
+
+do_op_sll:
+ sec
+ rol opl
+ in temp,sreg
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, temp,AVR_C ;
+ ret
+
+ checkspace PC, 8
+
+do_op_srl:
+ lsr opl
+ in temp,sreg
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ bmov z_flags,ZFL_C, temp,AVR_C ;
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|BIT b,m |?*1?0-|Test Bit |m&{2^b} |
+;|RES b,m |------|Reset bit |m=m&{~2^b} |
+;|SET b,m |------|Set bit |m=mv{2^b} |
+
+
+ checkspace PC, 2
+do_op_BIT7:
+ ldi temp,0x80
+ rjmp opbit
+ checkspace PC, 2
+do_op_BIT6:
+ ldi temp,0x40
+ rjmp opbit
+ checkspace PC, 2
+do_op_BIT5:
+ ldi temp,0x20
+ rjmp opbit
+ checkspace PC, 2
+do_op_BIT4:
+ ldi temp,0x10
+ rjmp opbit
+ checkspace PC, 2
+do_op_BIT3:
+ ldi temp,0x08
+ rjmp opbit
+ checkspace PC, 2
+do_op_BIT2:
+ ldi temp,0x04
+ rjmp opbit
+ checkspace PC, 2
+do_op_BIT1:
+ ldi temp,0x02
+ rjmp opbit
+
+ checkspace PC, 7
+do_op_BIT0:
+ ldi temp,0x01
+opbit:
+ andi z_flags,~((1<<ZFL_N)|(1<<ZFL_Z))
+ ori z_flags,(1<<ZFL_H)
+ and temp,opl
+ brne opbite
+ ori z_flags,(1<<ZFL_Z)
+opbite:
+ ret
+
+
+.macro m_do_op_RES7
+ andi opl,~0x80
+.endm
+.equ do_op_RES7 = 0
+; andi opl,~0x80
+; ret
+
+.macro m_do_op_RES6
+ andi opl,~0x40
+.endm
+.equ do_op_RES6 = 0
+; andi opl,~0x40
+; ret
+
+.macro m_do_op_RES5
+ andi opl,~0x20
+.endm
+.equ do_op_RES5 = 0
+; andi opl,~0x20
+; ret
+
+.macro m_do_op_RES4
+ andi opl,~0x10
+.endm
+.equ do_op_RES4 = 0
+; andi opl,~0x10
+; ret
+
+.macro m_do_op_RES3
+ andi opl,~0x08
+.endm
+.equ do_op_RES3 = 0
+; andi opl,~0x08
+; ret
+
+.macro m_do_op_RES2
+ andi opl,~0x04
+.endm
+.equ do_op_RES2 = 0
+; andi opl,~0x04
+; ret
+
+.macro m_do_op_RES1
+ andi opl,~0x02
+.endm
+.equ do_op_RES1 = 0
+; andi opl,~0x02
+; ret
+
+.macro m_do_op_RES0
+ andi opl,~0x01
+.endm
+.equ do_op_RES0 = 0
+; andi opl,~0x01
+; ret
+
+.macro m_do_op_SET7
+ ori opl,0x80
+.endm
+.equ do_op_SET7 = 0
+; ori opl,0x80
+; ret
+
+.macro m_do_op_SET6
+ ori opl,0x40
+.endm
+.equ do_op_SET6 = 0
+; ori opl,0x40
+; ret
+
+.macro m_do_op_SET5
+ ori opl,0x20
+.endm
+.equ do_op_SET5 = 0
+; ori opl,0x20
+; ret
+
+.macro m_do_op_SET4
+ ori opl,0x10
+.endm
+.equ do_op_SET4 = 0
+; ori opl,0x10
+; ret
+
+.macro m_do_op_SET3
+ ori opl,0x08
+.endm
+.equ do_op_SET3 = 0
+; ori opl,0x08
+; ret
+
+.macro m_do_op_SET2
+ ori opl,0x04
+.endm
+.equ do_op_SET2 = 0
+; ori opl,0x04
+; ret
+
+.macro m_do_op_SET1
+ ori opl,0x02
+.endm
+.equ do_op_SET1 = 0
+; ori opl,0x02
+; ret
+
+.macro m_do_op_SET0
+ ori opl,0x01
+.endm
+.equ do_op_SET0 = 0
+; ori opl,0x01
+; ret
+
+
+;.macro m_do_store_b
+; std y+oz_b,opl
+;.endm
+;.equ do_store_b = 0
+ checkspace PC, 2
+do_store2_b:
+ mov z_b,opl
+ ret
+
+ checkspace PC, 2
+do_store2_c:
+ mov z_c,opl
+ ret
+
+ checkspace PC, 2
+do_store2_d:
+ mov z_d,opl
+ ret
+
+ checkspace PC, 2
+do_store2_e:
+ mov z_e,opl
+ ret
+
+ checkspace PC, 2
+do_store2_h:
+ mov z_h,opl
+ ret
+
+ checkspace PC, 2
+do_store2_l:
+ mov z_l,opl
+ ret
+
+ checkspace PC, 2
+do_store2_a:
+ mov z_a,opl
+ ret
+
+ checkspace PC, 4
+do_fetch2_mhl:
+; movw x,z_l
+ mem_read_ds opl, z_hl
+ ret
+
+ opctable CBjmp, PC ;+256
+
+instr fetch_B, op_RLC, store2_B ;00 ;RLC B
+instr fetch_C, op_RLC, store2_C ;01 ;RLC C
+instr fetch_D, op_RLC, store2_D ;02 ;RLC D
+instr fetch_E, op_RLC, store2_E ;03 ;RLC E
+instr fetch_H, op_RLC, store2_H ;04 ;RLC H
+instr fetch_L, op_RLC, store2_L ;05 ;RLC L
+instr fetch2_mhl, op_RLC, store_MHL ;06 ;RLC (HL)
+instr fetch_A, op_RLC, store2_A ;07 ;RLC A
+instr fetch_B, op_RRC, store2_B ;08 ;RRC B
+instr fetch_C, op_RRC, store2_C ;09 ;RRC C
+instr fetch_D, op_RRC, store2_D ;0A ;RRC D
+instr fetch_E, op_RRC, store2_E ;0B ;RRC E
+instr fetch_H, op_RRC, store2_H ;0C ;RRC H
+instr fetch_L, op_RRC, store2_L ;0D ;RRC L
+instr fetch2_mhl, op_RRC, store_MHL ;0E ;RRC (HL)
+instr fetch_A, op_RRC, store2_A ;0F ;RRC A
+instr fetch_B, op_RL, store2_B ;10 ;RL B
+instr fetch_C, op_RL, store2_C ;11 ;RL C
+instr fetch_D, op_RL, store2_D ;12 ;RL D
+instr fetch_E, op_RL, store2_E ;13 ;RL E
+instr fetch_H, op_RL, store2_H ;14 ;RL H
+instr fetch_L, op_RL, store2_L ;15 ;RL L
+instr fetch2_mhl, op_RL, store_MHL ;16 ;RL (HL)
+instr fetch_A, op_RL, store2_A ;17 ;RL A
+instr fetch_B, op_RR, store2_B ;18 ;RR B
+instr fetch_C, op_RR, store2_C ;19 ;RR C
+instr fetch_D, op_RR, store2_D ;1A ;RR D
+instr fetch_E, op_RR, store2_E ;1B ;RR E
+instr fetch_H, op_RR, store2_H ;1C ;RR H
+instr fetch_L, op_RR, store2_L ;1D ;RR L
+instr fetch2_mhl, op_RR, store_MHL ;1E ;RR (HL)
+instr fetch_A, op_RR, store2_A ;1F ;RR A
+instr fetch_B, op_SLA, store2_B ;20 ;SLA B
+instr fetch_C, op_SLA, store2_C ;21 ;SLA C
+instr fetch_D, op_SLA, store2_D ;22 ;SLA D
+instr fetch_E, op_SLA, store2_E ;23 ;SLA E
+instr fetch_H, op_SLA, store2_H ;24 ;SLA H
+instr fetch_L, op_SLA, store2_L ;25 ;SLA L
+instr fetch2_mhl, op_SLA, store_MHL ;26 ;SLA (HL)
+instr fetch_A, op_SLA, store2_A ;27 ;SLA A
+instr fetch_B, op_SRA, store2_B ;28 ;SRA B
+instr fetch_C, op_SRA, store2_C ;29 ;SRA C
+instr fetch_D, op_SRA, store2_D ;2A ;SRA D
+instr fetch_E, op_SRA, store2_E ;2B ;SRA E
+instr fetch_H, op_SRA, store2_H ;2C ;SRA H
+instr fetch_L, op_SRA, store2_L ;2D ;SRA L
+instr fetch2_mhl, op_SRA, store_MHL ;2E ;SRA (HL)
+instr fetch_A, op_SRA, store2_A ;2F ;SRA A
+instr fetch_B, op_SLL, store2_B ;30 ;SLL B
+instr fetch_C, op_SLL, store2_C ;31 ;SLL C
+instr fetch_D, op_SLL, store2_D ;32 ;SLL D
+instr fetch_E, op_SLL, store2_E ;33 ;SLL E
+instr fetch_H, op_SLL, store2_H ;34 ;SLL H
+instr fetch_L, op_SLL, store2_L ;35 ;SLL L
+instr fetch2_mhl, op_SLL, store_MHL ;36 ;SLL (HL)
+instr fetch_A, op_SLL, store2_A ;37 ;SLL A
+instr fetch_B, op_SRL, store2_B ;38 ;SRL B
+instr fetch_C, op_SRL, store2_C ;39 ;SRL C
+instr fetch_D, op_SRL, store2_D ;3A ;SRL D
+instr fetch_E, op_SRL, store2_E ;3B ;SRL E
+instr fetch_H, op_SRL, store2_H ;3C ;SRL H
+instr fetch_L, op_SRL, store2_L ;3D ;SRL L
+instr fetch2_mhl, op_SRL, store_MHL ;3E ;SRL (HL)
+instr fetch_A, op_SRL, store2_A ;3F ;SRL A
+instr fetch_B, op_BIT0, store_nop ;40 ;BIT 0,B
+instr fetch_C, op_BIT0, store_nop ;41 ;BIT 0,C
+instr fetch_D, op_BIT0, store_nop ;42 ;BIT 0,D
+instr fetch_E, op_BIT0, store_nop ;43 ;BIT 0,E
+instr fetch_H, op_BIT0, store_nop ;44 ;BIT 0,H
+instr fetch_L, op_BIT0, store_nop ;45 ;BIT 0,L
+instr fetch2_mhl, op_BIT0, store_nop ;46 ;BIT 0,(HL)
+instr fetch_A, op_BIT0, store_nop ;47 ;BIT 0,A
+instr fetch_B, op_BIT1, store_nop ;48 ;BIT 1,B
+instr fetch_C, op_BIT1, store_nop ;49 ;BIT 1,C
+instr fetch_D, op_BIT1, store_nop ;4A ;BIT 1,D
+instr fetch_E, op_BIT1, store_nop ;4B ;BIT 1,E
+instr fetch_H, op_BIT1, store_nop ;4C ;BIT 1,H
+instr fetch_L, op_BIT1, store_nop ;4D ;BIT 1,L
+instr fetch2_mhl, op_BIT1, store_nop ;4E ;BIT 1,(HL)
+instr fetch_A, op_BIT1, store_nop ;4F ;BIT 1,A
+instr fetch_B, op_BIT2, store_nop ;50 ;BIT 2,B
+instr fetch_C, op_BIT2, store_nop ;51 ;BIT 2,C
+instr fetch_D, op_BIT2, store_nop ;52 ;BIT 2,D
+instr fetch_E, op_BIT2, store_nop ;53 ;BIT 2,E
+instr fetch_H, op_BIT2, store_nop ;54 ;BIT 2,H
+instr fetch_L, op_BIT2, store_nop ;55 ;BIT 2,L
+instr fetch2_mhl, op_BIT2, store_nop ;56 ;BIT 2,(HL)
+instr fetch_A, op_BIT2, store_nop ;57 ;BIT 2,A
+instr fetch_B, op_BIT3, store_nop ;58 ;BIT 3,B
+instr fetch_C, op_BIT3, store_nop ;59 ;BIT 3,C
+instr fetch_D, op_BIT3, store_nop ;5A ;BIT 3,D
+instr fetch_E, op_BIT3, store_nop ;5B ;BIT 3,E
+instr fetch_H, op_BIT3, store_nop ;5C ;BIT 3,H
+instr fetch_L, op_BIT3, store_nop ;5D ;BIT 3,L
+instr fetch2_mhl, op_BIT3, store_nop ;5E ;BIT 3,(HL)
+instr fetch_A, op_BIT3, store_nop ;5F ;BIT 3,A
+instr fetch_B, op_BIT4, store_nop ;60 ;BIT 4,B
+instr fetch_C, op_BIT4, store_nop ;61 ;BIT 4,C
+instr fetch_D, op_BIT4, store_nop ;62 ;BIT 4,D
+instr fetch_E, op_BIT4, store_nop ;63 ;BIT 4,E
+instr fetch_H, op_BIT4, store_nop ;64 ;BIT 4,H
+instr fetch_L, op_BIT4, store_nop ;65 ;BIT 4,L
+instr fetch2_mhl, op_BIT4, store_nop ;66 ;BIT 4,(HL)
+instr fetch_A, op_BIT4, store_nop ;67 ;BIT 4,A
+instr fetch_B, op_BIT5, store_nop ;68 ;BIT 5,B
+instr fetch_C, op_BIT5, store_nop ;69 ;BIT 5,C
+instr fetch_D, op_BIT5, store_nop ;6A ;BIT 5,D
+instr fetch_E, op_BIT5, store_nop ;6B ;BIT 5,E
+instr fetch_H, op_BIT5, store_nop ;6C ;BIT 5,H
+instr fetch_L, op_BIT5, store_nop ;6D ;BIT 5,L
+instr fetch2_mhl, op_BIT5, store_nop ;6E ;BIT 5,(HL)
+instr fetch_A, op_BIT5, store_nop ;6F ;BIT 5,A
+instr fetch_B, op_BIT6, store_nop ;70 ;BIT 6,B
+instr fetch_C, op_BIT6, store_nop ;71 ;BIT 6,C
+instr fetch_D, op_BIT6, store_nop ;72 ;BIT 6,D
+instr fetch_E, op_BIT6, store_nop ;73 ;BIT 6,E
+instr fetch_H, op_BIT6, store_nop ;74 ;BIT 6,H
+instr fetch_L, op_BIT6, store_nop ;75 ;BIT 6,L
+instr fetch2_mhl, op_BIT6, store_nop ;76 ;BIT 6,(HL)
+instr fetch_A, op_BIT6, store_nop ;77 ;BIT 6,A
+instr fetch_B, op_BIT7, store_nop ;78 ;BIT 7,B
+instr fetch_C, op_BIT7, store_nop ;79 ;BIT 7,C
+instr fetch_D, op_BIT7, store_nop ;7A ;BIT 7,D
+instr fetch_E, op_BIT7, store_nop ;7B ;BIT 7,E
+instr fetch_H, op_BIT7, store_nop ;7C ;BIT 7,H
+instr fetch_L, op_BIT7, store_nop ;7D ;BIT 7,L
+instr fetch2_mhl, op_BIT7, store_nop ;7E ;BIT 7,(HL)
+instr fetch_A, op_BIT7, store_nop ;7F ;BIT 7,A
+instr fetch_B, op_RES0, store2_B ;80 ;RES 0,B
+instr fetch_C, op_RES0, store2_C ;81 ;RES 0,C
+instr fetch_D, op_RES0, store2_D ;82 ;RES 0,D
+instr fetch_E, op_RES0, store2_E ;83 ;RES 0,E
+instr fetch_H, op_RES0, store2_H ;84 ;RES 0,H
+instr fetch_L, op_RES0, store2_L ;85 ;RES 0,L
+instr fetch2_mhl, op_RES0, store_MHL ;86 ;RES 0,(HL)
+instr fetch_A, op_RES0, store2_A ;87 ;RES 0,A
+instr fetch_B, op_RES1, store2_B ;88 ;RES 1,B
+instr fetch_C, op_RES1, store2_C ;89 ;RES 1,C
+instr fetch_D, op_RES1, store2_D ;8A ;RES 1,D
+instr fetch_E, op_RES1, store2_E ;8B ;RES 1,E
+instr fetch_H, op_RES1, store2_H ;8C ;RES 1,H
+instr fetch_L, op_RES1, store2_L ;8D ;RES 1,L
+instr fetch2_mhl, op_RES1, store_MHL ;8E ;RES 1,(HL)
+instr fetch_A, op_RES1, store2_A ;8F ;RES 1,A
+instr fetch_B, op_RES2, store2_B ;90 ;RES 2,B
+instr fetch_C, op_RES2, store2_C ;91 ;RES 2,C
+instr fetch_D, op_RES2, store2_D ;92 ;RES 2,D
+instr fetch_E, op_RES2, store2_E ;93 ;RES 2,E
+instr fetch_H, op_RES2, store2_H ;94 ;RES 2,H
+instr fetch_L, op_RES2, store2_L ;95 ;RES 2,L
+instr fetch2_mhl, op_RES2, store_MHL ;96 ;RES 2,(HL)
+instr fetch_A, op_RES2, store2_A ;97 ;RES 2,A
+instr fetch_B, op_RES3, store2_B ;98 ;RES 3,B
+instr fetch_C, op_RES3, store2_C ;99 ;RES 3,C
+instr fetch_D, op_RES3, store2_D ;9A ;RES 3,D
+instr fetch_E, op_RES3, store2_E ;9B ;RES 3,E
+instr fetch_H, op_RES3, store2_H ;9C ;RES 3,H
+instr fetch_L, op_RES3, store2_L ;9D ;RES 3,L
+instr fetch2_mhl, op_RES3, store_MHL ;9E ;RES 3,(HL)
+instr fetch_A, op_RES3, store2_A ;9F ;RES 3,A
+instr fetch_B, op_RES4, store2_B ;A0 ;RES 4,B
+instr fetch_C, op_RES4, store2_C ;A1 ;RES 4,C
+instr fetch_D, op_RES4, store2_D ;A2 ;RES 4,D
+instr fetch_E, op_RES4, store2_E ;A3 ;RES 4,E
+instr fetch_H, op_RES4, store2_H ;A4 ;RES 4,H
+instr fetch_L, op_RES4, store2_L ;A5 ;RES 4,L
+instr fetch2_mhl, op_RES4, store_MHL ;A6 ;RES 4,(HL)
+instr fetch_A, op_RES4, store2_A ;A7 ;RES 4,A
+instr fetch_B, op_RES5, store2_B ;A8 ;RES 5,B
+instr fetch_C, op_RES5, store2_C ;A9 ;RES 5,C
+instr fetch_D, op_RES5, store2_D ;AA ;RES 5,D
+instr fetch_E, op_RES5, store2_E ;AB ;RES 5,E
+instr fetch_H, op_RES5, store2_H ;AC ;RES 5,H
+instr fetch_L, op_RES5, store2_L ;AD ;RES 5,L
+instr fetch2_mhl, op_RES5, store_MHL ;AE ;RES 5,(HL)
+instr fetch_A, op_RES5, store2_A ;AF ;RES 5,A
+instr fetch_B, op_RES6, store2_B ;B0 ;RES 6,B
+instr fetch_C, op_RES6, store2_C ;B1 ;RES 6,C
+instr fetch_D, op_RES6, store2_D ;B2 ;RES 6,D
+instr fetch_E, op_RES6, store2_E ;B3 ;RES 6,E
+instr fetch_H, op_RES6, store2_H ;B4 ;RES 6,H
+instr fetch_L, op_RES6, store2_L ;B5 ;RES 6,L
+instr fetch2_mhl, op_RES6, store_MHL ;B6 ;RES 6,(HL)
+instr fetch_A, op_RES6, store2_A ;B7 ;RES 6,A
+instr fetch_B, op_RES7, store2_B ;B8 ;RES 7,B
+instr fetch_C, op_RES7, store2_C ;B9 ;RES 7,C
+instr fetch_D, op_RES7, store2_D ;BA ;RES 7,D
+instr fetch_E, op_RES7, store2_E ;BB ;RES 7,E
+instr fetch_H, op_RES7, store2_H ;BC ;RES 7,H
+instr fetch_L, op_RES7, store2_L ;BD ;RES 7,L
+instr fetch2_mhl, op_RES7, store_MHL ;BE ;RES 7,(HL)
+instr fetch_A, op_RES7, store2_A ;BF ;RES 7,A
+instr fetch_B, op_SET0, store2_B ;C0 ;SET 0,B
+instr fetch_C, op_SET0, store2_C ;C1 ;SET 0,C
+instr fetch_D, op_SET0, store2_D ;C2 ;SET 0,D
+instr fetch_E, op_SET0, store2_E ;C3 ;SET 0,E
+instr fetch_H, op_SET0, store2_H ;C4 ;SET 0,H
+instr fetch_L, op_SET0, store2_L ;C5 ;SET 0,L
+instr fetch2_mhl, op_SET0, store_MHL ;C6 ;SET 0,(HL)
+instr fetch_A, op_SET0, store2_A ;C7 ;SET 0,A
+instr fetch_B, op_SET1, store2_B ;C8 ;SET 1,B
+instr fetch_C, op_SET1, store2_C ;C9 ;SET 1,C
+instr fetch_D, op_SET1, store2_D ;CA ;SET 1,D
+instr fetch_E, op_SET1, store2_E ;CB ;SET 1,E
+instr fetch_H, op_SET1, store2_H ;CC ;SET 1,H
+instr fetch_L, op_SET1, store2_L ;CD ;SET 1,L
+instr fetch2_mhl, op_SET1, store_MHL ;CE ;SET 1,(HL)
+instr fetch_A, op_SET1, store2_A ;CF ;SET 1,A
+instr fetch_B, op_SET2, store2_B ;D0 ;SET 2,B
+instr fetch_C, op_SET2, store2_C ;D1 ;SET 2,C
+instr fetch_D, op_SET2, store2_D ;D2 ;SET 2,D
+instr fetch_E, op_SET2, store2_E ;D3 ;SET 2,E
+instr fetch_H, op_SET2, store2_H ;D4 ;SET 2,H
+instr fetch_L, op_SET2, store2_L ;D5 ;SET 2,L
+instr fetch2_mhl, op_SET2, store_MHL ;D6 ;SET 2,(HL)
+instr fetch_A, op_SET2, store2_A ;D7 ;SET 2,A
+instr fetch_B, op_SET3, store2_B ;D8 ;SET 3,B
+instr fetch_C, op_SET3, store2_C ;D9 ;SET 3,C
+instr fetch_D, op_SET3, store2_D ;DA ;SET 3,D
+instr fetch_E, op_SET3, store2_E ;DB ;SET 3,E
+instr fetch_H, op_SET3, store2_H ;DC ;SET 3,H
+instr fetch_L, op_SET3, store2_L ;DD ;SET 3,L
+instr fetch2_mhl, op_SET3, store_MHL ;DE ;SET 3,(HL)
+instr fetch_A, op_SET3, store2_A ;DF ;SET 3,A
+instr fetch_B, op_SET4, store2_B ;E0 ;SET 4,B
+instr fetch_C, op_SET4, store2_C ;E1 ;SET 4,C
+instr fetch_D, op_SET4, store2_D ;E2 ;SET 4,D
+instr fetch_E, op_SET4, store2_E ;E3 ;SET 4,E
+instr fetch_H, op_SET4, store2_H ;E4 ;SET 4,H
+instr fetch_L, op_SET4, store2_L ;E5 ;SET 4,L
+instr fetch2_mhl, op_SET4, store_MHL ;E6 ;SET 4,(HL)
+instr fetch_A, op_SET4, store2_A ;E7 ;SET 4,A
+instr fetch_B, op_SET5, store2_B ;E8 ;SET 5,B
+instr fetch_C, op_SET5, store2_C ;E9 ;SET 5,C
+instr fetch_D, op_SET5, store2_D ;EA ;SET 5,D
+instr fetch_E, op_SET5, store2_E ;EB ;SET 5,E
+instr fetch_H, op_SET5, store2_H ;EC ;SET 5,H
+instr fetch_L, op_SET5, store2_L ;ED ;SET 5,L
+instr fetch2_mhl, op_SET5, store_MHL ;EE ;SET 5,(HL)
+instr fetch_A, op_SET5, store2_A ;EF ;SET 5,A
+instr fetch_B, op_SET6, store2_B ;F0 ;SET 6,B
+instr fetch_C, op_SET6, store2_C ;F1 ;SET 6,C
+instr fetch_D, op_SET6, store2_D ;F2 ;SET 6,D
+instr fetch_E, op_SET6, store2_E ;F3 ;SET 6,E
+instr fetch_H, op_SET6, store2_H ;F4 ;SET 6,H
+instr fetch_L, op_SET6, store2_L ;F5 ;SET 6,L
+instr fetch2_mhl, op_SET6, store_MHL ;F6 ;SET 6,(HL)
+instr fetch_A, op_SET6, store2_A ;F7 ;SET 6,A
+instr fetch_B, op_SET7, store2_B ;F8 ;SET 7,B
+instr fetch_C, op_SET7, store2_C ;F9 ;SET 7,C
+instr fetch_D, op_SET7, store2_D ;FA ;SET 7,D
+instr fetch_E, op_SET7, store2_E ;FB ;SET 7,E
+instr fetch_H, op_SET7, store2_H ;FC ;SET 7,H
+instr fetch_L, op_SET7, store2_L ;FD ;SET 7,L
+instr fetch2_mhl, op_SET7, store_MHL ;FE ;SET 7,(HL)
+instr fetch_A, op_SET7, store2_A ;FF ;SET 7,A
+
+
+ opctable DDFDCBjmp, PC ;+256
+
+instr fetch_nop, op_RLC, store2_B ;00 ;RLC (Ix+d),B
+instr fetch_nop, op_RLC, store2_C ;01 ;RLC (Ix+d),C
+instr fetch_nop, op_RLC, store2_D ;02 ;RLC (Ix+d),D
+instr fetch_nop, op_RLC, store2_E ;03 ;RLC (Ix+d),E
+instr fetch_nop, op_RLC, store2_H ;04 ;RLC (Ix+d),H
+instr fetch_nop, op_RLC, store2_L ;05 ;RLC (Ix+d),L
+instr fetch_nop, op_RLC, store_nop ;06 ;RLC (Ix+d)
+instr fetch_nop, op_RLC, store2_A ;07 ;RLC (Ix+d),A
+instr fetch_nop, op_RRC, store2_B ;08 ;RRC (Ix+d),B
+instr fetch_nop, op_RRC, store2_C ;09 ;RRC (Ix+d),C
+instr fetch_nop, op_RRC, store2_D ;0A ;RRC (Ix+d),D
+instr fetch_nop, op_RRC, store2_E ;0B ;RRC (Ix+d),E
+instr fetch_nop, op_RRC, store2_H ;0C ;RRC (Ix+d),H
+instr fetch_nop, op_RRC, store2_L ;0D ;RRC (Ix+d),L
+instr fetch_nop, op_RRC, store_nop ;0E ;RRC (Ix+d)
+instr fetch_nop, op_RRC, store2_A ;0F ;RRC (Ix+d),A
+instr fetch_nop, op_RL, store2_B ;10 ;RL (Ix+d),B
+instr fetch_nop, op_RL, store2_C ;11 ;RL (Ix+d),C
+instr fetch_nop, op_RL, store2_D ;12 ;RL (Ix+d),D
+instr fetch_nop, op_RL, store2_E ;13 ;RL (Ix+d),E
+instr fetch_nop, op_RL, store2_H ;14 ;RL (Ix+d),H
+instr fetch_nop, op_RL, store2_L ;15 ;RL (Ix+d),L
+instr fetch_nop, op_RL, store_nop ;16 ;RL (Ix+d)
+instr fetch_nop, op_RL, store2_A ;17 ;RL (Ix+d),A
+instr fetch_nop, op_RR, store2_B ;18 ;RR (Ix+d),B
+instr fetch_nop, op_RR, store2_C ;19 ;RR (Ix+d),C
+instr fetch_nop, op_RR, store2_D ;1A ;RR (Ix+d),D
+instr fetch_nop, op_RR, store2_E ;1B ;RR (Ix+d),E
+instr fetch_nop, op_RR, store2_H ;1C ;RR (Ix+d),H
+instr fetch_nop, op_RR, store2_L ;1D ;RR (Ix+d),L
+instr fetch_nop, op_RR, store_nop ;1E ;RR (Ix+d)
+instr fetch_nop, op_RR, store2_A ;1F ;RR (Ix+d),A
+instr fetch_nop, op_SLA, store2_B ;20 ;SLA (Ix+d),B
+instr fetch_nop, op_SLA, store2_C ;21 ;SLA (Ix+d),C
+instr fetch_nop, op_SLA, store2_D ;22 ;SLA (Ix+d),D
+instr fetch_nop, op_SLA, store2_E ;23 ;SLA (Ix+d),E
+instr fetch_nop, op_SLA, store2_H ;24 ;SLA (Ix+d),H
+instr fetch_nop, op_SLA, store2_L ;25 ;SLA (Ix+d),L
+instr fetch_nop, op_SLA, store_nop ;26 ;SLA (Ix+d)
+instr fetch_nop, op_SLA, store2_A ;27 ;SLA (Ix+d),A
+instr fetch_nop, op_SRA, store2_B ;28 ;SRA (Ix+d),B
+instr fetch_nop, op_SRA, store2_C ;29 ;SRA (Ix+d),C
+instr fetch_nop, op_SRA, store2_D ;2A ;SRA (Ix+d),D
+instr fetch_nop, op_SRA, store2_E ;2B ;SRA (Ix+d),E
+instr fetch_nop, op_SRA, store2_H ;2C ;SRA (Ix+d),H
+instr fetch_nop, op_SRA, store2_L ;2D ;SRA (Ix+d),L
+instr fetch_nop, op_SRA, store_nop ;2E ;SRA (Ix+d)
+instr fetch_nop, op_SRA, store2_A ;2F ;SRA (Ix+d),A
+instr fetch_nop, op_SLL, store2_B ;30 ;SLL (Ix+d),B
+instr fetch_nop, op_SLL, store2_C ;31 ;SLL (Ix+d),C
+instr fetch_nop, op_SLL, store2_D ;32 ;SLL (Ix+d),D
+instr fetch_nop, op_SLL, store2_E ;33 ;SLL (Ix+d),E
+instr fetch_nop, op_SLL, store2_H ;34 ;SLL (Ix+d),H
+instr fetch_nop, op_SLL, store2_L ;35 ;SLL (Ix+d),L
+instr fetch_nop, op_SLL, store_nop ;36 ;SLL (Ix+d)
+instr fetch_nop, op_SLL, store2_A ;37 ;SLL (Ix+d),A
+instr fetch_nop, op_SRL, store2_B ;38 ;SRL (Ix+d),B
+instr fetch_nop, op_SRL, store2_C ;39 ;SRL (Ix+d),C
+instr fetch_nop, op_SRL, store2_D ;3A ;SRL (Ix+d),D
+instr fetch_nop, op_SRL, store2_E ;3B ;SRL (Ix+d),E
+instr fetch_nop, op_SRL, store2_H ;3C ;SRL (Ix+d),H
+instr fetch_nop, op_SRL, store2_L ;3D ;SRL (Ix+d),L
+instr fetch_nop, op_SRL, store_nop ;3E ;SRL (Ix+d)
+instr fetch_nop, op_SRL, store2_A ;3F ;SRL (Ix+d),A
+instr fetch_nop, op_BIT0, store_nop ;40 ;BIT 0,(Ix+d),B
+instr fetch_nop, op_BIT0, store_nop ;41 ;BIT 0,(Ix+d),C
+instr fetch_nop, op_BIT0, store_nop ;42 ;BIT 0,(Ix+d),D
+instr fetch_nop, op_BIT0, store_nop ;43 ;BIT 0,(Ix+d),E
+instr fetch_nop, op_BIT0, store_nop ;44 ;BIT 0,(Ix+d),H
+instr fetch_nop, op_BIT0, store_nop ;45 ;BIT 0,(Ix+d),L
+instr fetch_nop, op_BIT0, store_nop ;46 ;BIT 0,(Ix+d)
+instr fetch_nop, op_BIT0, store_nop ;47 ;BIT 0,(Ix+d),A
+instr fetch_nop, op_BIT1, store_nop ;48 ;BIT 1,(Ix+d),B
+instr fetch_nop, op_BIT1, store_nop ;49 ;BIT 1,(Ix+d),C
+instr fetch_nop, op_BIT1, store_nop ;4A ;BIT 1,(Ix+d),D
+instr fetch_nop, op_BIT1, store_nop ;4B ;BIT 1,(Ix+d),E
+instr fetch_nop, op_BIT1, store_nop ;4C ;BIT 1,(Ix+d),H
+instr fetch_nop, op_BIT1, store_nop ;4D ;BIT 1,(Ix+d),L
+instr fetch_nop, op_BIT1, store_nop ;4E ;BIT 1,(Ix+d)
+instr fetch_nop, op_BIT1, store_nop ;4F ;BIT 1,(Ix+d),A
+instr fetch_nop, op_BIT2, store_nop ;50 ;BIT 2,(Ix+d),B
+instr fetch_nop, op_BIT2, store_nop ;51 ;BIT 2,(Ix+d),C
+instr fetch_nop, op_BIT2, store_nop ;52 ;BIT 2,(Ix+d),D
+instr fetch_nop, op_BIT2, store_nop ;53 ;BIT 2,(Ix+d),E
+instr fetch_nop, op_BIT2, store_nop ;54 ;BIT 2,(Ix+d),H
+instr fetch_nop, op_BIT2, store_nop ;55 ;BIT 2,(Ix+d),L
+instr fetch_nop, op_BIT2, store_nop ;56 ;BIT 2,(Ix+d)
+instr fetch_nop, op_BIT2, store_nop ;57 ;BIT 2,(Ix+d),A
+instr fetch_nop, op_BIT3, store_nop ;58 ;BIT 3,(Ix+d),B
+instr fetch_nop, op_BIT3, store_nop ;59 ;BIT 3,(Ix+d),C
+instr fetch_nop, op_BIT3, store_nop ;5A ;BIT 3,(Ix+d),D
+instr fetch_nop, op_BIT3, store_nop ;5B ;BIT 3,(Ix+d),E
+instr fetch_nop, op_BIT3, store_nop ;5C ;BIT 3,(Ix+d),H
+instr fetch_nop, op_BIT3, store_nop ;5D ;BIT 3,(Ix+d),L
+instr fetch_nop, op_BIT3, store_nop ;5E ;BIT 3,(Ix+d)
+instr fetch_nop, op_BIT3, store_nop ;5F ;BIT 3,(Ix+d),A
+instr fetch_nop, op_BIT4, store_nop ;60 ;BIT 4,(Ix+d),B
+instr fetch_nop, op_BIT4, store_nop ;61 ;BIT 4,(Ix+d),C
+instr fetch_nop, op_BIT4, store_nop ;62 ;BIT 4,(Ix+d),D
+instr fetch_nop, op_BIT4, store_nop ;63 ;BIT 4,(Ix+d),E
+instr fetch_nop, op_BIT4, store_nop ;64 ;BIT 4,(Ix+d),H
+instr fetch_nop, op_BIT4, store_nop ;65 ;BIT 4,(Ix+d),L
+instr fetch_nop, op_BIT4, store_nop ;66 ;BIT 4,(Ix+d)
+instr fetch_nop, op_BIT4, store_nop ;67 ;BIT 4,(Ix+d),A
+instr fetch_nop, op_BIT5, store_nop ;68 ;BIT 5,(Ix+d),B
+instr fetch_nop, op_BIT5, store_nop ;69 ;BIT 5,(Ix+d),C
+instr fetch_nop, op_BIT5, store_nop ;6A ;BIT 5,(Ix+d),D
+instr fetch_nop, op_BIT5, store_nop ;6B ;BIT 5,(Ix+d),E
+instr fetch_nop, op_BIT5, store_nop ;6C ;BIT 5,(Ix+d),H
+instr fetch_nop, op_BIT5, store_nop ;6D ;BIT 5,(Ix+d),L
+instr fetch_nop, op_BIT5, store_nop ;6E ;BIT 5,(Ix+d)
+instr fetch_nop, op_BIT5, store_nop ;6F ;BIT 5,(Ix+d),A
+instr fetch_nop, op_BIT6, store_nop ;70 ;BIT 6,(Ix+d),B
+instr fetch_nop, op_BIT6, store_nop ;71 ;BIT 6,(Ix+d),C
+instr fetch_nop, op_BIT6, store_nop ;72 ;BIT 6,(Ix+d),D
+instr fetch_nop, op_BIT6, store_nop ;73 ;BIT 6,(Ix+d),E
+instr fetch_nop, op_BIT6, store_nop ;74 ;BIT 6,(Ix+d),H
+instr fetch_nop, op_BIT6, store_nop ;75 ;BIT 6,(Ix+d),L
+instr fetch_nop, op_BIT6, store_nop ;76 ;BIT 6,(Ix+d)
+instr fetch_nop, op_BIT6, store_nop ;77 ;BIT 6,(Ix+d),A
+instr fetch_nop, op_BIT7, store_nop ;78 ;BIT 7,(Ix+d),B
+instr fetch_nop, op_BIT7, store_nop ;79 ;BIT 7,(Ix+d),C
+instr fetch_nop, op_BIT7, store_nop ;7A ;BIT 7,(Ix+d),D
+instr fetch_nop, op_BIT7, store_nop ;7B ;BIT 7,(Ix+d),E
+instr fetch_nop, op_BIT7, store_nop ;7C ;BIT 7,(Ix+d),H
+instr fetch_nop, op_BIT7, store_nop ;7D ;BIT 7,(Ix+d),L
+instr fetch_nop, op_BIT7, store_nop ;7E ;BIT 7,(Ix+d)
+instr fetch_nop, op_BIT7, store_nop ;7F ;BIT 7,(Ix+d),A
+instr fetch_nop, op_RES0, store2_B ;80 ;RES 0,(Ix+d),B
+instr fetch_nop, op_RES0, store2_C ;81 ;RES 0,(Ix+d),C
+instr fetch_nop, op_RES0, store2_D ;82 ;RES 0,(Ix+d),D
+instr fetch_nop, op_RES0, store2_E ;83 ;RES 0,(Ix+d),E
+instr fetch_nop, op_RES0, store2_H ;84 ;RES 0,(Ix+d),H
+instr fetch_nop, op_RES0, store2_L ;85 ;RES 0,(Ix+d),L
+instr fetch_nop, op_RES0, store_nop ;86 ;RES 0,(Ix+d)
+instr fetch_nop, op_RES0, store2_A ;87 ;RES 0,(Ix+d),A
+instr fetch_nop, op_RES1, store2_B ;88 ;RES 1,(Ix+d),B
+instr fetch_nop, op_RES1, store2_C ;89 ;RES 1,(Ix+d),C
+instr fetch_nop, op_RES1, store2_D ;8A ;RES 1,(Ix+d),D
+instr fetch_nop, op_RES1, store2_E ;8B ;RES 1,(Ix+d),E
+instr fetch_nop, op_RES1, store2_H ;8C ;RES 1,(Ix+d),H
+instr fetch_nop, op_RES1, store2_L ;8D ;RES 1,(Ix+d),L
+instr fetch_nop, op_RES1, store_nop ;8E ;RES 1,(Ix+d)
+instr fetch_nop, op_RES1, store2_A ;8F ;RES 1,(Ix+d),A
+instr fetch_nop, op_RES2, store2_B ;90 ;RES 2,(Ix+d),B
+instr fetch_nop, op_RES2, store2_C ;91 ;RES 2,(Ix+d),C
+instr fetch_nop, op_RES2, store2_D ;92 ;RES 2,(Ix+d),D
+instr fetch_nop, op_RES2, store2_E ;93 ;RES 2,(Ix+d),E
+instr fetch_nop, op_RES2, store2_H ;94 ;RES 2,(Ix+d),H
+instr fetch_nop, op_RES2, store2_L ;95 ;RES 2,(Ix+d),L
+instr fetch_nop, op_RES2, store_nop ;96 ;RES 2,(Ix+d)
+instr fetch_nop, op_RES2, store2_A ;97 ;RES 2,(Ix+d),A
+instr fetch_nop, op_RES3, store2_B ;98 ;RES 3,(Ix+d),B
+instr fetch_nop, op_RES3, store2_C ;99 ;RES 3,(Ix+d),C
+instr fetch_nop, op_RES3, store2_D ;9A ;RES 3,(Ix+d),D
+instr fetch_nop, op_RES3, store2_E ;9B ;RES 3,(Ix+d),E
+instr fetch_nop, op_RES3, store2_H ;9C ;RES 3,(Ix+d),H
+instr fetch_nop, op_RES3, store2_L ;9D ;RES 3,(Ix+d),L
+instr fetch_nop, op_RES3, store_nop ;9E ;RES 3,(Ix+d)
+instr fetch_nop, op_RES3, store2_A ;9F ;RES 3,(Ix+d),A
+instr fetch_nop, op_RES4, store2_B ;A0 ;RES 4,(Ix+d),B
+instr fetch_nop, op_RES4, store2_C ;A1 ;RES 4,(Ix+d),C
+instr fetch_nop, op_RES4, store2_D ;A2 ;RES 4,(Ix+d),D
+instr fetch_nop, op_RES4, store2_E ;A3 ;RES 4,(Ix+d),E
+instr fetch_nop, op_RES4, store2_H ;A4 ;RES 4,(Ix+d),H
+instr fetch_nop, op_RES4, store2_L ;A5 ;RES 4,(Ix+d),L
+instr fetch_nop, op_RES4, store_nop ;A6 ;RES 4,(Ix+d)
+instr fetch_nop, op_RES4, store2_A ;A7 ;RES 4,(Ix+d),A
+instr fetch_nop, op_RES5, store2_B ;A8 ;RES 5,(Ix+d),B
+instr fetch_nop, op_RES5, store2_C ;A9 ;RES 5,(Ix+d),C
+instr fetch_nop, op_RES5, store2_D ;AA ;RES 5,(Ix+d),D
+instr fetch_nop, op_RES5, store2_E ;AB ;RES 5,(Ix+d),E
+instr fetch_nop, op_RES5, store2_H ;AC ;RES 5,(Ix+d),H
+instr fetch_nop, op_RES5, store2_L ;AD ;RES 5,(Ix+d),L
+instr fetch_nop, op_RES5, store_nop ;AE ;RES 5,(Ix+d)
+instr fetch_nop, op_RES5, store2_A ;AF ;RES 5,(Ix+d),A
+instr fetch_nop, op_RES6, store2_B ;B0 ;RES 6,(Ix+d),B
+instr fetch_nop, op_RES6, store2_C ;B1 ;RES 6,(Ix+d),C
+instr fetch_nop, op_RES6, store2_D ;B2 ;RES 6,(Ix+d),D
+instr fetch_nop, op_RES6, store2_E ;B3 ;RES 6,(Ix+d),E
+instr fetch_nop, op_RES6, store2_H ;B4 ;RES 6,(Ix+d),H
+instr fetch_nop, op_RES6, store2_L ;B5 ;RES 6,(Ix+d),L
+instr fetch_nop, op_RES6, store_nop ;B6 ;RES 6,(Ix+d)
+instr fetch_nop, op_RES6, store2_A ;B7 ;RES 6,(Ix+d),A
+instr fetch_nop, op_RES7, store2_B ;B8 ;RES 7,(Ix+d),B
+instr fetch_nop, op_RES7, store2_C ;B9 ;RES 7,(Ix+d),C
+instr fetch_nop, op_RES7, store2_D ;BA ;RES 7,(Ix+d),D
+instr fetch_nop, op_RES7, store2_E ;BB ;RES 7,(Ix+d),E
+instr fetch_nop, op_RES7, store2_H ;BC ;RES 7,(Ix+d),H
+instr fetch_nop, op_RES7, store2_L ;BD ;RES 7,(Ix+d),L
+instr fetch_nop, op_RES7, store_nop ;BE ;RES 7,(Ix+d)
+instr fetch_nop, op_RES7, store2_A ;BF ;RES 7,(Ix+d),A
+instr fetch_nop, op_SET0, store2_B ;C0 ;SET 0,(Ix+d),B
+instr fetch_nop, op_SET0, store2_C ;C1 ;SET 0,(Ix+d),C
+instr fetch_nop, op_SET0, store2_D ;C2 ;SET 0,(Ix+d),D
+instr fetch_nop, op_SET0, store2_E ;C3 ;SET 0,(Ix+d),E
+instr fetch_nop, op_SET0, store2_H ;C4 ;SET 0,(Ix+d),H
+instr fetch_nop, op_SET0, store2_L ;C5 ;SET 0,(Ix+d),L
+instr fetch_nop, op_SET0, store_nop ;C6 ;SET 0,(Ix+d)
+instr fetch_nop, op_SET0, store2_A ;C7 ;SET 0,(Ix+d),A
+instr fetch_nop, op_SET1, store2_B ;C8 ;SET 1,(Ix+d),B
+instr fetch_nop, op_SET1, store2_C ;C9 ;SET 1,(Ix+d),C
+instr fetch_nop, op_SET1, store2_D ;CA ;SET 1,(Ix+d),D
+instr fetch_nop, op_SET1, store2_E ;CB ;SET 1,(Ix+d),E
+instr fetch_nop, op_SET1, store2_H ;CC ;SET 1,(Ix+d),H
+instr fetch_nop, op_SET1, store2_L ;CD ;SET 1,(Ix+d),L
+instr fetch_nop, op_SET1, store_nop ;CE ;SET 1,(Ix+d)
+instr fetch_nop, op_SET1, store2_A ;CF ;SET 1,(Ix+d),A
+instr fetch_nop, op_SET2, store2_B ;D0 ;SET 2,(Ix+d),B
+instr fetch_nop, op_SET2, store2_C ;D1 ;SET 2,(Ix+d),C
+instr fetch_nop, op_SET2, store2_D ;D2 ;SET 2,(Ix+d),D
+instr fetch_nop, op_SET2, store2_E ;D3 ;SET 2,(Ix+d),E
+instr fetch_nop, op_SET2, store2_H ;D4 ;SET 2,(Ix+d),H
+instr fetch_nop, op_SET2, store2_L ;D5 ;SET 2,(Ix+d),L
+instr fetch_nop, op_SET2, store_nop ;D6 ;SET 2,(Ix+d)
+instr fetch_nop, op_SET2, store2_A ;D7 ;SET 2,(Ix+d),A
+instr fetch_nop, op_SET3, store2_B ;D8 ;SET 3,(Ix+d),B
+instr fetch_nop, op_SET3, store2_C ;D9 ;SET 3,(Ix+d),C
+instr fetch_nop, op_SET3, store2_D ;DA ;SET 3,(Ix+d),D
+instr fetch_nop, op_SET3, store2_E ;DB ;SET 3,(Ix+d),E
+instr fetch_nop, op_SET3, store2_H ;DC ;SET 3,(Ix+d),H
+instr fetch_nop, op_SET3, store2_L ;DD ;SET 3,(Ix+d),L
+instr fetch_nop, op_SET3, store_nop ;DE ;SET 3,(Ix+d)
+instr fetch_nop, op_SET3, store2_A ;DF ;SET 3,(Ix+d),A
+instr fetch_nop, op_SET4, store2_B ;E0 ;SET 4,(Ix+d),B
+instr fetch_nop, op_SET4, store2_C ;E1 ;SET 4,(Ix+d),C
+instr fetch_nop, op_SET4, store2_D ;E2 ;SET 4,(Ix+d),D
+instr fetch_nop, op_SET4, store2_E ;E3 ;SET 4,(Ix+d),E
+instr fetch_nop, op_SET4, store2_H ;E4 ;SET 4,(Ix+d),H
+instr fetch_nop, op_SET4, store2_L ;E5 ;SET 4,(Ix+d),L
+instr fetch_nop, op_SET4, store_nop ;E6 ;SET 4,(Ix+d)
+instr fetch_nop, op_SET4, store2_A ;E7 ;SET 4,(Ix+d),A
+instr fetch_nop, op_SET5, store2_B ;E8 ;SET 5,(Ix+d),B
+instr fetch_nop, op_SET5, store2_C ;E9 ;SET 5,(Ix+d),C
+instr fetch_nop, op_SET5, store2_D ;EA ;SET 5,(Ix+d),D
+instr fetch_nop, op_SET5, store2_E ;EB ;SET 5,(Ix+d),E
+instr fetch_nop, op_SET5, store2_H ;EC ;SET 5,(Ix+d),H
+instr fetch_nop, op_SET5, store2_L ;ED ;SET 5,(Ix+d),L
+instr fetch_nop, op_SET5, store_nop ;EE ;SET 5,(Ix+d)
+instr fetch_nop, op_SET5, store2_A ;EF ;SET 5,(Ix+d),A
+instr fetch_nop, op_SET6, store2_B ;F0 ;SET 6,(Ix+d),B
+instr fetch_nop, op_SET6, store2_C ;F1 ;SET 6,(Ix+d),C
+instr fetch_nop, op_SET6, store2_D ;F2 ;SET 6,(Ix+d),D
+instr fetch_nop, op_SET6, store2_E ;F3 ;SET 6,(Ix+d),E
+instr fetch_nop, op_SET6, store2_H ;F4 ;SET 6,(Ix+d),H
+instr fetch_nop, op_SET6, store2_L ;F5 ;SET 6,(Ix+d),L
+instr fetch_nop, op_SET6, store_nop ;F6 ;SET 6,(Ix+d)
+instr fetch_nop, op_SET6, store2_A ;F7 ;SET 6,(Ix+d),A
+instr fetch_nop, op_SET7, store2_B ;F8 ;SET 7,(Ix+d),B
+instr fetch_nop, op_SET7, store2_C ;F9 ;SET 7,(Ix+d),C
+instr fetch_nop, op_SET7, store2_D ;FA ;SET 7,(Ix+d),D
+instr fetch_nop, op_SET7, store2_E ;FB ;SET 7,(Ix+d),E
+instr fetch_nop, op_SET7, store2_H ;FC ;SET 7,(Ix+d),H
+instr fetch_nop, op_SET7, store2_L ;FD ;SET 7,(Ix+d),L
+instr fetch_nop, op_SET7, store_nop ;FE ;SET 7,(Ix+d)
+instr fetch_nop, op_SET7, store2_A ;FF ;SET 7,(Ix+d),A
+
+.macro m_do_fetch_0
+ ldi opl,0
+.endm
+.equ do_fetch_0 = 0
+; ldi opl,0
+; ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|IN r,[C] |***P0-|Input |r=[C] |
+;
+
+do_op_in: ; in opl,(opl)
+.if PORT_DEBUG
+ push opl
+ cp opl,_0 ; don't debug port 0 (con stat)
+ breq dbg_op_in_1
+ printnewline
+ printstring "Port read: ("
+ mov temp,opl
+ lcall printhex
+ printstring ") -> "
+dbg_op_in_1:
+.endif
+
+ mov temp2,opl
+ lcall portRead
+ mov opl,temp
+ bst z_flags,ZFL_C ;save Carry
+ ldpmx z_flags,sz53p_tab,temp ;S,Z,P
+ bld z_flags,ZFL_C
+
+.if PORT_DEBUG
+ pop temp
+ cp temp,_0
+ breq dbg_op_in_2
+ lcall printhex
+ printstring " "
+dbg_op_in_2:
+.endif
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|OUT [C],r |------|Output |[C]=r |
+;
+
+do_op_out: ; out (c),opl
+.if PORT_DEBUG
+ printnewline
+ printstring "Port write: "
+ mov temp,opl
+ lcall printhex
+ printstring " -> ("
+ mov temp,z_c
+ lcall printhex
+ printstring ") "
+.endif
+ mov temp,opl
+ mov temp2,z_c
+ lcall portWrite
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|LD dst,src|------|Load |dst=src |
+;
+
+do_op_stbc: ;store bc to mem loc in opl:h
+ movw xl,opl
+ mem_write_s z_c
+ adiw xl,1
+ mem_write_s z_b
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|LD dst,src|------|Load |dst=src |
+;
+;
+do_op_stde: ;store de to mem loc in opl:h
+ movw xl,opl
+ mem_write_s z_e
+ adiw xl,1
+ mem_write_s z_d
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|LD dst,src|------|Load |dst=src |
+;
+;
+do_op_stsp: ;store sp to mem loc in opl:h
+ movw xl,opl
+ mem_write_s z_spl
+ adiw xl,1
+ mem_write_s z_sph
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|ADC HL,ss |***V0*|Add with Carry |HL=HL+ss+CY |
+;
+
+do_op_ADCHL:
+ lsr z_flags ; ZFL_C --> Carry
+ ldi z_flags,0 ; clear N
+ adc z_l,opl
+ in temp,sreg ; save lower Z
+ adc z_h,oph
+ in temp2,sreg
+
+ and temp,temp2 ; 16bit Z
+ bmov z_flags,ZFL_C, temp2,AVR_C
+ bmov z_flags,ZFL_P, temp2,AVR_V
+ bmov z_flags,ZFL_H, temp2,AVR_H
+ bmov z_flags,ZFL_Z, temp,AVR_Z
+ bmov z_flags,ZFL_S, temp2,AVR_N
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|SBC HL,ss |***V1*|Subtract with carry |HL=HL-ss-CY |
+;
+
+ checkspace PC, 24
+
+do_op_sbchl:
+ lsr z_flags ; get Z80 carry
+ sez ; set z
+ sbc z_l,opl
+ sbc z_h,oph
+ in temp,sreg
+ ldi z_flags,(1<<ZFL_N) ; set N
+ bmov z_flags,ZFL_C, temp,AVR_C
+ bmov z_flags,ZFL_P, temp,AVR_V
+ bmov z_flags,ZFL_H, temp,AVR_H
+ bmov z_flags,ZFL_Z, temp,AVR_Z
+ bmov z_flags,ZFL_S, temp,AVR_N
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|NEG |***V1*|Negate A |A=0-A |
+
+;
+do_op_NEG:
+ ldi temp,0
+ sub temp,z_a
+ mov z_a,temp
+ in temp,sreg
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,P
+ bmov z_flags,ZFL_C, temp,AVR_C
+ bmov z_flags,ZFL_H, temp,AVR_H
+ do_z80_flags_V
+ do_z80_flags_set_N
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|RETI |------|Return from Interrupt|PC=[SP]+ |
+;|RETN |------|Return from NMI | Copy IFF2 to IFF1 |
+
+
+do_op_RETI:
+do_op_RETN:
+ ldd temp,y+oz_istat
+ bmov temp,IFF1, temp,IFF2
+ std y+oz_istat,temp
+ ljmp do_store_ret
+
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|IM n |------|Interrupt Mode | (n=0,1,2)|
+
+do_op_IM0:
+ ldd temp,y+oz_istat
+ andi temp, ~IM_MASK
+ std y+oz_istat,temp
+ ret
+
+do_op_IM1:
+ ldd temp,y+oz_istat
+ andi temp,~IM_MASK
+ ori temp,IM1
+ std y+oz_istat,temp
+ ret
+
+do_op_IM2:
+ ldd temp,y+oz_istat
+ andi temp, ~IM_MASK
+ ori temp,IM2
+ std y+oz_istat,temp
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|LD A,i |**0*0-|Load |(i=I,R) IFF2 --> P |
+;|LD i,A |------|Load |(i=I,R) |
+
+do_op_ldai:
+ ldd z_a,y+oz_i
+ rjmp op_ldar1
+
+do_op_ldar:
+ ldd z_a,y+oz_r
+op_ldar1:
+ bst z_flags,ZFL_C ;save C
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ bld z_flags,ZFL_C ;
+ ldd temp,y+oz_istat
+ bmov z_flags,ZFL_P, temp,IFF2
+ ret
+
+do_op_ldia:
+ std y+oz_i,z_a
+ ret
+
+do_op_ldra:
+ std y+oz_r,z_a
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|
+;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|
+
+do_op_rld:
+ swap opl
+ mov oph,opl
+ andi opl,0xf0
+ andi oph,0x0f
+ mov temp,z_a
+ andi temp,0x0f
+ or opl,temp
+ mov temp,z_a
+ andi temp,0xf0
+ or temp,oph
+ mov z_a,temp
+ bst z_flags,ZFL_C ;save C
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ bld z_flags,ZFL_C ;
+ ret
+
+do_op_rrd:
+ mov oph,opl
+ andi opl,0xf0
+ andi oph,0x0f
+ mov temp,z_a
+ andi temp,0x0f
+ or opl,temp
+ swap opl
+ mov temp,z_a
+ andi temp,0xf0
+ or temp,oph
+ mov z_a,temp
+ bst z_flags,ZFL_C ;save C
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ bld z_flags,ZFL_C ;
+ ret
+
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |
+;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |
+;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |
+;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
+;
+
+ checkspace PC, 13
+
+op_LDxx_common:
+; movw x,z_l ;
+; lcall dram_read ; temp = (HL)
+ mem_read_ds temp, z_hl
+; movw x,z_e ;
+; lcall dram_write ; (DE) = temp
+ mem_write_ds z_de, temp
+
+ cbr z_flags,(1<<ZFL_H) | (1<<ZFL_P) | (1<<ZFL_N)
+
+ movw x,z_c
+ sbiw x,1 ;BC--
+ movw z_c,x
+ breq PC+2
+ sbr z_flags,(1<<ZFL_P)
+ ret
+
+ checkspace PC, 6
+
+do_op_LDI:
+ rcall op_LDxx_common
+ sub z_e,_255 ;-low(-1) DE++
+ sbc z_d,_255 ;-high(-1)
+ sub z_l,_255 ;-low(-1) HL++
+ sbc z_h,_255 ;-high(-1)
+ ret
+
+ checkspace PC, 6
+
+do_op_LDD:
+ rcall op_LDxx_common
+ add z_e,_255 ;+low(-1) DE--
+ adc z_d,_255 ;+high(-1)
+ add z_l,_255 ;+low(-1) HL--
+ adc z_h,_255 ;+high(-1)
+ ret
+
+ checkspace PC, 5
+
+do_op_LDIR:
+ rcall do_op_LDI
+#if 1
+ sbrc z_flags,ZFL_P
+ rjmp do_op_LDIR
+ ret
+#else
+ sbrs z_flags,ZFL_P
+ ret
+ sbiw z_pcl,2
+ ret
+#endif
+
+ checkspace PC, 5
+
+do_op_LDDR:
+ rcall do_op_LDD
+#if 1
+ sbrc z_flags,ZFL_P
+ rjmp do_op_LDDR
+ ret
+#else
+ sbrs z_flags,ZFL_P
+ ret
+ sbiw z_pcl,2
+ ret
+#endif
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
+;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
+;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
+;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
+
+
+ checkspace PC, 21
+
+op_CPxx_common:
+ movw x,z_l ; HL
+
+ movw z,z_c ;BC
+
+ cbr z_flags,(1<<ZFL_S)|(1<<ZFL_Z)|(1<<ZFL_H)|(1<<ZFL_P)
+ sbr z_flags,(1<<ZFL_N)
+ lcall dram_read ; temp = (HL)
+
+ cp z_a,temp ; A - (HL)
+
+ brpl PC+2
+ sbr z_flags,(1<<ZFL_S)
+ brne PC+2
+ sbr z_flags,(1<<ZFL_Z)
+ brhc PC+2
+ sbr z_flags,(1<<ZFL_H)
+
+ sbiw z,1 ; BC--
+ breq PC+2
+ sbr z_flags,(1<<ZFL_P)
+ movw z_c,z ;BC
+ ret
+
+ checkspace PC, 5
+
+do_op_CPI:
+ rcall op_CPxx_common
+ adiw x,1 ; HL++
+ movw z_l,x ; HL
+ ret
+
+
+ checkspace PC, 5
+
+do_op_CPD:
+ rcall op_CPxx_common
+ sbiw x,1 ; HL--
+ movw z_l,x ; HL
+ ret
+
+ checkspace PC, 7
+
+do_op_CPIR:
+ rcall do_op_CPI
+ sbrc z_flags,ZFL_Z
+ ret
+ sbrs z_flags,ZFL_P
+ ret
+ sbiw z_pcl,2
+ ret
+
+ checkspace PC, 7
+
+do_op_CPDR:
+ rcall do_op_CPD
+ sbrc z_flags,ZFL_Z
+ ret
+ sbrs z_flags,ZFL_P
+ ret
+ sbiw z_pcl,2
+ ret
+
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;----------------------------------------------------------------
+;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|
+;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|
+;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
+;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
+
+ checkspace PC, 12
+
+op_INxx_common:
+ cbr z_flags,(1<<ZFL_Z)
+ sbr z_flags,(1<<ZFL_N)
+ mov temp2,z_c ;C
+ lcall portRead
+ movw x,z_l ;HL
+ lcall dram_write
+ dec z_b ;B
+ brne PC+2
+ sbr z_flags,(1<<ZFL_Z)
+ ret
+
+ checkspace PC, 4
+
+do_op_INI:
+ rcall op_INxx_common
+ adiw x,1
+ movw z_l,x ;HL
+ ret
+
+ checkspace PC, 4
+
+do_op_IND:
+ rcall op_INxx_common
+ sbiw x,1
+ movw z_l,x ;HL
+ ret
+
+ checkspace PC, 5
+
+do_op_INIR:
+ rcall do_op_INI
+ sbrc z_flags,ZFL_Z
+ ret
+ sbiw z_pcl,2
+ ret