-;----------------------------------------------------------------\r
-;| |\r
-;| Zilog |\r
-;| |\r
-;| ZZZZZZZ 88888 000 |\r
-;| Z 8 8 0 0 |\r
-;| Z 8 8 0 0 0 |\r
-;| Z 88888 0 0 0 |\r
-;| Z 8 8 0 0 0 |\r
-;| Z 8 8 0 0 |\r
-;| ZZZZZZZ 88888 000 |\r
-;| |\r
-;| Z80 MICROPROCESSOR Instruction Set Summary |\r
-;| |\r
-;----------------------------------------------------------------\r
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;|----------+------+---------------------+----------------------|\r
-;|ADC A,s |***V0*|Add with Carry |A=A+s+CY |\r
-;|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |\r
-;|ADD A,s |***V0*|Add |A=A+s |\r
-;|ADD HL,ss |--?-0*|Add |HL=HL+ss |\r
-;|ADD IX,pp |--?-0*|Add |IX=IX+pp |\r
-;|ADD IY,rr |--?-0*|Add |IY=IY+rr |\r
-;|AND s |***P00|Logical AND |A=A&s |\r
-;|BIT b,m |?*1?0-|Test Bit |m&{2^b} |\r
-;|CALL cc,nn|------|Conditional Call |If cc CALL |\r
-;|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |\r
-;|CCF |--?-0*|Complement Carry Flag|CY=~CY |\r
-;|CP s |***V1*|Compare |A-s |\r
-;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|\r
-;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|\r
-;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|\r
-;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|\r
-;|CPL |--1-1-|Complement |A=~A |\r
-;|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |\r
-;|DEC s |***V1-|Decrement |s=s-1 |\r
-;|DEC xx |------|Decrement |xx=xx-1 |\r
-;|DEC ss |------|Decrement |ss=ss-1 |\r
-;|DI |------|Disable Interrupts | |\r
-;|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |\r
-;|EI |------|Enable Interrupts | |\r
-;|EX [SP],HL|------|Exchange |[SP]<->HL |\r
-;|EX [SP],xx|------|Exchange |[SP]<->xx |\r
-;|EX AF,AF' |------|Exchange |AF<->AF' |\r
-;|EX DE,HL |------|Exchange |DE<->HL |\r
-;|EXX |------|Exchange |qq<->qq' (except AF)|\r
-;|HALT |------|Halt | |\r
-;|IM n |------|Interrupt Mode | (n=0,1,2)|\r
-;|IN A,[n] |------|Input |A=[n] |\r
-;|IN r,[C] |***P0-|Input |r=[C] |\r
-;|INC r |***V0-|Increment |r=r+1 |\r
-;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |\r
-;|INC xx |------|Increment |xx=xx+1 |\r
-;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |\r
-;|INC ss |------|Increment |ss=ss+1 |\r
-;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|\r
-;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |\r
-;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|\r
-;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |\r
-;|JP [HL] |------|Unconditional Jump |PC=[HL] |\r
-;|JP [xx] |------|Unconditional Jump |PC=[xx] |\r
-;|JP nn |------|Unconditional Jump |PC=nn |\r
-;|JP cc,nn |------|Conditional Jump |If cc JP |\r
-;|JR e |------|Unconditional Jump |PC=PC+e |\r
-;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|\r
-;|LD dst,src|------|Load |dst=src |\r
-;|LD A,i |**0*0-|Load |A=i (i=I,R)|\r
-;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |\r
-;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |\r
-;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |\r
-;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |\r
-;|NEG |***V1*|Negate |A=-A |\r
-;|NOP |------|No Operation | |\r
-;|OR s |***P00|Logical inclusive OR |A=Avs |\r
-;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |\r
-;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |\r
-;|OUT [C],r |------|Output |[C]=r |\r
-;|OUT [n],A |------|Output |[n]=A |\r
-;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|\r
-;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|\r
-;|POP xx |------|Pop |xx=[SP]+ |\r
-;|POP qq |------|Pop |qq=[SP]+ |\r
-;|PUSH xx |------|Push |-[SP]=xx |\r
-;|PUSH qq |------|Push |-[SP]=qq |\r
-;|RES b,m |------|Reset bit |m=m&{~2^b} |\r
-;|RET |------|Return |PC=[SP]+ |\r
-;|RET cc |------|Conditional Return |If cc RET |\r
-;|RETI |------|Return from Interrupt|PC=[SP]+ |\r
-;|RETN |------|Return from NMI |PC=[SP]+ |\r
-;|RL m |**0P0*|Rotate Left |m={CY,m}<- |\r
-;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |\r
-;|RLC m |**0P0*|Rotate Left Circular |m=m<- |\r
-;|RLCA |--0-0*|Rotate Left Circular |A=A<- |\r
-;----------------------------------------------------------------\r
-;----------------------------------------------------------------\r
-;|Mnemonic |SZHPNC|Description |Notes |\r
-;|----------+------+---------------------+----------------------|\r
-;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|\r
-;|RR m |**0P0*|Rotate Right |m=->{CY,m} |\r
-;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |\r
-;|RRC m |**0P0*|Rotate Right Circular|m=->m |\r
-;|RRCA |--0-0*|Rotate Right Circular|A=->A |\r
-;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|\r
-;|RST p |------|Restart | (p=0H,8H,10H,...,38H)|\r
-;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |\r
-;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |\r
-;|SCF |--0-01|Set Carry Flag |CY=1 |\r
-;|SET b,m |------|Set bit |m=mv{2^b} |\r
-;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |\r
-;|SRA m |**0P0*|Shift Right Arith. |m=m/2 |\r
-;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |\r
-;|SUB s |***V1*|Subtract |A=A-s |\r
-;|XOR s |***P00|Logical Exclusive OR |A=Axs |\r
-;|----------+------+--------------------------------------------|\r
-;| F |-*01? |Flag unaffected/affected/reset/set/unknown |\r
-;| S |S |Sign flag (Bit 7) |\r
-;| Z | Z |Zero flag (Bit 6) |\r
-;| HC | H |Half Carry flag (Bit 4) |\r
-;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) |\r
-;| N | N |Add/Subtract flag (Bit 1) |\r
-;| CY | C|Carry flag (Bit 0) |\r
-;|-----------------+--------------------------------------------|\r
-;| n |Immediate addressing |\r
-;| nn |Immediate extended addressing |\r
-;| e |Relative addressing (PC=PC+2+offset) |\r
-;| [nn] |Extended addressing |\r
-;| [xx+d] |Indexed addressing |\r
-;| r |Register addressing |\r
-;| [rr] |Register indirect addressing |\r
-;| |Implied addressing |\r
-;| b |Bit addressing |\r
-;| p |Modified page zero addressing (see RST) |\r
-;|-----------------+--------------------------------------------|\r
-;|DEFB n(,...) |Define Byte(s) |\r
-;|DEFB 'str'(,...) |Define Byte ASCII string(s) |\r
-;|DEFS nn |Define Storage Block |\r
-;|DEFW nn(,...) |Define Word(s) |\r
-;|-----------------+--------------------------------------------|\r
-;| A B C D E |Registers (8-bit) |\r
-;| AF BC DE HL |Register pairs (16-bit) |\r
-;| F |Flag register (8-bit) |\r
-;| I |Interrupt page address register (8-bit) |\r
-;| IX IY |Index registers (16-bit) |\r
-;| PC |Program Counter register (16-bit) |\r
-;| R |Memory Refresh register |\r
-;| SP |Stack Pointer register (16-bit) |\r
-;|-----------------+--------------------------------------------|\r
-;| b |One bit (0 to 7) |\r
-;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |\r
-;| d |One-byte expression (-128 to +127) |\r
-;| dst |Destination s, ss, [BC], [DE], [HL], [nn] |\r
-;| e |One-byte expression (-126 to +129) |\r
-;| m |Any register r, [HL] or [xx+d] |\r
-;| n |One-byte expression (0 to 255) |\r
-;| nn |Two-byte expression (0 to 65535) |\r
-;| pp |Register pair BC, DE, IX or SP |\r
-;| qq |Register pair AF, BC, DE or HL |\r
-;| qq' |Alternative register pair AF, BC, DE or HL |\r
-;| r |Register A, B, C, D, E, H or L |\r
-;| rr |Register pair BC, DE, IY or SP |\r
-;| s |Any register r, value n, [HL] or [xx+d] |\r
-;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] |\r
-;| ss |Register pair BC, DE, HL or SP |\r
-;| xx |Index register IX or IY |\r
-;|-----------------+--------------------------------------------|\r
-;| + - * / ^ |Add/subtract/multiply/divide/exponent |\r
-;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |\r
-;| <- -> |Rotate left/right |\r
-;| [ ] |Indirect addressing |\r
-;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|\r
-;| { } |Combination of operands |\r
-;| # |Also BC=BC-1,DE=DE-1 |\r
-;| ## |Only lower 4 bits of accumulator A used |\r
-;----------------------------------------------------------------\r
-\r
-
-;ToDo: Parity at more instructions...
-
+;----------------------------------------------------------------
+;| |
+;| Zilog |
+;| |
+;| ZZZZZZZ 88888 000 |
+;| Z 8 8 0 0 |
+;| Z 8 8 0 0 0 |
+;| Z 88888 0 0 0 |
+;| Z 8 8 0 0 0 |
+;| Z 8 8 0 0 |
+;| ZZZZZZZ 88888 000 |
+;| |
+;| Z80 MICROPROCESSOR Instruction Set Summary |
+;| |
+;----------------------------------------------------------------
+;----------------------------------------------------------------
+;|Mnemonic |SZHPNC|Description |Notes |
+;|----------+------+---------------------+----------------------|
+;|ADC A,s |***V0*|Add with Carry |A=A+s+CY |
+;|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |
+;|ADD A,s |***V0*|Add |A=A+s |
+;|ADD HL,ss |--?-0*|Add |HL=HL+ss |
+;|ADD IX,pp |--?-0*|Add |IX=IX+pp |
+;|ADD IY,rr |--?-0*|Add |IY=IY+rr |
+;|AND s |**1P00|Logical AND |A=A&s |
+;|BIT b,m |?*1?0-|Test Bit |m&{2^b} |
+;|CALL cc,nn|------|Conditional Call |If cc CALL |
+;|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |
+;|CCF |--?-0*|Complement Carry Flag|CY=~CY |
+;|CP s |***V1*|Compare |A-s |
+;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
+;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
+;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
+;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
+;|CPL |--1-1-|Complement |A=~A |
+;|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |
+;|DEC s |***V1-|Decrement |s=s-1 |
+;|DEC xx |------|Decrement |xx=xx-1 |
+;|DEC ss |------|Decrement |ss=ss-1 |
+;|DI |------|Disable Interrupts | |
+;|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |
+;|EI |------|Enable Interrupts | |
+;|EX [SP],HL|------|Exchange |[SP]<->HL |
+;|EX [SP],xx|------|Exchange |[SP]<->xx |
+;|EX AF,AF' |------|Exchange |AF<->AF' |
+;|EX DE,HL |------|Exchange |DE<->HL |
+;|EXX |------|Exchange |qq<->qq' (except AF)|
+;|HALT |------|Halt | |
+;|IM n |------|Interrupt Mode | (n=0,1,2)|
+;|IN A,[n] |------|Input |A=[n] |
+;|IN r,[C] |***P0-|Input |r=[C] |
+;|INC r |***V0-|Increment |r=r+1 |
+;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |
+;|INC xx |------|Increment |xx=xx+1 |
+;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |
+;|INC ss |------|Increment |ss=ss+1 |
+;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|
+;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
+;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|
+;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
+;|JP [HL] |------|Unconditional Jump |PC=[HL] |
+;|JP [xx] |------|Unconditional Jump |PC=[xx] |
+;|JP nn |------|Unconditional Jump |PC=nn |
+;|JP cc,nn |------|Conditional Jump |If cc JP |
+;|JR e |------|Unconditional Jump |PC=PC+e |
+;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|
+;|LD dst,src|------|Load |dst=src |
+;|LD A,i |**0*0-|Load |A=i (i=I,R)|
+;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |
+;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |
+;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |
+;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
+;|NEG |***V1*|Negate |A=-A |
+;|NOP |------|No Operation | |
+;|OR s |**0P00|Logical inclusive OR |A=Avs |
+;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |
+;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |
+;|OUT [C],r |------|Output |[C]=r |
+;|OUT [n],A |------|Output |[n]=A |
+;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|
+;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|
+;|POP xx |------|Pop |xx=[SP]+ |
+;|POP qq |------|Pop |qq=[SP]+ |
+;|PUSH xx |------|Push |-[SP]=xx |
+;|PUSH qq |------|Push |-[SP]=qq |
+;|RES b,m |------|Reset bit |m=m&{~2^b} |
+;|RET |------|Return |PC=[SP]+ |
+;|RET cc |------|Conditional Return |If cc RET |
+;|RETI |------|Return from Interrupt|PC=[SP]+ |
+;|RETN |------|Return from NMI |PC=[SP]+ |
+;|RL m |**0P0*|Rotate Left |m={CY,m}<- |
+;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |
+;|RLC m |**0P0*|Rotate Left Circular |m=m<- |
+;|RLCA |--0-0*|Rotate Left Circular |A=A<- |
+;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|
+;|RR m |**0P0*|Rotate Right |m=->{CY,m} |
+;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |
+;|RRC m |**0P0*|Rotate Right Circular|m=->m |
+;|RRCA |--0-0*|Rotate Right Circular|A=->A |
+;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|
+;|RST p |------|Restart | (p=0H,8H,10H,...,38H)|
+;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |
+;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |
+;|SCF |--0-01|Set Carry Flag |CY=1 |
+;|SET b,m |------|Set bit |m=mv{2^b} |
+;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |
+;|SRA m |**0P0*|Shift Right Arith. |m=m/2 |
+;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |
+;|SUB s |***V1*|Subtract |A=A-s |
+;|XOR s |**0P00|Logical Exclusive OR |A=Axs |
+;|----------+------+--------------------------------------------|
+
+
+.equ AVR_T = 6