; ------------------- DRAM Refresh Interrupt --------------------
.cseg
-; refresh interupt; exec 2 cbr cycles
-refrint: ;4
- .org OC2Aaddr
- rjmp refrint ; tim2cmpa
- .org refrint
+; Refresh interupt; exec 2 cbr cycles
+
+ INTERRUPT OC2Aaddr
+
sbis P_RAS,ram_ras ;2
reti
; CAS RAS
pop zl
pop zh
ret
-\r
- .dseg\r
+
+ .dseg
.cseg
-
+
; ****************************************************************************
.cseg
-sysclockint:
- .org OC1Baddr ; Timer/Counter1 Compare Match B
- rjmp sysclockint ; 1ms system timer
- .org sysclockint
+; Timer/Counter1 Compare Match B interrupt
+
+ INTERRUPT OC1Baddr
+
push zl
in zl,SREG
push zl