; 8080/Z80 Interpreter.
; This is part of the Z80-CP/M emulator written by Sprite_tm.
-;
+;
; Copyright (C) 2010 Sprite_tm
-; Copyright (C) 2010 Leo C.
+; Copyright (C) 2010-2013 Leo C.
; Copyright (C) 2010 Horst S.
; This file is part of avrcpm.
; You should have received a copy of the GNU General Public License
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
-; $Id$
+; $Id: Z80int-jmp.asm 93 2014-01-03 16:32:32Z rapid $
;
#if EM_Z80
.dseg
-z_regs:
+z_regs:
z_c2:
.equ oz_c2 = z_c2 - z_regs
.byte 1
#endif
.cseg
-
+
;Init z80
z80_init:
ldiw z_pc,IPLADDR
;TODO: hier kommt die Interruptbehandlung rein
- cpse intstat,_0 ;Fast path if no trace, int, break, ...
+ cpse intstat,_0 ; 2 Fast path if no trace, int, break, ...
rjmp int_test
int_instr:
- mem_read_ds zl,z_pc ;zl = memReadByte(z_pc)
- adiw z_pcl,1 ;++z_pc
- ldi zh,high(opcjmp) ;
- icall
- rjmp main ;
-
+ mem_read_ds zl,z_pc ;11 zl = memReadByte(z_pc)
+ adiw z_pcl,1 ; 2 ++z_pc
+ ldi zh,high(opcjmp) ; 1
+ icall ; 3 (+4 ret)
+ rjmp main ; 2
+ ; / 25 cycles minimum (NOP)
int_test:
sbrs intstat,i_trace
rjmp int_notrace
;--------------------------------------------------
-; init opcode table
+; init opcode table
;
; opctable opc_name, pos
;
.set opc_tablen_1 = 256
;.message "add tab_1"
.endif
- .else
+ .else
.if (opc_tablow_1 + opc_tablen_1) == opcjmp_table_pos_
.set opc_tablen_1 = opc_tablen_1 + 256
;.message "tab_1++"
.endm
;--------------------------------------------------
-;
+;
; checkspace frompos, size
;
.macro checkspace
;
; instr fetch, op, store
;
-.macro instr
+.macro instr
.set fetch_ = (do_@0 != do_fetch_nop) ; must call or jump to fetch action
.set op_ = (do_@1 != do_op_nop) ; must call or jump to op action
.org l_@0_@1_@2
.if fetch_ ; must fetch
- .if op_ || store_
+ .if op_ || store_
.if do_@0 == 0
m_do_@0
.else
.else
ljmp do_@2 ; store is allways last
.endif
- .endif
+ .endif
.endif
.endif
; mov opl,z_l
; ret
-do_fetch_af:
+.macro m_do_fetch_af
movw opl,z_flags
- ret
+.endm
+
+.equ do_fetch_af = 0
+; movw opl,z_flags
+; ret
.macro m_do_fetch_bc
movw opl,z_c
.endm
.equ do_fetch_de = 0
-; ldd opl,y+oz_e
-; ldd oph,y+oz_d
- ret
+; movw opl,z_e
+; ret
.macro m_do_fetch_hl
movw opl,z_l
; ret
do_fetch_mbc:
- movw x,z_c
- mem_read_d z_a
+; movw x,z_c
+ mem_read_ds z_a, z_bc
ret
do_fetch_mde:
- movw x,z_e
-; ldd xh,y+oz_d
-; ldd xl,y+oz_e
- mem_read_d z_a
+; movw x,z_e
+ mem_read_ds z_a, z_de
ret
do_fetch_mhl:
- movw x,z_l
- mem_read_d opl
+; movw x,z_l
+ mem_read_ds opl, z_hl
ret
do_fetch_msp:
store_ops:
.equ do_store_nop = do_x_nop
-
+
do_store_a:
mov z_a,opl
ret
-;.macro m_do_store_b
+;.macro m_do_store_b
; std y+oz_b,opl
;.endm
;.equ do_store_b = 0
ret
do_store_mbc:
- movw x,z_c
- mem_write_s z_a
+; movw x,z_c
+ mem_write_ds z_bc, z_a
ret
do_store_mde:
- movw x,z_e
-; ldd xh,y+oz_d
-; ldd xl,y+oz_e
- mem_write_s z_a
+; movw x,z_e
+ mem_write_ds z_de, z_a
ret
do_store_mhl:
- movw x,z_l
- mem_write_s opl
+; movw x,z_l
+ mem_write_ds z_hl, opl
ret
do_store_msp:
do_store_pcrel: ;add displacement to PC
#if EM_Z80
- clr oph
- tst opl ;sign extend
- brpl stpcr1
- com oph
-stpcr1:
+ mov oph,opl ;sign extend
+ lsl oph
+ sbc oph,oph
add z_pcl,opl
adc z_pch,oph
ret
.macro ldpmx
ldi zh,high(@1*2) ; table must be page aligned
- mov zl,@2
- lpm @0,z
+ mov zl,@2
+ lpm @0,z
.endm
.macro do_z80_flags_V
#endif
.endm
-
+
.macro do_z80_flags_copy_HC
#if EM_Z80
bmov z_flags, ZFL_H, z_flags, ZFL_C
;
do_op_ina: ; in a,(opl)
.if PORT_DEBUG
- push opl
+ push opl
cp opl,_0 ; don't debug port 0 (con stat)
breq dbg_op_ina_1
printnewline
bst z_flags,ZFL_C ; save C flag
subi opl,-1
in temp,sreg
- ldpmx z_flags,flagmap_tab,temp
+ ldpmx z_flags,flagmap_tab,temp
bld z_flags,ZFL_C
ret
#endif
;|INC xx |------|Increment |xx=xx+1 |
;|INC ss |------|Increment |ss=ss+1 |
;
-;
+;
do_op_inc16:
subi opl,low(-1)
sbci oph,high(-1)
;|DEC xx |------|Decrement |xx=xx-1 |
;|DEC ss |------|Decrement |ss=ss-1 |
;
-;
+;
do_op_dec16:
subi opl, 1
sbci oph, 0
;
;
do_op_rlca:
- ;Rotate Left Cyclical. All bits move 1 to the
+ ;Rotate Left Cyclical. All bits move 1 to the
;left, the msb becomes c and lsb.
do_z80_flags_op_rotate
lsl z_a
;|RRCA |---- *|Rotate Right Circular|A=->A |
;
;
-do_op_rrca:
- ;Rotate Right Cyclical. All bits move 1 to the
+do_op_rrca:
+ ;Rotate Right Cyclical. All bits move 1 to the
;right, the lsb becomes c and msb.
do_z80_flags_op_rotate
lsr z_a
;|----------|SZHP C|---------- 8080 ----------------------------|
;|RRA |---- *|Rotate Right Acc. |A=->{CY,A} |
;
-;
-do_op_rra:
- ;Rotate Right. All bits move 1 to the right, the lsb
+;
+do_op_rra:
+ ;Rotate Right. All bits move 1 to the right, the lsb
;becomes c, c becomes msb.
clc ; get z80 carry to avr carry
sbrc z_flags,ZFL_C
;|----------|SZHP C|---------- 8080 ----------------------------|
;|RLA |---- *|Rotate Left Acc. |A={CY,A}<- |
;
-;
+;
do_op_rla:
- ;Rotate Left. All bits move 1 to the left, the msb
+ ;Rotate Left. All bits move 1 to the left, the msb
;becomes c, c becomes lsb.
clc
sbrc z_flags,ZFL_C
;----------------------------------------------------------------
;|LD dst,src|------|Load |dst=src |
;
-;
+;
do_op_rmem16:
movw xl,opl
mem_read_d opl
;
; ---------------------
; | N | H | low |H' |
-; | | |nibble | |
+; | | |nibble | |
; |---+---+-------+---|
-; | 0 | * | 0-9 | 0 |
-; | 0 | * | a-f | 1 |
-; | 1 | 0 | * | 0 |
-; | 1 | 1 | 6-f | 0 |
-; | 1 | 1 | 0-5 | 1 |
+; | 0 | * | 0-9 | 0 |
+; | 0 | * | a-f | 1 |
+; | 1 | 0 | * | 0 |
+; | 1 | 1 | 6-f | 0 |
+; | 1 | 1 | 0-5 | 1 |
; ---------------------
;
; Ohter flags:
#if 0
#if EM_Z80
- sbrc z_flags,ZFL_N ;if add-op
+ sbrc z_flags,ZFL_N ;if add-op
rjmp op_da_sub ;then
#endif
brlo op_da_a10 ; |
op_da_a01: ; then
ldi oph,0x06 ; add 6 to lower nibble
- add opl,oph ;
- brhc op_da_02 ; if
+ add opl,oph ;
+ brhc op_da_02 ; if
ori temp2,(1<<ZFL_H) ; set new H flag
op_da_02: ;
brcc op_da_a10 ; if
sbrc z_flags,ZFL_C ; |
rjmp op_da_a12 ; if (C flag ...
cpi opl,0xA0 ; |... or upper nibble >= 0xA0)
- brlo op_da_a13 ;
+ brlo op_da_a13 ;
op_da_a12: ;
ldi oph,0x60 ; add 6 to lower nibble
add opl,oph ;
brlo op_da_s10 ; |
op_da_s01: ; then
ldi oph,0x06 ; add 6 to lower nibble
- sub opl,oph ;
- brhc PC+2 ; if
+ sub opl,oph ;
+ brhc PC+2 ; if
ori temp2,(1<<ZFL_H) ; set new H flag
brcc op_da_s10 ; if
ori temp2,(1<<ZFL_C) ; set new C flag
sbrc z_flags,ZFL_C ; |
rjmp op_da_s12 ; if (C flag ...
cpi opl,0x90 ; |... or upper nibble >= 0xA0)
- brlo op_da_s13 ;
+ brlo op_da_s13 ;
op_da_s12: ;
ldi oph,0x60 ; add 6 to lower nibble
sub opl,oph ;
ldi oph,0 ;oph: what to add
#if EM_Z80
- sbrc z_flags,ZFL_N ;if add-op
+ sbrc z_flags,ZFL_N ;if add-op
rjmp op_da_sub ;then
#endif
rjmp op_da_a02 ; if (C flag ...
cpi opl,0x90 ; |... or upper nibble >= 0x90)
brlo op_da_a03 ; |
-op_da_a02:
+op_da_a02:
ori oph,0x60 ; add 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_a03: ; endif
sbrc z_flags,ZFL_C ; |
rjmp op_da_a12 ; if (C flag ...
cpi opl,0xA0 ; |... or upper nibble >= 0xA0)
- brlo op_da_a13 ;
-op_da_a12:
+ brlo op_da_a13 ;
+op_da_a12:
ori oph,0x60 ; add 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_a13:
rjmp op_da_s02 ; if (C flag ...
cpi opl,0x90 ; |... or upper nibble >= 0x90)
brlo op_da_s03 ; |
-op_da_s02:
+op_da_s02:
ori oph,0x60 ; sub 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_s03: ; endif
sbrc z_flags,ZFL_C ; |
rjmp op_da_s12 ; if (C flag ...
cpi opl,0xA0 ; |... or upper nibble >= 0xA0)
- brlo op_da_s13 ;
-op_da_s12:
+ brlo op_da_s13 ;
+op_da_s12:
ori oph,0x60 ; sub 0x60
ori temp2,(1<<ZFL_C) ; set new C flag
op_da_s13:
;|EX [SP],HL|------|Exchange |[SP]<->HL |
;|EX DE,HL |------|Exchange |DE<->HL |
;-----------------------------Z80--------------------------------
-;
+;
do_op_exhl:
movw temp,z_l
movw z_l,opl
sbrs z_flags, ZFL_Z
ret
pop temp ; nix tun
- pop temp ; direkt zurueck zu main
+ pop temp ; direkt zurueck zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_Z
ret
pop temp ; nix tun
- pop temp ; direkt zurueck zu main
+ pop temp ; direkt zurueck zu main
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_C
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_C
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_P
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_P
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrs z_flags, ZFL_S
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
sbrc z_flags, ZFL_S
ret
pop temp ; nix tun
- pop temp ; direkt zuruech zu main
+ pop temp ; direkt zuruech zu main
ret
;----------------------------------------------------------------
dec z_b
brne opdjnze
pop temp ; nix tun
- pop temp ; direkt zurueck zu main
+ pop temp ; direkt zurueck zu main
opdjnze:
ret
mem_read_ds zl,z_pc ;zl = memReadByte(z_pc)
adiw z_pcl,1 ;++z_pc
ldi zh,high(EDjmp) ;
-;;; ldi zh,high(0) ;
ijmp
opprxcb_1:
mem_read_s z_pc ;get displacement
adiw z_pcl,1 ;++z_pc
- clr temp2 ;sign extend
- tst temp
- brpl PC+2
- com temp2
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_read_d opl
; Lookup table for Z80 opcodes. Translates the first byte of the instruction word into three
; operations: fetch, do something, store.
-; The table is made of 256 words.
+; The table is made of 256 words.
opctable opcjmp, PC ;+3*256
-
+
instr fetch_nop, op_nop, store_nop ;00 ;NOP
instr fetch_DIR16, op_nop, store_BC ;01 nn nn ;LD BC,nn
instr fetch_nop, op_nop, store_MBC ;02 ;LD (BC),A
fetchmxx1:
mem_read_ds opl, z_pc ;get displacement
adiw z_pcl,1
- clr oph ;sign extend
- tst opl
- brpl fetchmxx2
- com oph
-fetchmxx2:
+ mov oph,opl ;sign extend
+ lsl oph
+ sbc oph,oph
add xl,opl ;add displacement
adc xh,oph
mem_read_d opl ;get operand
storemxx1:
mem_read_s z_pc ;get displacement
adiw z_pcl,1
- clr temp2 ;sign extend
- tst temp
- brpl storemxx2
- com temp2
-storemxx2:
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_write_s opl ;store operand
mem_read_s z_pc ;get displacement
adiw z_pcl,1
adiw z_pcl,1
- clr temp2 ;sign extend
- tst temp
- brpl storemxx22
- com temp2
-storemxx22:
+ mov temp2,temp ;sign extend
+ lsl temp2
+ sbc temp2,temp2
add xl,temp ;add displacement
adc xh,temp2
mem_write_s opl ;store operand
;----------------------------------------------------------------
;|EX [SP],IX|------|Exchange |[SP]<->IX |
;|EX [SP],IY|------|Exchange |[SP]<->IY |
-;
+;
checkspace PC, 13
do_op_EXxx:
checkspace PC, 9
do_op_rlc:
- ;Rotate Left Cyclical. All bits move 1 to the
+ ;Rotate Left Cyclical. All bits move 1 to the
;left, the msb becomes c and lsb.
clr temp
lsl opl
adc temp,_0
or opl,temp
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
or z_flags,temp
ret
checkspace PC, 9
-do_op_rrc:
- ;Rotate Right Cyclical. All bits move 1 to the
+do_op_rrc:
+ ;Rotate Right Cyclical. All bits move 1 to the
;right, the lsb becomes c and msb.
lsr opl
brcc PC+2
ori opl,0x80
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, opl,7
ret
checkspace PC, 11
do_op_rl:
- ;Rotate Left. All bits move 1 to the left, the msb
+ ;Rotate Left. All bits move 1 to the left, the msb
;becomes c, c becomes lsb.
clc
sbrc z_flags,ZFL_C
sec
rol opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C
ret
checkspace PC, 10
do_op_rr:
- ;Rotate Right. All bits move 1 to the right, the lsb
+ ;Rotate Right. All bits move 1 to the right, the lsb
;becomes c, c becomes msb.
ror opl
in temp,sreg ;CY
bmov opl,7, z_flags,ZFL_C ;old CY --> Bit 7
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
do_op_sla:
lsl opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
lsr opl
in temp,sreg
bmov opl,7, opl,6 ;old CY --> Bit 7
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
sec
rol opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
do_op_srl:
lsr opl
in temp,sreg
- ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N
bmov z_flags,ZFL_C, temp,AVR_C ;
ret
; ret
-;.macro m_do_store_b
+;.macro m_do_store_b
; std y+oz_b,opl
;.endm
;.equ do_store_b = 0
checkspace PC, 4
do_fetch2_mhl:
- movw x,z_l
- mem_read_d opl
+; movw x,z_l
+ mem_read_ds opl, z_hl
ret
opctable CBjmp, PC ;+256
instr fetch_H, op_BIT0, store_nop ;44 ;BIT 0,H
instr fetch_L, op_BIT0, store_nop ;45 ;BIT 0,L
instr fetch2_mhl, op_BIT0, store_nop ;46 ;BIT 0,(HL)
-instr fetch_A, op_BIT0, store_nop ;47 ;BIT 0,A
+instr fetch_A, op_BIT0, store_nop ;47 ;BIT 0,A
instr fetch_B, op_BIT1, store_nop ;48 ;BIT 1,B
instr fetch_C, op_BIT1, store_nop ;49 ;BIT 1,C
instr fetch_D, op_BIT1, store_nop ;4A ;BIT 1,D
instr fetch_nop, op_RLC, store2_E ;03 ;RLC (Ix+d),E
instr fetch_nop, op_RLC, store2_H ;04 ;RLC (Ix+d),H
instr fetch_nop, op_RLC, store2_L ;05 ;RLC (Ix+d),L
-instr fetch_nop, op_RLC, store_nop ;06 ;RLC (Ix+d)
+instr fetch_nop, op_RLC, store_nop ;06 ;RLC (Ix+d)
instr fetch_nop, op_RLC, store2_A ;07 ;RLC (Ix+d),A
instr fetch_nop, op_RRC, store2_B ;08 ;RRC (Ix+d),B
instr fetch_nop, op_RRC, store2_C ;09 ;RRC (Ix+d),C
instr fetch_nop, op_RRC, store2_E ;0B ;RRC (Ix+d),E
instr fetch_nop, op_RRC, store2_H ;0C ;RRC (Ix+d),H
instr fetch_nop, op_RRC, store2_L ;0D ;RRC (Ix+d),L
-instr fetch_nop, op_RRC, store_nop ;0E ;RRC (Ix+d)
+instr fetch_nop, op_RRC, store_nop ;0E ;RRC (Ix+d)
instr fetch_nop, op_RRC, store2_A ;0F ;RRC (Ix+d),A
instr fetch_nop, op_RL, store2_B ;10 ;RL (Ix+d),B
instr fetch_nop, op_RL, store2_C ;11 ;RL (Ix+d),C
instr fetch_nop, op_RL, store2_E ;13 ;RL (Ix+d),E
instr fetch_nop, op_RL, store2_H ;14 ;RL (Ix+d),H
instr fetch_nop, op_RL, store2_L ;15 ;RL (Ix+d),L
-instr fetch_nop, op_RL, store_nop ;16 ;RL (Ix+d)
+instr fetch_nop, op_RL, store_nop ;16 ;RL (Ix+d)
instr fetch_nop, op_RL, store2_A ;17 ;RL (Ix+d),A
instr fetch_nop, op_RR, store2_B ;18 ;RR (Ix+d),B
instr fetch_nop, op_RR, store2_C ;19 ;RR (Ix+d),C
instr fetch_nop, op_RR, store2_E ;1B ;RR (Ix+d),E
instr fetch_nop, op_RR, store2_H ;1C ;RR (Ix+d),H
instr fetch_nop, op_RR, store2_L ;1D ;RR (Ix+d),L
-instr fetch_nop, op_RR, store_nop ;1E ;RR (Ix+d)
+instr fetch_nop, op_RR, store_nop ;1E ;RR (Ix+d)
instr fetch_nop, op_RR, store2_A ;1F ;RR (Ix+d),A
instr fetch_nop, op_SLA, store2_B ;20 ;SLA (Ix+d),B
instr fetch_nop, op_SLA, store2_C ;21 ;SLA (Ix+d),C
instr fetch_nop, op_SLA, store2_E ;23 ;SLA (Ix+d),E
instr fetch_nop, op_SLA, store2_H ;24 ;SLA (Ix+d),H
instr fetch_nop, op_SLA, store2_L ;25 ;SLA (Ix+d),L
-instr fetch_nop, op_SLA, store_nop ;26 ;SLA (Ix+d)
+instr fetch_nop, op_SLA, store_nop ;26 ;SLA (Ix+d)
instr fetch_nop, op_SLA, store2_A ;27 ;SLA (Ix+d),A
instr fetch_nop, op_SRA, store2_B ;28 ;SRA (Ix+d),B
instr fetch_nop, op_SRA, store2_C ;29 ;SRA (Ix+d),C
instr fetch_nop, op_SRA, store2_E ;2B ;SRA (Ix+d),E
instr fetch_nop, op_SRA, store2_H ;2C ;SRA (Ix+d),H
instr fetch_nop, op_SRA, store2_L ;2D ;SRA (Ix+d),L
-instr fetch_nop, op_SRA, store_nop ;2E ;SRA (Ix+d)
+instr fetch_nop, op_SRA, store_nop ;2E ;SRA (Ix+d)
instr fetch_nop, op_SRA, store2_A ;2F ;SRA (Ix+d),A
instr fetch_nop, op_SLL, store2_B ;30 ;SLL (Ix+d),B
instr fetch_nop, op_SLL, store2_C ;31 ;SLL (Ix+d),C
instr fetch_nop, op_SLL, store2_E ;33 ;SLL (Ix+d),E
instr fetch_nop, op_SLL, store2_H ;34 ;SLL (Ix+d),H
instr fetch_nop, op_SLL, store2_L ;35 ;SLL (Ix+d),L
-instr fetch_nop, op_SLL, store_nop ;36 ;SLL (Ix+d)
+instr fetch_nop, op_SLL, store_nop ;36 ;SLL (Ix+d)
instr fetch_nop, op_SLL, store2_A ;37 ;SLL (Ix+d),A
instr fetch_nop, op_SRL, store2_B ;38 ;SRL (Ix+d),B
instr fetch_nop, op_SRL, store2_C ;39 ;SRL (Ix+d),C
instr fetch_nop, op_SRL, store2_E ;3B ;SRL (Ix+d),E
instr fetch_nop, op_SRL, store2_H ;3C ;SRL (Ix+d),H
instr fetch_nop, op_SRL, store2_L ;3D ;SRL (Ix+d),L
-instr fetch_nop, op_SRL, store_nop ;3E ;SRL (Ix+d)
+instr fetch_nop, op_SRL, store_nop ;3E ;SRL (Ix+d)
instr fetch_nop, op_SRL, store2_A ;3F ;SRL (Ix+d),A
instr fetch_nop, op_BIT0, store_nop ;40 ;BIT 0,(Ix+d),B
instr fetch_nop, op_BIT0, store_nop ;41 ;BIT 0,(Ix+d),C
instr fetch_nop, op_BIT0, store_nop ;44 ;BIT 0,(Ix+d),H
instr fetch_nop, op_BIT0, store_nop ;45 ;BIT 0,(Ix+d),L
instr fetch_nop, op_BIT0, store_nop ;46 ;BIT 0,(Ix+d)
-instr fetch_nop, op_BIT0, store_nop ;47 ;BIT 0,(Ix+d),A
+instr fetch_nop, op_BIT0, store_nop ;47 ;BIT 0,(Ix+d),A
instr fetch_nop, op_BIT1, store_nop ;48 ;BIT 1,(Ix+d),B
instr fetch_nop, op_BIT1, store_nop ;49 ;BIT 1,(Ix+d),C
instr fetch_nop, op_BIT1, store_nop ;4A ;BIT 1,(Ix+d),D
instr fetch_nop, op_SET7, store_nop ;FE ;SET 7,(Ix+d)
instr fetch_nop, op_SET7, store2_A ;FF ;SET 7,(Ix+d),A
-do_fetch_0:
+.macro m_do_fetch_0
ldi opl,0
- ret
+.endm
+.equ do_fetch_0 = 0
+; ldi opl,0
+; ret
;----------------------------------------------------------------
;|Mnemonic |SZHPNC|Description |Notes |
do_op_in: ; in opl,(opl)
.if PORT_DEBUG
- push opl
+ push opl
cp opl,_0 ; don't debug port 0 (con stat)
breq dbg_op_in_1
printnewline
lsr z_flags ; ZFL_C --> Carry
ldi z_flags,0 ; clear N
adc z_l,opl
- in temp,sreg ; save lower Z
+ in temp,sreg ; save lower Z
adc z_h,oph
in temp2,sreg
ldd z_a,y+oz_r
op_ldar1:
bst z_flags,ZFL_C ;save C
- ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
bld z_flags,ZFL_C ;
ldd temp,y+oz_istat
bmov z_flags,ZFL_P, temp,IFF2
or temp,oph
mov z_a,temp
bst z_flags,ZFL_C ;save C
- ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
bld z_flags,ZFL_C ;
ret
or temp,oph
mov z_a,temp
bst z_flags,ZFL_C ;save C
- ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
+ ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N
bld z_flags,ZFL_C ;
ret
checkspace PC, 13
op_LDxx_common:
- movw x,z_l ;HL
-; mem_read_ds temp, z
- lcall dram_read ; temp = (HL)
- movw x,z_e ;DE
-; mem_write_ds x, temp
- lcall dram_write ; (DE) = temp
+; movw x,z_l ;
+; lcall dram_read ; temp = (HL)
+ mem_read_ds temp, z_hl
+; movw x,z_e ;
+; lcall dram_write ; (DE) = temp
+ mem_write_ds z_de, temp
cbr z_flags,(1<<ZFL_H) | (1<<ZFL_P) | (1<<ZFL_N)
do_op_LDDR:
rcall do_op_LDD
+#if 1
+ sbrc z_flags,ZFL_P
+ rjmp do_op_LDDR
+ ret
+#else
sbrs z_flags,ZFL_P
ret
sbiw z_pcl,2
ret
+#endif
;----------------------------------------------------------------
;|Mnemonic |SZHPNC|Description |Notes |
op_CPxx_common:
movw x,z_l ; HL
-
+
movw z,z_c ;BC
cbr z_flags,(1<<ZFL_S)|(1<<ZFL_Z)|(1<<ZFL_H)|(1<<ZFL_P)
; Lookup table, stolen from z80ex, Z80 emulation library.
; http://z80ex.sourceforge.net/
-; The S, Z, 5 and 3 bits and the parity of the lookup value
+; The S, Z, 5 and 3 bits and the parity of the lookup value
checkspace PC, 256
.org (PC+255) & 0xff00
; .org opcjmp + 256
-; .org sz53p_table_pos
; .org FLASHEND & 0xff00
-; .org 0x1fff & 0xff00
sz53p_tab:
.db 0x44,0x00,0x00,0x04,0x00,0x04,0x04,0x00
.db 0xac,0xa8,0xa8,0xac,0xa8,0xac,0xac,0xa8
.db 0xa4,0xa0,0xa0,0xa4,0xa0,0xa4,0xa4,0xa0
.db 0xa8,0xac,0xac,0xa8,0xac,0xa8,0xa8,0xac
-
-; vim:set ts=8 noet nowrap
+; vim:set ts=8 noet nowrap
projects / avrcpm.git / blobdiff