#define VMINOR 1
#ifndef DRAM_8BIT
- #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */
-#endif
+ #define DRAM_8BIT 1 /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/
+#endif /* 0 = only one 4 bit wide DRAM chip */
#ifndef F_CPU
#define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
#endif
#define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */
#define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */
-#if EM_Z80
- #define CPUSTR "Z80"
-#else
- #define CPUSTR "8080"
-#endif
-
;-----------------------------------------------------------------------
; Port declarations
.equ P_MMC_CS = PORTB
.equ P_A8 = PORTB
.equ P_RXD = PORTB
+.equ P_TXD = PORTB
;Port C
.equ RAM_RAS = 0
#define PORT7 0x87
+#if EM_Z80
+ #define CPUSTR "Z80"
+#else
+ #define CPUSTR "8080"
+#endif
+
#if defined __ATmega8__
.equ RXTXDR0 = UDR
.equ UCSR0A = UCSRA