+;-----------------------------------------------------------------------
+; Z80/8080 Virtual Ports
+
+#define TIMERPORT 0x40 /* Base z80 port address for clock access */
+#define TIMER_CTL TIMERPORT
+#define TIMER_MSECS TIMERPORT+1
+#define TIMER_SECS TIMER_MSECS+2
+#define CLOCKPORT TIMERPORT+7 /* Real time clock BCD (ss,mm,hh,DD,MM,YYYY) */
+
+#define starttimercmd 1
+#define quitTimerCmd 2
+#define printTimerCmd 15
+#define uptimeCmd 16
+
+#define DEBUGPORT 0x4F
+
+#define startTraceCmd 1 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */
+#define stopTraceCmd 0
+
+; Virtual I2C Interface
+#define I2CSTAT 0x05
+#define I2CCTRL 0x05
+#define I2CBLEN 0x06
+#define I2CADR 0x07
+#define I2CADRL 0x07
+#define I2CADRH 0x08
+
+; Simple ADC Interface
+#define ADC80 0x17
+#define ADC81 0x18
+
+; Port-Expander PCF8574
+#define PORT 0x80
+#define PORT0 0x80
+#define PORT1 0x81
+#define PORT2 0x82
+#define PORT3 0x83
+#define PORT4 0x84
+#define PORT5 0x85
+#define PORT6 0x86
+#define PORT7 0x87
+
+;-----------------------------------------------------------------------
+;
+
+#define PARTID 0x52 /* Partition table id */
+ /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
+#define IPLADDR 0x2000 /* Bootloader load address */
+
+#define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
+#define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
+ /* Most drams need 1/15.6µs. */
+#define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
+#define TXBUFSIZE 32 /* USART transmit buffer size. Must be power of 2 */
+
+#define I2C_CLOCK 100000 /* 100kHz */
+#define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */
+
+