; Configuration, hardware definition, ...
;
; Copyright (C) 2010 Sprite_tm
-; Copyright (C) 2010 Leo C.
+; Copyright (C) 2010,2012,2013 Leo C.
;
; This file is part of avrcpm.
;
; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
;
; $Id$
-;
-#define VMAJOR 2 /* Version number */
+#define VMAJOR 3 /* Version number */
#define VMINOR 2
-#ifndef DRAM_8BIT
- #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */
-#endif
-#ifndef F_CPU
- #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
-#endif
-#ifndef BAUD
- #define BAUD 38400 /* console baud rate */
-#endif
-
-#define K 1024
-#define M 1024*K
+;-----------------------------------------------------------------------
+;
+; Hardware and feature configuration
+;
-;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */
-#define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */
+; Supported MCUs are: atmega328P atmega168 atmega88 atmega8
+; Z80 emulation currently needs atmega328P, so this is the default.
+;#define atmega328p
-#ifndef FAT16_SUPPORT
- #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */
-#endif /* which may contain CP/M image files. */
-#define RAMDISKCNT 0 /* Number of RAM disks */
-#define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */
+; MCU frequency in Hz.
+;#define F_CPU 20000000
-#define PARTID 0x52 /* Partition table id */
- /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
-#define IPLADDR 0x2000 /* Bootloader load address */
+; Set this to 0, if you have a (one) DRAM chip whith 4 Bit data bus.
+;#define DRAM_8BIT 1
-#define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
-#define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
- /* Most drams need 1/15.6µs. */
-#define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
-#define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */
+; Baudrate of serial port (console).
+;#define BAUD 115200
+
+; I2C_SUPPORT defaults to 1 on 8-bit-ram systems and must be 0 on 4-bit-ram systems.
+; Set this do 0, if you don't have I2C peripherals and want to save some flash
+; or use the I2C pins for other purposes.
+;#define I2C_SUPPORT
+
+; Emulate Z80 cpu if 1, 8080 otherwise.
+;
+;#define EM_Z80 1
+
+; Uncomment and set RAMDISKCOUNT to 1-4 if you want to test the experimental and
+; unsupported ramdisk feature . Number depends on actual ram size (256kx4 - 4Mx8)
+; and bios dpb/dph definitions.
+;#define RAMDISKCNT 0
+
+; Uncomment and set to 0, if you need to save flash (ie. ATmega88).
+;#define FAT16_SUPPORT 1
+; Uncomment and set to 0, if you don't want to use CP/M partitions.
+; (Saves some bytes.)
+;#define CPMDSK_SUPPORT 1
+; Uncomment and set to 0, if you need to save flash.
+;#define MMCBOOTLOADER 1
-#define EM_Z80 0 /* we don't have any z80 instructions yet */
+; Uncomment to disable ADC support
+;#define ADC_SUPPORT 0
+
+;-----------------------------------------------------------------------
+;Debugging aids
.equ BOOTWAIT = 1
.equ MEMTEST = 1
-.equ MEMFILL = 1
+.equ MEMFILL = 1 /* Fill DRAM */
+.equ SRAM_FILL = 1 /* Fill unused SRAM */
.equ MMC_DEBUG = 0 /* Increase for more debugging */
+.equ MMC_DEBUG_RDW = 0
+.equ DSKSEL_DEBUG = 0
+.equ DISK_DEBUG = 0 /* 1 = BOOT/HOME debug, 2 = +R/W debug */
+.equ HOSTRW_DEBUG = 0
.equ FAT16_DEBUG = 0
-.equ FAT16_RWDEBUG = 0
.equ FAT16_DBG_FAT = 0
-.equ DISK_DEBUG = 0 /* Increase for more debugging */
-.equ HOSTRW_DEBUG = 0
.equ HEAP_DEBUG = 0
.equ PORT_DEBUG = 0
.equ INS_DEBUG = 0
.equ STACK_DBG = 0
.equ PRINT_PC = 0
+.equ TIMER_DEBUG = 0
+
+;-----------------------------------------------------------------------
+; Z80/8080 Virtual Ports
+
+#define READ_FUNC 7
+#define WRITE_FUNC 6
+#define BOOT_FUNC 5
+#define HOME_FUNC 4
+
+#define TIMERPORT 0x40 /* Base z80 port address for clock access */
+#define TIMER_CTL TIMERPORT
+#define TIMER_MSECS TIMERPORT+1
+#define TIMER_SECS TIMER_MSECS+2
+#define CLOCKPORT TIMERPORT+7 /* Real time clock BCD (ss,mm,hh,DD,MM,YYYY) */
+
+#define starttimercmd 1
+#define quitTimerCmd 2
+#define printTimerCmd 15
+#define uptimeCmd 16
+
+#define DEBUGPORT 0x4F
+
+#define startTraceCmd 0x01 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */
+#define stopTraceCmd 0x00
+#define PrintStackCmd 0x02
+
+; Virtual I2C Interface
+#define I2CSTAT 0x05
+#define I2CCTRL 0x05
+#define I2CBLEN 0x06
+#define I2CADR 0x07
+#define I2CADRL 0x07
+#define I2CADRH 0x08
+
+; Simple ADC Interface
+#define ADC80 0x17 /* Read Value from ADC6 Pin, 8 bit */
+#define ADC81 0x18 /* Read Value from ADC7 Pin, 8 bit */
+#define ADCTEMP 0x19 /* Read Value from Temp Sensor, 8 bit */
+#define ADCBGL 0x20 /* Read 1.1V Bandgap, 10 bit */
+#define ADCBGH 0x21 /* Read 1.1V Bandgap, 10 bit */
+
+
+; Port-Expander PCF8574
+#define PORT 0x80
+#define PORT0 0x80
+#define PORT1 0x81
+#define PORT2 0x82
+#define PORT3 0x83
+#define PORT4 0x84
+#define PORT5 0x85
+#define PORT6 0x86
+#define PORT7 0x87
+
+;-----------------------------------------------------------------------
+;
+
+#define PARTID 0x52 /* Partition table id */
+ /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
+#define IPLADDR 0x2000 /* Bootloader load address */
+
+#define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
+#define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
+ /* Most drams need 1/15.6µs. */
+#define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
+#define TXBUFSIZE 32 /* USART transmit buffer size. Must be power of 2 */
+
+#define I2C_CLOCK 100000 /* 100kHz */
+#define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */
+
#define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
-#define MEMFILL_VAL 0xCB /* Fill ram with cbs, which will trigger an invalid opcode error. */
+#define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */
#define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */
#define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */
+#define SRAMFILL_VAL 0x5A /* Fill unused SRAM */
+
+#ifndef DRAM_8BIT
+ #define DRAM_8BIT 1 /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/
+#endif /* 0 = only one 4 bit wide DRAM chip */
+#ifndef F_CPU
+ #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
+#endif
+#ifndef BAUD
+ #define BAUD 115200 /* console baud rate */
+#endif
+#ifndef I2C_SUPPORT
+ #define I2C_SUPPORT DRAM_8BIT /* I2C requires 8 bit DRAM */
+#endif
+#if I2C_SUPPORT && !DRAM_8BIT
+ #error "I2C_SUPPORT requires 8 bit DRAM (DRAM_8BIT=1)!"
+#endif
+#ifndef ADC_SUPPORT
+ #define ADC_SUPPORT 1
+#endif
+
+#ifndef EM_Z80
+ #define EM_Z80 1 /* Emulate Z80 if true, else 8080 */
+#endif
+
+#ifndef CPMDSK_SUPPORT
+ #define CPMDSK_SUPPORT 1 /* Include Support for CP/M partitions */
+#endif
+
+#ifndef FAT16_SUPPORT
+ #define FAT16_SUPPORT 1 /* Include Support for a FAT16 partition */
+#endif /* which may contain CP/M image files. */
+
+#ifndef RAMDISKCNT
+ #define RAMDISKCNT 0 /* Number of RAM disks */
+#endif
+#define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */
+
+/* MMC/SD Bootloader support. */
+#define BOOTLDRSIZE 2048 /* Bytes needed for Bootloader (1024 Words Bootsection Size) */
+#define DEVID_S "ACPM"
+#ifndef MMCBOOTLOADER
+ #define MMCBOOTLOADER 1
+#endif
+#ifndef TESTVERSION
+ #define TESTVERSION 0
+#endif
;-----------------------------------------------------------------------
; Port declarations
.equ P_MMC_CS = PORTB
.equ P_A8 = PORTB
.equ P_RXD = PORTB
+.equ P_TXD = PORTB
;Port C
.equ RAM_RAS = 0
.def _WE = r5
.def _255 = r6
.def _0 = r7
-.def z_a = r9
-;.def stx_bitcount = r9
-;.def stx_dr = r10
-
-.def srx_lastedgel = r10
-.def srx_lastedgeh = r11
-;.def insstore= r8 ;
-;.def insop = r13 ;
-
-.def insdecl = r12 ;
-.def insdech = r13 ;
-.def z_spl = r14
+
+.def z_c = r8 ;
+.def z_b = r9 ;
+.def z_e = r10 ;
+.def z_d = r11 ;
+.def z_l = r12 ;
+.def z_h = r13 ;
+.def z_spl = r14 ;
.def z_sph = r15 ;
.def temp = r16 ;
.def temp2 = r17 ;
-.def temp3 = r18
-.def temp4 = r19
+.def temp3 = r18 ;
+;.def temp4 = r19 ;
+.def intstat = r19 ;interpreter status / interrupt status
.def z_flags = r20 ;
-.def intstat = r21 ; interpreter status / interrupt status
+.def z_a = r21 ;
.def opl = r22 ;
.def oph = r23 ;
.def z_pcl = r24 ;
; xh ;r27
; yl ;r28
; yh ;r29
-; zl ;r30 ;
-; zh ;r31 ;
+; zl ;r30
+; zh ;r31
.equ i_break = 0 ;break detected flag
+.equ i_trace = 1 ;cpu interpreter trace flag
+.equ i_halt = 2 ;executing halt instruction
#if defined __ATmega8__
-.equ flags = TWBR
-.equ P_PUD = SFIOR
-#else
-.equ flags = GPIOR0
-.equ P_PUD = MCUCR
-#endif
+ #if DRAM_8BIT
+
+ .equ flags = UBRRL ;UART is unused with 8-Bit RAM
+ #else
+ .equ flags = TWBR ;TWI is unused with 4-Bit RAM
+ #endif
+ .equ P_PUD = SFIOR
+
+#else
+
+ .equ flags = GPIOR0
+ .equ P_PUD = MCUCR
+
+#endif /* __ATmega8__ */
; Flags:
.equ hostact = 7 ;host active flag
.equ hostwrt = 6 ;host written flag
.equ rsflag = 5 ;read sector flag
.equ readop = 4 ;1 if read operation
- .equ trace = 0
-; This is the base z80 port address for clock access
-#define TIMERPORT 0x40
-#define TIMER_CTL TIMERPORT
-#define TIMER_MSECS TIMERPORT+1
-#define TIMER_SECS TIMER_MSECS+2
+ .equ prefixfd = 1 ;Opcode prefix DD=0, FD=1
-#define starttimercmd 1
-#define quitTimerCmd 2
-#define printTimerCmd 15
-#define uptimeCmd 16
+
+#if EM_Z80
+ #define CPUSTR "Z80"
+#else
+ #define CPUSTR "8080"
+#endif
+#if TESTVERSION
+ #define TESTSTR "Test"
+#else
+ #define TESTSTR ""
+#endif
#if defined __ATmega8__
.equ RXTXDR0 = UDR
; vim:set ts=8 noet nowrap
-
projects / avrcpm.git / blobdiff