* RAMDISK (re)integrated

[avrcpm.git] / avr / config.inc

diff --git a/avr/config.inc b/avr/config.inc
index 0ef4c915874b407b562661a1f38746b81051d5b5..48f4b4aca855a19c3ef813f43f8e242c8928de08 100644 (file)
--- a/avr/config.inc
+++ b/avr/config.inc
@@ -22,8 +22,8 @@
 ;
 
 
-#define VMAJOR 2               /* Version number */
-#define VMINOR 2
+#define VMAJOR 3               /* Version number */
+#define VMINOR 0
 
 #ifndef DRAM_8BIT
   #define DRAM_8BIT 1          /* 1 = 8bit wide DRAM */
@@ -41,10 +41,12 @@
 ;#define RAMSIZE 256*K*4       /* 1 chip 256Kx4 */
 #define  RAMSIZE   4*M*4 * 2   /* 2 chips 4Mx4  */
 
+#define EM_Z80 1               /* Emulate Z80 if true */
+
 #ifndef FAT16_SUPPORT
   #define FAT16_SUPPORT 1      /* Include Support for FAT16 Partitions */
 #endif                         /*  which may contain CP/M image files. */ 
-#define RAMDISKCNT    0                /* Number of RAM disks */
+#define RAMDISKCNT    4                /* Number of RAM disks */
 #define RAMDISKNR     'I'-'A'  /* Drive "letter" for first RAM disk */
 
 #define PARTID 0x52            /* Partition table id */
@@ -58,8 +60,11 @@
 #define        TXBUFSIZE 128           /* USART transmit buffer size. Must be power of 2 */
 
 
-
-#define EM_Z80 0               /* we don't have any z80 instructions yet */
+#if EM_Z80
+  #define CPUSTR "Z80"
+#else
+  #define CPUSTR "8080"
+#endif
 
 .equ BOOTWAIT      = 1
 .equ MEMTEST       = 1
@@ -78,7 +83,7 @@
 
 #define MMC_SPI2X  1           /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
 
-#define MEMFILL_VAL      0xCB  /* Fill ram with cbs, which will trigger an invalid opcode error. */
+#define MEMFILL_VAL      0x76  /* Fill ram with HALT opcode. */
 #define DBG_TRACE_BOTTOM 0x01  /* Page boundaries for INS_DEBUG and PRINT_PC  */
 #define DBG_TRACE_TOP   0xdc   /* Trace is off, below bottom page and above top page. */
 
@@ -234,6 +239,8 @@
 
 
 .equ   i_break = 0                     ;break detected flag
+.equ   i_trace = 1                     ;cpu interpreter trace flag
+.equ   i_halt  = 2                     ;executing halt instruction
 
 #if defined __ATmega8__
 .equ   flags   = TWBR
@@ -248,7 +255,9 @@
        .equ    hostwrt = 6             ;host written flag
        .equ    rsflag  = 5             ;read sector flag
        .equ    readop  = 4             ;1 if read operation
-       .equ    trace   = 0
+
+       .equ    prefixfd = 1            ;Opcode prefix DD=0, FD=1
+       .equ    trace    = 0
 
 ; This is the base z80 port address for clock access
 #define        TIMERPORT   0x40
@@ -261,6 +270,12 @@
 #define printTimerCmd  15
 #define uptimeCmd      16
 
+#define DEBUGPORT   0x4F
+
+#define startTraceCmd 1
+#define stopTraceCmd  0
+
+
 #if defined __ATmega8__
 .equ   RXTXDR0 = UDR
 .equ   UCSR0A  = UCSRA