.include "m88def.inc"
;device ATmega88
-.equ MMC_DEBUG = 0
-.equ INS_DEBUG = 0
-.equ MEMTEST = 0
-.equ BOOTWAIT = 0
-.equ PORT_DEBUG = 0
-.equ DISK_DEBUG = 0
-.equ MEMFILL_CB = 1
-.equ STACK_DBG = 0
-.equ PRINT_PC = 0
+.equ MMC_DEBUG = 0
+.equ INS_DEBUG = 0
+.equ MEMTEST = 0
+.equ BOOTWAIT = 0
+.equ PORT_DEBUG = 0
+.equ DISK_DEBUG = 0
+.equ MEMFILL_CB = 1
+.equ STACK_DBG = 0
+.equ PRINT_PC = 0
;Port declarations
; Port D
-.equ rxd = 0
-.equ txd = 1
-.equ ram_oe = 2
-.equ ram_a8 = 3
-.equ mmc_cs = 4
-.equ ram_a5 = 5
-.equ ram_a6 = 6
-.equ ram_a7 = 7
+.equ rxd = 0
+.equ txd = 1
+.equ ram_oe = 2
+.equ ram_a8 = 3
+.equ mmc_cs = 4
+.equ ram_a5 = 5
+.equ ram_a6 = 6
+.equ ram_a7 = 7
;Port B
.equ ram_a4 = 0
.equ ZFL_C = 0
;Register definitions
-.def z_a = r2
-.def z_b = r3
-.def z_c = r4
-.def z_d = r5
-.def z_e = r6
-.def z_l = r7
-.def z_h = r8
-.def z_spl = r9
-.def z_sph = r10
-
-.def dsk_trk= r11
-.def dsk_sec= r12
-.def dsk_dmah= r13
-.def dsk_dmal= r14
-
-.def parityb= r15
-
-.def temp = R16 ;The temp register
-.def temp2 = R17 ;Second temp register
-.def trace = r18
-.def opl = r19
-.def oph = r20
-.def adrl = r21
-.def adrh = r22
-.def insdecl= r23
-.def z_pcl = r24
-.def z_pch = r25
-.def insdech= r26
-.def z_flags= r27
+.def z_a = r2
+.def z_b = r3
+.def z_c = r4
+.def z_d = r5
+.def z_e = r6
+.def z_l = r7
+.def z_h = r8
+.def z_spl = r9
+.def z_sph = r10
+
+.def dsk_trk = r11
+.def dsk_sec = r12
+.def dsk_dmah = r13
+.def dsk_dmal = r14
+
+.def parityb = r15
+
+.def temp = R16 ;The temp register
+.def temp2 = R17 ;Second temp register
+.def trace = r18
+.def opl = r19
+.def oph = r20
+.def adrl = r21
+.def adrh = r22
+.def insdecl = r23
+.def z_pcl = r24
+.def z_pch = r25
+.def insdech = r26
+.def z_flags = r27
;SRAM
.endif
rcall printstr
- .db "CPM on an AVR, v1.0",13,0
+ .db "CPM on an AVR, v1.0",13,0,0
rcall printstr
ldi trace,0
rcall printstr
- .db 13,"Ok, CPU is live!",13,0
+ .db 13,"Ok, CPU is live!",13,0,0
main:
ldi trace,0
;
;I sure hope I got the mapping between flags and instructions correct...
+;----------------------------------------------------------------\r
+;| |\r
+;| Zilog |\r
+;| |\r
+;| ZZZZZZZ 88888 000 |\r
+;| Z 8 8 0 0 |\r
+;| Z 8 8 0 0 0 |\r
+;| Z 88888 0 0 0 |\r
+;| Z 8 8 0 0 0 |\r
+;| Z 8 8 0 0 |\r
+;| ZZZZZZZ 88888 000 |\r
+;| |\r
+;| Z80 MICROPROCESSOR Instruction Set Summary |\r
+;| |\r
+;----------------------------------------------------------------\r
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;|----------+------+---------------------+----------------------|\r
+;|ADC A,s |***V0*|Add with Carry |A=A+s+CY |\r
+;|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |\r
+;|ADD A,s |***V0*|Add |A=A+s |\r
+;|ADD HL,ss |--?-0*|Add |HL=HL+ss |\r
+;|ADD IX,pp |--?-0*|Add |IX=IX+pp |\r
+;|ADD IY,rr |--?-0*|Add |IY=IY+rr |\r
+;|AND s |***P00|Logical AND |A=A&s |\r
+;|BIT b,m |?*1?0-|Test Bit |m&{2^b} |\r
+;|CALL cc,nn|------|Conditional Call |If cc CALL |\r
+;|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |\r
+;|CCF |--?-0*|Complement Carry Flag|CY=~CY |\r
+;|CP s |***V1*|Compare |A-s |\r
+;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|\r
+;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|\r
+;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|\r
+;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|\r
+;|CPL |--1-1-|Complement |A=~A |\r
+;|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |\r
+;|DEC s |***V1-|Decrement |s=s-1 |\r
+;|DEC xx |------|Decrement |xx=xx-1 |\r
+;|DEC ss |------|Decrement |ss=ss-1 |\r
+;|DI |------|Disable Interrupts | |\r
+;|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |\r
+;|EI |------|Enable Interrupts | |\r
+;|EX [SP],HL|------|Exchange |[SP]<->HL |\r
+;|EX [SP],xx|------|Exchange |[SP]<->xx |\r
+;|EX AF,AF' |------|Exchange |AF<->AF' |\r
+;|EX DE,HL |------|Exchange |DE<->HL |\r
+;|EXX |------|Exchange |qq<->qq' (except AF)|\r
+;|HALT |------|Halt | |\r
+;|IM n |------|Interrupt Mode | (n=0,1,2)|\r
+;|IN A,[n] |------|Input |A=[n] |\r
+;|IN r,[C] |***P0-|Input |r=[C] |\r
+;|INC r |***V0-|Increment |r=r+1 |\r
+;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |\r
+;|INC xx |------|Increment |xx=xx+1 |\r
+;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |\r
+;|INC ss |------|Increment |ss=ss+1 |\r
+;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|\r
+;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |\r
+;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|\r
+;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |\r
+;|JP [HL] |------|Unconditional Jump |PC=[HL] |\r
+;|JP [xx] |------|Unconditional Jump |PC=[xx] |\r
+;|JP nn |------|Unconditional Jump |PC=nn |\r
+;|JP cc,nn |------|Conditional Jump |If cc JP |\r
+;|JR e |------|Unconditional Jump |PC=PC+e |\r
+;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|\r
+;|LD dst,src|------|Load |dst=src |\r
+;|LD A,i |**0*0-|Load |A=i (i=I,R)|\r
+;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |\r
+;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |\r
+;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |\r
+;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |\r
+;|NEG |***V1*|Negate |A=-A |\r
+;|NOP |------|No Operation | |\r
+;|OR s |***P00|Logical inclusive OR |A=Avs |\r
+;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 |\r
+;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |\r
+;|OUT [C],r |------|Output |[C]=r |\r
+;|OUT [n],A |------|Output |[n]=A |\r
+;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|\r
+;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|\r
+;|POP xx |------|Pop |xx=[SP]+ |\r
+;|POP qq |------|Pop |qq=[SP]+ |\r
+;|PUSH xx |------|Push |-[SP]=xx |\r
+;|PUSH qq |------|Push |-[SP]=qq |\r
+;|RES b,m |------|Reset bit |m=m&{~2^b} |\r
+;|RET |------|Return |PC=[SP]+ |\r
+;|RET cc |------|Conditional Return |If cc RET |\r
+;|RETI |------|Return from Interrupt|PC=[SP]+ |\r
+;|RETN |------|Return from NMI |PC=[SP]+ |\r
+;|RL m |**0P0*|Rotate Left |m={CY,m}<- |\r
+;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |\r
+;|RLC m |**0P0*|Rotate Left Circular |m=m<- |\r
+;|RLCA |--0-0*|Rotate Left Circular |A=A<- |\r
+;----------------------------------------------------------------\r
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;|----------+------+---------------------+----------------------|\r
+;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|\r
+;|RR m |**0P0*|Rotate Right |m=->{CY,m} |\r
+;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |\r
+;|RRC m |**0P0*|Rotate Right Circular|m=->m |\r
+;|RRCA |--0-0*|Rotate Right Circular|A=->A |\r
+;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|\r
+;|RST p |------|Restart | (p=0H,8H,10H,...,38H)|\r
+;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |\r
+;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |\r
+;|SCF |--0-01|Set Carry Flag |CY=1 |\r
+;|SET b,m |------|Set bit |m=mv{2^b} |\r
+;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |\r
+;|SRA m |**0P0*|Shift Right Arith. |m=m/2 |\r
+;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |\r
+;|SUB s |***V1*|Subtract |A=A-s |\r
+;|XOR s |***P00|Logical Exclusive OR |A=Axs |\r
+;|----------+------+--------------------------------------------|\r
+;| F |-*01? |Flag unaffected/affected/reset/set/unknown |\r
+;| S |S |Sign flag (Bit 7) |\r
+;| Z | Z |Zero flag (Bit 6) |\r
+;| HC | H |Half Carry flag (Bit 4) |\r
+;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) |\r
+;| N | N |Add/Subtract flag (Bit 1) |\r
+;| CY | C|Carry flag (Bit 0) |\r
+;|-----------------+--------------------------------------------|\r
+;| n |Immediate addressing |\r
+;| nn |Immediate extended addressing |\r
+;| e |Relative addressing (PC=PC+2+offset) |\r
+;| [nn] |Extended addressing |\r
+;| [xx+d] |Indexed addressing |\r
+;| r |Register addressing |\r
+;| [rr] |Register indirect addressing |\r
+;| |Implied addressing |\r
+;| b |Bit addressing |\r
+;| p |Modified page zero addressing (see RST) |\r
+;|-----------------+--------------------------------------------|\r
+;|DEFB n(,...) |Define Byte(s) |\r
+;|DEFB 'str'(,...) |Define Byte ASCII string(s) |\r
+;|DEFS nn |Define Storage Block |\r
+;|DEFW nn(,...) |Define Word(s) |\r
+;|-----------------+--------------------------------------------|\r
+;| A B C D E |Registers (8-bit) |\r
+;| AF BC DE HL |Register pairs (16-bit) |\r
+;| F |Flag register (8-bit) |\r
+;| I |Interrupt page address register (8-bit) |\r
+;| IX IY |Index registers (16-bit) |\r
+;| PC |Program Counter register (16-bit) |\r
+;| R |Memory Refresh register |\r
+;| SP |Stack Pointer register (16-bit) |\r
+;|-----------------+--------------------------------------------|\r
+;| b |One bit (0 to 7) |\r
+;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |\r
+;| d |One-byte expression (-128 to +127) |\r
+;| dst |Destination s, ss, [BC], [DE], [HL], [nn] |\r
+;| e |One-byte expression (-126 to +129) |\r
+;| m |Any register r, [HL] or [xx+d] |\r
+;| n |One-byte expression (0 to 255) |\r
+;| nn |Two-byte expression (0 to 65535) |\r
+;| pp |Register pair BC, DE, IX or SP |\r
+;| qq |Register pair AF, BC, DE or HL |\r
+;| qq' |Alternative register pair AF, BC, DE or HL |\r
+;| r |Register A, B, C, D, E, H or L |\r
+;| rr |Register pair BC, DE, IY or SP |\r
+;| s |Any register r, value n, [HL] or [xx+d] |\r
+;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] |\r
+;| ss |Register pair BC, DE, HL or SP |\r
+;| xx |Index register IX or IY |\r
+;|-----------------+--------------------------------------------|\r
+;| + - * / ^ |Add/subtract/multiply/divide/exponent |\r
+;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |\r
+;| <- -> |Rotate left/right |\r
+;| [ ] |Indirect addressing |\r
+;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|\r
+;| { } |Combination of operands |\r
+;| # |Also BC=BC-1,DE=DE-1 |\r
+;| ## |Only lower 4 bits of accumulator A used |\r
+;----------------------------------------------------------------\r
+\r
;ToDo: Parity at more instructions...
do_op_nop:
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|INC r |***V0-|Increment |r=r+1 |\r
+;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |\r
+;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |\r
+;\r
+; OK\r
do_op_inc:
- andi z_flags,1
- ldi temp,1
- add opl,temp
- in temp,sreg
- mov parityb,opl
- bst temp,AVR_Z
- bld z_flags,ZFL_Z
- sbrc opl,7
- ori z_flags,(1<<ZFL_S)
- bst temp,AVR_H
- bld z_flags,ZFL_H
- ret
-
+ andi z_flags, (1<<ZFL_C) ; bis auf Carry alles auf 0
+ ldi temp, 1
+ add opl, temp
+ in temp, sreg
+ mov parityb, opl
+ bst temp, AVR_Z ; Zero
+ bld z_flags, ZFL_Z
+ sbrc opl, 7 ; Sign
+ ori z_flags, (1<<ZFL_S)
+ bst temp, AVR_H ; Half Sign
+ bld z_flags, ZFL_H\r
+ bst temp, AVR_C ; Overflow\r
+ bld z_flags, ZFL_P\r
+ ret
+
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|DEC s |***V1-|Decrement |s=s-1 |\r
+;\r
+; OK\r
do_op_dec:
- andi z_flags,1
- ori z_flags,(1<<ZFL_N)
- ldi temp,1
- sub opl,temp
- in temp,sreg
- mov parityb,opl
- bst temp,AVR_Z
- bld z_flags,ZFL_Z
- bst temp,AVR_S
- bld z_flags,ZFL_S
- bst temp,AVR_H
- bld z_flags,ZFL_H
- ret
-
+ andi z_flags, (1<<ZFL_C) ; bis auf Carry alles auf 0
+ ori z_flags, (1<<ZFL_N) ; Negation auf 1
+ ldi temp, 1
+ sub opl, temp
+ in temp, sreg
+ mov parityb, opl
+ bst temp, AVR_Z ; Zero
+ bld z_flags, ZFL_Z
+ bst temp, AVR_S ; Sign
+ bld z_flags, ZFL_S
+ bst temp, AVR_H ; Half Sign
+ bld z_flags, ZFL_H
+ bst temp, AVR_C ; Underflow\r
+ bld z_flags, ZFL_P\r
+ ret
+\r
+\r
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|INC xx |------|Increment |xx=xx+1 |\r
+;|INC ss |------|Increment |ss=ss+1 |\r
+;\r
+; OK\r
do_op_inc16:
- ldi temp,1
- ldi temp2,0
- add opl,temp
- adc oph,temp2
- ret
-
+ ldi temp, 1
+ ldi temp2, 0
+ add opl, temp
+ adc oph, temp2
+ ret
+
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|DEC xx |------|Decrement |xx=xx-1 |\r
+;|DEC ss |------|Decrement |ss=ss-1 |\r
+;\r
+; OK\r
do_op_dec16:
- ldi temp,1
- ldi temp2,0
- sub opl,temp
- sbc oph,temp2
- ret
-
+ ldi temp, 1
+ ldi temp2, 0
+ sub opl, temp
+ sbc oph, temp2
+ ret
+
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|RLCA |--0-0*|Rotate Left Circular |A=A<- |\r
+;\r
+; OK\r
do_op_rlc:
;Rotate Left Cyclical. All bits move 1 to the
;left, the msb becomes c and lsb.
- andi z_flags,0b11101100
- lsl opl
- brcc do_op_rlc_noc
- ori opl,1
- ori z_flags,(1<<ZFL_C)
+ andi z_flags, ~( (1<<ZFL_H) | (1<<ZFL_N) | (1<<ZFL_C) )
+ lsl opl
+ brcc do_op_rlc_noc
+ ori opl, 1
+ ori z_flags, (1<<ZFL_C)
do_op_rlc_noc:
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|RRCA |--0-0*|Rotate Right Circular|A=->A |\r
+;\r
+; OK\r
do_op_rrc:
;Rotate Right Cyclical. All bits move 1 to the
;right, the lsb becomes c and msb.
- andi z_flags,0b11101100
- lsr opl
- brcc do_op_rrc_noc
- ori opl,0x80
- ori z_flags,(1<<ZFL_C)
+ andi z_flags, ~( (1<<ZFL_H) | (1<<ZFL_N) | (1<<ZFL_C) )
+ lsr opl
+ brcc do_op_rrc_noc
+ ori opl, 0x80
+ ori z_flags, (1<<ZFL_C)
do_op_rrc_noc:
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |\r
+;\r
+; OK\r
do_op_rr:
;Rotate Right. All bits move 1 to the right, the lsb
;becomes c, c becomes msb.
clc
- sbrc z_flags,ZFL_C
- sec
- ror opl
- in temp,sreg
- andi z_flags,0b11101100
- bst temp,AVR_C
- bld z_flags,ZFL_C
- ret
-
+ sbrc z_flags,ZFL_C
+ sec
+ ror opl
+ in temp,sreg
+ andi z_flags,~( (1<<ZFL_H) | (1<<ZFL_N) | (1<<ZFL_C) )
+ bst temp,AVR_C
+ bld z_flags,ZFL_C
+ ret
+
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_rl:
;Rotate Left. All bits move 1 to the left, the msb
;becomes c, c becomes lsb.
bld z_flags,ZFL_C
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_adda:
ldi z_flags,0
add opl,z_a
bld z_flags,ZFL_C
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_adca:
clc
sbrc z_flags,ZFL_C
andi z_flags,~(1<<ZFL_N)
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_subfa:
mov temp,z_a
sub temp,opl
ori z_flags,(1<<ZFL_N)
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_sbcfa:
mov temp,z_a
clc
ori z_flags,(1<<ZFL_N)
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_anda:
ldi z_flags,0
and opl,z_a
mov temp,opl
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ora:
ldi z_flags,0
or opl,z_a
mov temp,opl
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_xora:
ldi z_flags,0
eor opl,z_a
mov temp,opl
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_addhl:
add opl,z_l
adc oph,z_h
andi z_flags,~(1<<ZFL_N)
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_sthl: ;store hl to mem loc in opl
;ToDo: check flags
mov adrl,opl
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_rmem16:
mov adrl,opl
mov adrh,oph
mov oph,temp
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_rmem8:
mov adrl,opl
mov adrh,oph
mov opl,temp
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_da:
;DAA -> todo
rcall do_op_inv
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_scf:
ori z_flags,(1<<ZFL_C)
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ccf:
ldi temp,(1<<ZFL_C)
eor z_flags,temp
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_cpl:
com opl
ori z_flags,(1<<ZFL_N)|(1<<ZFL_H)
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_push16:
ldi temp,1
ldi temp2,0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_pop16:
mov adrl,z_spl
mov adrh,z_sph
.endif
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_exhl:
mov temp,z_h
mov z_h,oph
mov opl,temp
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_di:
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ei:
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifnz:
- sbrs z_flags,ZFL_Z
- ret
- ldi insdech,0
- ldi insdecl,0
+ sbrs z_flags, ZFL_Z
+ ret
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifz:
- sbrc z_flags,ZFL_Z
- ret
- ldi insdech,0
- ldi insdecl,0
+ sbrc z_flags, ZFL_Z
+ ret
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifnc:
- sbrs z_flags,ZFL_C
- ret
- ldi insdech,0
- ldi insdecl,0
+ sbrs z_flags, ZFL_C
+ ret
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifc:
- sbrc z_flags,ZFL_C
- ret
- ldi insdech,0
- ldi insdecl,0
+ sbrc z_flags, ZFL_C
+ ret
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifpo:
rcall do_op_calcparity
- sbrs temp2,0
- ret
- ldi insdech,0
- ldi insdecl,0
+ sbrs temp2, 0
+ ret
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifpe:
rcall do_op_calcparity
- sbrc temp2,0
- ret
- ldi insdech,0
- ldi insdecl,0
+ sbrc temp2, 0
+ ret
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifp: ;sign positive, aka s=0
- sbrs z_flags,ZFL_S
+ sbrs z_flags, ZFL_S
ret
ldi insdech,0
ldi insdecl,0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_ifm: ;sign negative, aka s=1
- sbrc z_flags,ZFL_S
+ sbrc z_flags, ZFL_S
ret
- ldi insdech,0
- ldi insdecl,0
+ ldi insdech, 0
+ ldi insdecl, 0
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
;Interface with peripherials goes here :)
do_op_outa: ; out (opl),a
.if PORT_DEBUG
rcall portWrite
ret
+;----------------------------------------------------------------\r
+;|Mnemonic |SZHPNC|Description |Notes |\r
+;----------------------------------------------------------------\r
+;\r
+; Not yet checked\r
do_op_in: ; in a,(opl)
.if PORT_DEBUG
rcall printstr
.endif
ret
+;----------------------------------------------------------------\r
do_op_calcparity:
ldi temp2,1
sbrc parityb,0
andi temp2,1
ret
+;----------------------------------------------------------------\r
do_op_inv:
rcall printstr
- .db "Invalid opcode @ PC=",0
- mov temp,z_pch
+ .db "Invalid opcode @ PC=",0,0
+ mov temp,z_pch
rcall printhex
- mov temp,z_pcl
+ mov temp,z_pcl
rcall printhex
+\r
+;----------------------------------------------------------------\r
haltinv:
rjmp haltinv
; operation (bit 5-9).
inst_table:
-.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 00 NOP
-.dw (FETCH_DIR16| OP_NOP | STORE_BC ) ; 01 nn nn LD BC,nn
-.dw (FETCH_A | OP_NOP | STORE_MBC ) ; 02 LD (BC),A
-.dw (FETCH_BC | OP_INC16 | STORE_BC ) ; 03 INC BC
-.dw (FETCH_B | OP_INC | STORE_B ) ; 04 INC B
-.dw (FETCH_B | OP_DEC | STORE_B ) ; 05 DEC B
-.dw (FETCH_DIR8 | OP_NOP | STORE_B ) ; 06 nn LD B,n
-.dw (FETCH_A | OP_RLC | STORE_A ) ; 07 RLCA
-.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 08 EX AF,AF' (Z80)
-.dw (FETCH_BC | OP_ADDHL | STORE_HL ) ; 09 ADD HL,BC
-.dw (FETCH_MBC | OP_NOP | STORE_A ) ; 0A LD A,(BC)
-.dw (FETCH_BC | OP_DEC16 | STORE_BC ) ; 0B DEC BC
-.dw (FETCH_C | OP_INC | STORE_C ) ; 0C INC C
-.dw (FETCH_C | OP_DEC | STORE_C ) ; 0D DEC C
-.dw (FETCH_DIR8 | OP_NOP | STORE_C ) ; 0E nn LD C,n
-.dw (FETCH_A | OP_RRC | STORE_A ) ; 0F RRCA
-.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 10 oo DJNZ o (Z80)
+.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 00 NOP
+.dw (FETCH_DIR16| OP_NOP | STORE_BC ) ; 01 nn nn LD BC,nn
+.dw (FETCH_A | OP_NOP | STORE_MBC ) ; 02 LD (BC),A
+.dw (FETCH_BC | OP_INC16 | STORE_BC ) ; 03 INC BC
+.dw (FETCH_B | OP_INC | STORE_B ) ; 04 INC B
+.dw (FETCH_B | OP_DEC | STORE_B ) ; 05 DEC B
+.dw (FETCH_DIR8 | OP_NOP | STORE_B ) ; 06 nn LD B,n
+.dw (FETCH_A | OP_RLC | STORE_A ) ; 07 RLCA
+.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 08 EX AF,AF' (Z80)
+.dw (FETCH_BC | OP_ADDHL | STORE_HL ) ; 09 ADD HL,BC
+.dw (FETCH_MBC | OP_NOP | STORE_A ) ; 0A LD A,(BC)
+.dw (FETCH_BC | OP_DEC16 | STORE_BC ) ; 0B DEC BC
+.dw (FETCH_C | OP_INC | STORE_C ) ; 0C INC C
+.dw (FETCH_C | OP_DEC | STORE_C ) ; 0D DEC C
+.dw (FETCH_DIR8 | OP_NOP | STORE_C ) ; 0E nn LD C,n
+.dw (FETCH_A | OP_RRC | STORE_A ) ; 0F RRCA
+.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 10 oo DJNZ o (Z80)
.dw (FETCH_DIR16| OP_NOP | STORE_DE ) ; 11 nn nn LD DE,nn
-.dw (FETCH_A | OP_NOP | STORE_MDE) ; 12 LD (DE),A
+.dw (FETCH_A | OP_NOP | STORE_MDE) ; 12 LD (DE),A
.dw (FETCH_DE | OP_INC16 | STORE_DE ) ; 13 INC DE
.dw (FETCH_D | OP_INC | STORE_D ) ; 14 INC D
.dw (FETCH_D | OP_DEC | STORE_D ) ; 15 DEC D
.dw (FETCH_DIR8 | OP_NOP | STORE_D ) ; 16 nn LD D,n
-.dw (FETCH_A | OP_RL | STORE_A ) ; 17 RLA
+.dw (FETCH_A | OP_RL | STORE_A ) ; 17 RLA
.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 18 oo JR o (Z80)
.dw (FETCH_DE | OP_ADDHL | STORE_HL ) ; 19 ADD HL,DE
.dw (FETCH_MDE | OP_NOP | STORE_A ) ; 1A LD A,(DE)
.dw (FETCH_E | OP_INC | STORE_E ) ; 1C INC E
.dw (FETCH_E | OP_DEC | STORE_E ) ; 1D DEC E
.dw (FETCH_DIR8 | OP_NOP | STORE_E ) ; 1E nn LD E,n
-.dw (FETCH_A | OP_RR | STORE_A ) ; 1F RRA
+.dw (FETCH_A | OP_RR | STORE_A ) ; 1F RRA
.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 20 oo JR NZ,o (Z80)
.dw (FETCH_DIR16| OP_NOP | STORE_HL ) ; 21 nn nn LD HL,nn
.dw (FETCH_DIR16| OP_STHL | STORE_NOP) ; 22 nn nn LD (nn),HL
.dw (FETCH_H | OP_INC | STORE_H ) ; 24 INC H
.dw (FETCH_H | OP_DEC | STORE_H ) ; 25 DEC H
.dw (FETCH_DIR8 | OP_NOP | STORE_H ) ; 26 nn LD H,n
-.dw (FETCH_A | OP_DA | STORE_A ) ; 27 DAA
+.dw (FETCH_A | OP_DA | STORE_A ) ; 27 DAA
.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 28 oo JR Z,o (Z80)
.dw (FETCH_HL | OP_ADDHL | STORE_HL ) ; 29 ADD HL,HL
.dw (FETCH_DIR16| OP_RMEM16 | STORE_HL ) ; 2A nn nn LD HL,(nn)
.dw (FETCH_L | OP_INC | STORE_L ) ; 2C INC L
.dw (FETCH_L | OP_DEC | STORE_L ) ; 2D DEC L
.dw (FETCH_DIR8 | OP_NOP | STORE_L ) ; 2E nn LD L,n
-.dw (FETCH_A | OP_CPL | STORE_A ) ; 2F CPL
+.dw (FETCH_A | OP_CPL | STORE_A ) ; 2F CPL
.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 30 oo JR NC,o (Z80)
.dw (FETCH_DIR16| OP_NOP | STORE_SP ) ; 31 nn nn LD SP,nn
.dw (FETCH_DIR16| OP_NOP | STORE_AM ) ; 32 nn nn LD (nn),A
.dw (FETCH_SP | OP_ADDHL | STORE_HL ) ; 39 ADD HL,SP
.dw (FETCH_DIR16| OP_RMEM8 | STORE_A ) ; 3A nn nn LD A,(nn)
.dw (FETCH_SP | OP_DEC16 | STORE_SP ) ; 3B DEC SP
-.dw (FETCH_A | OP_INC | STORE_A ) ; 3C INC A
-.dw (FETCH_A | OP_DEC | STORE_A ) ; 3D DEC A
+.dw (FETCH_A | OP_INC | STORE_A ) ; 3C INC A
+.dw (FETCH_A | OP_DEC | STORE_A ) ; 3D DEC A
.dw (FETCH_DIR8 | OP_NOP | STORE_A ) ; 3E nn LD A,n
.dw (FETCH_NOP | OP_CCF | STORE_NOP) ; 3F CCF (Complement Carry Flag, gvd)
.dw (FETCH_B | OP_NOP | STORE_B ) ; 40 LD B,r
.dw (FETCH_H | OP_NOP | STORE_B ) ; 44 LD B,r
.dw (FETCH_L | OP_NOP | STORE_B ) ; 45 LD B,r
.dw (FETCH_MHL | OP_NOP | STORE_B ) ; 46 LD B,r
-.dw (FETCH_A | OP_NOP | STORE_B ) ; 47 LD B,r
+.dw (FETCH_A | OP_NOP | STORE_B ) ; 47 LD B,r
.dw (FETCH_B | OP_NOP | STORE_C ) ; 48 LD C,r
.dw (FETCH_C | OP_NOP | STORE_C ) ; 49 LD C,r
.dw (FETCH_D | OP_NOP | STORE_C ) ; 4A LD C,r
.dw (FETCH_H | OP_NOP | STORE_C ) ; 4C LD C,r
.dw (FETCH_L | OP_NOP | STORE_C ) ; 4D LD C,r
.dw (FETCH_MHL | OP_NOP | STORE_C ) ; 4E LD C,r
-.dw (FETCH_A | OP_NOP | STORE_C ) ; 4F LD C,r
+.dw (FETCH_A | OP_NOP | STORE_C ) ; 4F LD C,r
.dw (FETCH_B | OP_NOP | STORE_D ) ; 50 LD D,r
.dw (FETCH_C | OP_NOP | STORE_D ) ; 51 LD D,r
.dw (FETCH_D | OP_NOP | STORE_D ) ; 52 LD D,r
.dw (FETCH_H | OP_NOP | STORE_D ) ; 54 LD D,r
.dw (FETCH_L | OP_NOP | STORE_D ) ; 55 LD D,r
.dw (FETCH_MHL | OP_NOP | STORE_D ) ; 56 LD D,r
-.dw (FETCH_A | OP_NOP | STORE_D ) ; 57 LD D,r
+.dw (FETCH_A | OP_NOP | STORE_D ) ; 57 LD D,r
.dw (FETCH_B | OP_NOP | STORE_E ) ; 58 LD E,r
.dw (FETCH_C | OP_NOP | STORE_E ) ; 59 LD E,r
.dw (FETCH_D | OP_NOP | STORE_E ) ; 5A LD E,r
.dw (FETCH_H | OP_NOP | STORE_E ) ; 5C LD E,r
.dw (FETCH_L | OP_NOP | STORE_E ) ; 5D LD E,r
.dw (FETCH_MHL | OP_NOP | STORE_E ) ; 5E LD E,r
-.dw (FETCH_A | OP_NOP | STORE_E ) ; 5F LD E,r
+.dw (FETCH_A | OP_NOP | STORE_E ) ; 5F LD E,r
.dw (FETCH_B | OP_NOP | STORE_H ) ; 60 LD H,r
.dw (FETCH_C | OP_NOP | STORE_H ) ; 61 LD H,r
.dw (FETCH_D | OP_NOP | STORE_H ) ; 62 LD H,r
.dw (FETCH_H | OP_NOP | STORE_H ) ; 64 LD H,r
.dw (FETCH_L | OP_NOP | STORE_H ) ; 65 LD H,r
.dw (FETCH_MHL | OP_NOP | STORE_H ) ; 66 LD H,r
-.dw (FETCH_A | OP_NOP | STORE_H ) ; 67 LD H,r
+.dw (FETCH_A | OP_NOP | STORE_H ) ; 67 LD H,r
.dw (FETCH_B | OP_NOP | STORE_L ) ; 68 LD L,r
.dw (FETCH_C | OP_NOP | STORE_L ) ; 69 LD L,r
.dw (FETCH_D | OP_NOP | STORE_L ) ; 6A LD L,r
.dw (FETCH_H | OP_NOP | STORE_L ) ; 6C LD L,r
.dw (FETCH_L | OP_NOP | STORE_L ) ; 6D LD L,r
.dw (FETCH_MHL | OP_NOP | STORE_L ) ; 6E LD L,r
-.dw (FETCH_A | OP_NOP | STORE_L ) ; 6F LD L,r
+.dw (FETCH_A | OP_NOP | STORE_L ) ; 6F LD L,r
.dw (FETCH_B | OP_NOP | STORE_MHL) ; 70 LD (HL),r
.dw (FETCH_C | OP_NOP | STORE_MHL) ; 71 LD (HL),r
.dw (FETCH_D | OP_NOP | STORE_MHL) ; 72 LD (HL),r
.dw (FETCH_H | OP_NOP | STORE_MHL) ; 74 LD (HL),r
.dw (FETCH_L | OP_NOP | STORE_MHL) ; 75 LD (HL),r
.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 76 HALT
-.dw (FETCH_A | OP_NOP | STORE_MHL) ; 77 LD (HL),r
+.dw (FETCH_A | OP_NOP | STORE_MHL) ; 77 LD (HL),r
.dw (FETCH_B | OP_NOP | STORE_A ) ; 78 LD A,r
.dw (FETCH_C | OP_NOP | STORE_A ) ; 79 LD A,r
.dw (FETCH_D | OP_NOP | STORE_A ) ; 7A LD A,r
.dw (FETCH_H | OP_NOP | STORE_A ) ; 7C LD A,r
.dw (FETCH_L | OP_NOP | STORE_A ) ; 7D LD A,r
.dw (FETCH_MHL | OP_NOP | STORE_A ) ; 7E LD A,r
-.dw (FETCH_A | OP_NOP | STORE_A ) ; 7F LD A,r
+.dw (FETCH_A | OP_NOP | STORE_A ) ; 7F LD A,r
.dw (FETCH_B | OP_ADDA | STORE_A ) ; 80 ADD A,r
.dw (FETCH_C | OP_ADDA | STORE_A ) ; 81 ADD A,r
.dw (FETCH_D | OP_ADDA | STORE_A ) ; 82 ADD A,r
.dw (FETCH_H | OP_ADDA | STORE_A ) ; 84 ADD A,r
.dw (FETCH_L | OP_ADDA | STORE_A ) ; 85 ADD A,r
.dw (FETCH_MHL | OP_ADDA | STORE_A ) ; 86 ADD A,r
-.dw (FETCH_A | OP_ADDA | STORE_A ) ; 87 ADD A,r
+.dw (FETCH_A | OP_ADDA | STORE_A ) ; 87 ADD A,r
.dw (FETCH_B | OP_ADCA | STORE_A ) ; 88 ADC A,r
.dw (FETCH_C | OP_ADCA | STORE_A ) ; 89 ADC A,r
.dw (FETCH_D | OP_ADCA | STORE_A ) ; 8A ADC A,r
.dw (FETCH_H | OP_ADCA | STORE_A ) ; 8C ADC A,r
.dw (FETCH_L | OP_ADCA | STORE_A ) ; 8D ADC A,r
.dw (FETCH_MHL | OP_ADCA | STORE_A ) ; 8E ADC A,r
-.dw (FETCH_A | OP_ADCA | STORE_A ) ; 8F ADC A,r
+.dw (FETCH_A | OP_ADCA | STORE_A ) ; 8F ADC A,r
.dw (FETCH_B | OP_SUBFA | STORE_A ) ; 90 SUB A,r
.dw (FETCH_C | OP_SUBFA | STORE_A ) ; 91 SUB A,r
.dw (FETCH_D | OP_SUBFA | STORE_A ) ; 92 SUB A,r
.dw (FETCH_H | OP_SUBFA | STORE_A ) ; 94 SUB A,r
.dw (FETCH_L | OP_SUBFA | STORE_A ) ; 95 SUB A,r
.dw (FETCH_MHL | OP_SUBFA | STORE_A ) ; 96 SUB A,r
-.dw (FETCH_A | OP_SUBFA | STORE_A ) ; 97 SUB A,r
+.dw (FETCH_A | OP_SUBFA | STORE_A ) ; 97 SUB A,r
.dw (FETCH_B | OP_SBCFA | STORE_A ) ; 98 SBC A,r
.dw (FETCH_C | OP_SBCFA | STORE_A ) ; 99 SBC A,r
.dw (FETCH_D | OP_SBCFA | STORE_A ) ; 9A SBC A,r
.dw (FETCH_H | OP_SBCFA | STORE_A ) ; 9C SBC A,r
.dw (FETCH_L | OP_SBCFA | STORE_A ) ; 9D SBC A,r
.dw (FETCH_MHL | OP_SBCFA | STORE_A ) ; 9E SBC A,r
-.dw (FETCH_A | OP_SBCFA | STORE_A ) ; 9F SBC A,r
+.dw (FETCH_A | OP_SBCFA | STORE_A ) ; 9F SBC A,r
.dw (FETCH_B | OP_ANDA | STORE_A ) ; A0 AND A,r
.dw (FETCH_C | OP_ANDA | STORE_A ) ; A1 AND A,r
.dw (FETCH_D | OP_ANDA | STORE_A ) ; A2 AND A,r
.dw (FETCH_H | OP_ANDA | STORE_A ) ; A4 AND A,r
.dw (FETCH_L | OP_ANDA | STORE_A ) ; A5 AND A,r
.dw (FETCH_MHL | OP_ANDA | STORE_A ) ; A6 AND A,r
-.dw (FETCH_A | OP_ANDA | STORE_A ) ; A7 AND A,r
+.dw (FETCH_A | OP_ANDA | STORE_A ) ; A7 AND A,r
.dw (FETCH_B | OP_XORA | STORE_A ) ; A8 XOR A,r
.dw (FETCH_C | OP_XORA | STORE_A ) ; A9 XOR A,r
.dw (FETCH_D | OP_XORA | STORE_A ) ; AA XOR A,r
.dw (FETCH_H | OP_XORA | STORE_A ) ; AC XOR A,r
.dw (FETCH_L | OP_XORA | STORE_A ) ; AD XOR A,r
.dw (FETCH_MHL | OP_XORA | STORE_A ) ; AE XOR A,r
-.dw (FETCH_A | OP_XORA | STORE_A ) ; AF XOR A,r
+.dw (FETCH_A | OP_XORA | STORE_A ) ; AF XOR A,r
.dw (FETCH_B | OP_ORA | STORE_A ) ; B0 OR A,r
.dw (FETCH_C | OP_ORA | STORE_A ) ; B1 OR A,r
.dw (FETCH_D | OP_ORA | STORE_A ) ; B2 OR A,r
.dw (FETCH_H | OP_ORA | STORE_A ) ; B4 OR A,r
.dw (FETCH_L | OP_ORA | STORE_A ) ; B5 OR A,r
.dw (FETCH_MHL | OP_ORA | STORE_A ) ; B6 OR A,r
-.dw (FETCH_A | OP_ORA | STORE_A ) ; B7 OR A,r
+.dw (FETCH_A | OP_ORA | STORE_A ) ; B7 OR A,r
.dw (FETCH_B | OP_SUBFA | STORE_NOP) ; B8 CP A,r
.dw (FETCH_C | OP_SUBFA | STORE_NOP) ; B9 CP A,r
.dw (FETCH_D | OP_SUBFA | STORE_NOP) ; BA CP A,r
.dw (FETCH_H | OP_SUBFA | STORE_NOP) ; BC CP A,r
.dw (FETCH_L | OP_SUBFA | STORE_NOP) ; BD CP A,r
.dw (FETCH_MHL | OP_SUBFA | STORE_NOP) ; BE CP A,r
-.dw (FETCH_A | OP_SUBFA | STORE_NOP) ; BF CP A,r
+.dw (FETCH_A | OP_SUBFA | STORE_NOP) ; BF CP A,r
.dw (FETCH_NOP | OP_IFNZ | STORE_RET) ; C0 RET NZ
.dw (FETCH_NOP | OP_POP16 | STORE_BC ) ; C1 POP BC
.dw (FETCH_DIR16| OP_IFNZ | STORE_PC ) ; C2 nn nn JP NZ,nn
projects / avrcpm.git / blobdiff