X-Git-Url: http://cloudbase.mooo.com/gitweb/avrcpm.git/blobdiff_plain/22ed98eed278d3a4040c70196ff096328ad25814..21347864605f3d413cc202fc7316064554f60c09:/z80.asm

diff --git a/z80.asm b/z80.asm
index 409cc88..43ad4e0 100644
--- a/z80.asm
+++ b/z80.asm
@@ -59,7 +59,7 @@
 	.equ refr_vect = OC2Aaddr
 #endif
 
-#define DRAM_WORD_ACCESS 0	/* experimental */
+#define DRAM_WORD_ACCESS 1	/* experimental */
 
 #define EM_Z80	0	/* we don't have any z80 instructions yet */
 
@@ -1212,238 +1212,24 @@ resetwait:
 
 ; ------------------ DRAM routines -------------
 
-; TODO: 
-
-#if DRAM_DQ_ORDER == 1
- #define CLASSIC_DRAM 0
-#else
- #define CLASSIC_DRAM 1		/* Change manualy, if you want new hw w/ old sw */
-#endif
-
-
-#if DRAM_DQ_ORDER == 0
- #if CLASSIC_DRAM == 1
-   #error "Old harware can not work with new software!"
- #endif
-#endif
-
-; ****************************************************************************
-
-#if CLASSIC_DRAM
-
-; ********************** DRAM routines from Sprite_tm ************************
-
-;Sends the address in zh:zl to the ram
-dram_setaddr:
-	push temp
-	in temp,portd
-	andi temp,0x17
-	out portd,temp
-	in temp,portb
-	andi temp,0xE0
-	out portb,temp
-	sbrc zl,0
-	 sbi portb,ram_a0
-	sbrc zl,1
-	 sbi portb,ram_a1
-	sbrc zl,2
-	 sbi portb,ram_a2
-	sbrc zl,3
-	 sbi portb,ram_a3
-	sbrc zl,4
-	 sbi portb,ram_a4
-	sbrc zl,5
-	 sbi portd,ram_a5
-	sbrc zl,6
-	 sbi portd,ram_a6
-	sbrc zl,7
-	 sbi portd,ram_a7
-	sbrc zh,0
-	 sbi portd,ram_a8
-	pop temp
-	ret
-
-dram_getnibble:
-	andi temp,0xf0
-	sbic pinc,ram_d0
-	 ori temp,0x1
-	sbic pinc,ram_d1
-	 ori temp,0x2
-	sbic pinc,ram_d2
-	 ori temp,0x4
-	sbic pinc,ram_d3
-	 ori temp,0x8
-	ret
-
-dram_sendnibble:
-	push temp2
-	in temp2,portc
-	andi temp2,~RAM_DQ_MASK
-
-	sbrc temp,0
-	 ori temp2,(1<<ram_d0)
-	sbrc temp,1
-	 ori temp2,(1<<ram_d1)
-	sbrc temp,2
-	 ori temp2,(1<<ram_d2)
-	sbrc temp,3
-	 ori temp2,(1<<ram_d3)
-
-	out portc,temp2
-	pop temp2
-	ret
-
-
-;Loads the byte on address adrh:adrl into temp.
-dram_read:
-	cli
-	mov zl,adrh
-	ldi zh,0
-	mov temp2,adrl
-	lsl temp2
-	rol zl
-	rol zh
-	;z=addr[15-7]
-	rcall dram_setaddr
-	cbi portb,ram_ras
-
-	ldi zh,0
-	mov zl,adrl
-	andi zl,0x7F
-	rcall dram_setaddr
-	nop
-	cbi portc,ram_cas
-	nop
-	nop
-	cbi portd,ram_oe
-	nop
-	rcall dram_getnibble	
-	sbi portd,ram_oe
-	swap temp
-	sbi portc,ram_cas
-
-	ldi zh,0
-	mov zl,adrl
-	ori zl,0x80
-	rcall dram_setaddr
-	nop
-	cbi portc,ram_cas
-	nop
-	cbi portd,ram_oe
-	nop
-	nop
-	rcall dram_getnibble	
-
-	sbi portd,ram_oe
-	sbi portc,ram_cas
-	sbi portb,ram_ras
-	sei
-	ret
-
-;Writes the byte in temp to  adrh:adrl
-dram_write:
-	cli
-
-	in temp2,ddrc
-	ori temp2,RAM_DQ_MASK
-	out ddrc,temp2
-
-	rcall dram_sendnibble
-
-	mov zl,adrh
-	ldi zh,0
-	mov temp2,adrl
-	lsl temp2
-	rol zl
-	rol zh
-	;z=addr[15-7]
-	rcall dram_setaddr
-	nop
-	nop
-	cbi portb,ram_ras
-
-	ldi zh,0
-	mov zl,adrl
-	ori zl,0x80
-	rcall dram_setaddr
-	nop
-	nop
-	cbi portc,ram_cas
-	nop
-	nop
-	cbi portc,ram_w
-	nop
-	nop
-	nop
-	sbi portc,ram_w
-	sbi portc,ram_cas
-
-
-	ldi zh,0
-	mov zl,adrl
-	andi zl,0x7F
-	rcall dram_setaddr
-	swap temp
-	rcall dram_sendnibble
-	cbi portc,ram_cas
-	nop
-	nop
-	cbi portc,ram_w
-	nop
-	nop
-	sbi portc,ram_w
-	nop
-	nop
-	sbi portc,ram_cas
-	sbi portb,ram_ras
-
-	in temp,ddrc
-	andi temp,~RAM_DQ_MASK
-	out ddrc,temp
-	in temp,portc
-	andi temp,~RAM_DQ_MASK
-	out portc,temp
-	sei
-	ret
-#endif  /* CLASSIC_DRAM == 1 */
-
-; ****************************************************************************
-
-#if ! CLASSIC_DRAM
-
-; ***************************** New DRAM routines ****************************
-
-;todo: see below
+; DRAM_SETADDR val, low_and_mask, low_or_mask, high_and_mask, high_or_mask
 .macro DRAM_SETADDR
-#if 1
-	in temp,P_AL
-	andi temp,~RAM_AL_MASK
-	sbrc @0,0
-	 ori temp,(1<<ram_a0)
-	sbrc @0,1
-	 ori temp,(1<<ram_a1)
-	sbrc @0,2
-	 ori temp,(1<<ram_a2)
-	sbrc @0,3
-	 ori temp,(1<<ram_a3)
-	sbrc @0,4
-	 ori temp,(1<<ram_a4)
+	mov temp,@0
+.if low(@1) != 0xff
+	andi temp,@1
+.endif
+.if  low(@2) != 0
+	ori temp, @2
+.endif
 	out P_AL,temp
-#else
-	out PORTB,@0
-#endif
-
-	in temp,P_AH
-	andi temp,~RAM_AH_MASK
-	sbrc @0,5
-	 ori temp,(1<<ram_a5)
-	sbrc @0,6
-	 ori temp,(1<<ram_a6)
-	sbrc @0,7
-	 ori temp,(1<<ram_a7)
+	
+	mov temp,@0
+.if low(@3) != 0xff
+	andi temp,@3
+.endif
+	ori temp, @4 | (1<<mmc_cs)
 	out P_AH,temp
 .endm
-	ret
 
 
 ;Loads the byte on address adrh:adrl into temp.
@@ -1451,26 +1237,20 @@ dram_write:
 
 dram_read:
 	cli
-	cbi P_A8,ram_a8
-	DRAM_SETADDR adrh
+	DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8), (1<<ram_oe)
 	cbi P_RAS,ram_ras
-
-	DRAM_SETADDR adrl
+	DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
 	cbi P_CAS,ram_cas
-	cbi P_OE,ram_oe
-	nop
-	nop
+	cbi P_A8,ram_a8
 	in  temp,P_DQ-2		; PIN
 	sbi P_CAS,ram_cas
 
-	sbi P_A8,ram_a8
 	cbi P_CAS,ram_cas
 	andi temp,0x0f
 	swap temp
 	in  temp2,P_DQ-2	; PIN
 	andi temp2,0x0f
 	or  temp,temp2
-	swap temp
 
 	sbi P_OE,ram_oe
 	sbi P_CAS,ram_cas
@@ -1478,6 +1258,59 @@ dram_read:
 	sei
 	ret
 
+#if DRAM_WORD_ACCESS
+dram_read_w:
+	cpi adrl,255
+	brne dram_read_w1
+	
+	rcall dram_read
+	push temp
+	adiw adrl,1
+	rcall dram_read
+	mov temp2,temp
+	pop temp
+	ret	
+
+dram_read_w1:
+	cli
+	DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
+	cbi P_RAS,ram_ras
+	DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
+	cbi P_CAS,ram_cas
+	cbi P_A8,ram_a8
+	in  temp,P_DQ-2		; PIN
+	sbi P_CAS,ram_cas
+	cbi P_CAS,ram_cas
+	andi temp,0x0f
+	swap temp
+	in  temp2,P_DQ-2	; PIN
+	sbi P_CAS,ram_cas
+	andi temp2,0x0f
+	or  temp,temp2
+	
+;	push temp
+	mov _wl,temp
+	inc adrl
+	DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
+	cbi P_CAS,ram_cas
+	cbi P_A8,ram_a8
+	in  temp,P_DQ-2		; PIN
+	sbi P_CAS,ram_cas
+	cbi P_CAS,ram_cas
+	andi temp,0x0f
+	swap temp
+	in  temp2,P_DQ-2	; PIN
+	sbi P_CAS,ram_cas
+	andi temp2,0x0f
+	or  temp2,temp
+;	pop temp
+	mov temp,_wl
+
+	sbi P_OE,ram_oe
+	sbi P_RAS,ram_ras
+	sei
+	ret
+#endif
 
 ;Writes the byte in temp to  adrh:adrl
 ;must not alter adrh:adrl
@@ -1492,10 +1325,9 @@ dram_write:
 	ori temp,(1<<ram_cas)
 	out PORTC,temp
 
-	cbi PORTD,ram_a8
-	DRAM_SETADDR adrh
+	DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
 	cbi P_RAS,ram_ras
-	DRAM_SETADDR adrl
+	DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
 	cbi PORTC,ram_cas
 	sbi PORTC,ram_cas
 
@@ -1515,7 +1347,72 @@ dram_write:
 	sei
 	ret
 
-#endif  /* CLASSIC_DRAM == 0 */
+#if DRAM_WORD_ACCESS
+dram_write_w:
+	cpi adrl,255
+	brne dram_write_w1
+	
+	push temp2
+	rcall dram_write
+	pop temp
+	adiw adrl,1
+	rcall dram_write
+	ret	
+
+dram_write_w1:
+	cli
+	push temp2
+	ldi temp2,RAM_DQ_MASK | (1<<ram_w) | (1<<ram_cas)
+	out DDRC,temp2
+
+	mov  temp2,temp
+	andi temp,RAM_DQ_MASK & ~(1<<ram_w)
+	ori temp,(1<<ram_cas)
+	out PORTC,temp
+
+	DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
+	cbi P_RAS,ram_ras
+	DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
+	cbi PORTC,ram_cas
+	sbi PORTC,ram_cas
+
+	sbi PORTD,ram_a8
+	swap temp2
+
+	andi temp2,RAM_DQ_MASK & ~(1<<ram_w)
+	ori temp2,(1<<ram_cas)
+	out PORTC,temp2
+
+	cbi PORTC,ram_cas
+	sbi PORTC,ram_cas
+
+	pop temp
+	inc adrl
+	mov  temp2,temp
+	andi temp,RAM_DQ_MASK & ~(1<<ram_w)
+	ori temp,(1<<ram_cas)
+	out PORTC,temp
+
+	DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
+	cbi PORTC,ram_cas
+	sbi PORTC,ram_cas
+
+	sbi PORTD,ram_a8
+	swap temp2
+
+	andi temp2,RAM_DQ_MASK & ~(1<<ram_w)
+	ori temp2,(1<<ram_cas)
+	out PORTC,temp2
+	cbi PORTC,ram_cas
+
+	sbi P_RAS,ram_ras
+
+	ldi temp,~RAM_DQ_MASK | (1<<ram_w) | (1<<ram_cas)
+	out DDRC,temp
+	out PORTC,temp
+	sei
+	ret
+#endif
 
 ; ****************************************************************************