X-Git-Url: http://cloudbase.mooo.com/gitweb/avrcpm.git/blobdiff_plain/24fb3c9d88450abc11093647829582c544ec08a2..21347864605f3d413cc202fc7316064554f60c09:/z80.asm
diff --git a/z80.asm b/z80.asm
old mode 100755
new mode 100644
index 32b902f..43ad4e0
--- a/z80.asm
+++ b/z80.asm
@@ -16,7 +16,7 @@
; You should have received a copy of the GNU General Public License
; along with this program. If not, see .
-.nolist
+;.nolist
#if defined atmega8
.include "m8def.inc"
#elif defined atmega168
@@ -27,7 +27,6 @@
;FUSE_L=0xF7
#endif
.list
-
.listmac
#ifndef DRAM_DQ_ORDER /* If this is set to 1, the portbits */
@@ -60,6 +59,7 @@
.equ refr_vect = OC2Aaddr
#endif
+#define DRAM_WORD_ACCESS 1 /* experimental */
#define EM_Z80 0 /* we don't have any z80 instructions yet */
@@ -84,10 +84,14 @@
.equ ram_a5 = 5
.equ ram_a6 = 6
.equ ram_a7 = 7
-.equ P_OE = PORTD
-.equ RAM_AH_MASK = 0xE0 ; ram_a[7..5]
-.equ PD_OUTPUT_MASK = 0xFE
+.equ P_OE = PORTD
+.equ P_AH = PORTD
+.equ P_A8 = PORTD
+.equ P_MMC_CS = PORTD
+ ; ram_a[7..5]
+.equ RAM_AH_MASK = (1< 0xFF
+ ;the first answer must be 0x01 (Idle-Mode)
cpi temp,0
- breq mmcInitOcrLoopDone
+ breq mmcInitOcrLoopDone ;second answer is 0x00 (Idle-Mode leave) CMD1 is OK
- sbi PORTD,mmc_cs
- rcall mmcByteNoSend
+ sbi P_MMC_CS,mmc_cs ;disable /CS
+
+; rcall mmcByteNoSend ;unnecessary
+
+ ldi temp,10
+ rcall delay_ms
pop temp2
dec temp2
cpi temp2,0
- brne mmcInitOcrLoop
+ brne mmcInitOcrLoop ;repeat
- ldi temp,4
+ ldi temp2,4
rjmp mmcWaitErr
mmcInitOcrLoopDone:
pop temp2
- sbi PORTD,mmc_cs
+ sbi P_MMC_CS,mmc_cs ;disable /CS
rcall mmcByteNoSend
- ldi temp,0
- out SPCR,temp
+ out SPCR,_0
ret
@@ -1087,7 +1076,7 @@ mmcReadSect:
ldi temp,0x50
out SPCR,temp
- cbi PORTD,mmc_cs
+ cbi P_MMC_CS,mmc_cs
rcall mmcByteNoSend
ldi temp,0x51 ;cmd (read sector)
rcall mmcByte
@@ -1130,11 +1119,10 @@ mmcreadloop:
rcall mmcByteNoSend
rcall mmcByteNoSend
- sbi PORTD,mmc_cs
+ sbi P_MMC_CS,mmc_cs
rcall mmcByteNoSend
- ldi temp,0
- out SPCR,temp
+ out SPCR,_0
ret
@@ -1144,7 +1132,7 @@ mmcWriteSect:
ldi temp,0x50
out SPCR,temp
- cbi PORTD,mmc_cs
+ cbi P_MMC_CS,mmc_cs
rcall mmcByteNoSend
ldi temp,0x58 ;cmd (write sector)
@@ -1197,11 +1185,10 @@ mmcwaitwritten:
cpi temp,0xff
brne mmcwaitwritten
- sbi PORTD,mmc_cs
+ sbi P_MMC_CS,mmc_cs
rcall mmcByteNoSend
- ldi temp,0
- out SPCR,temp
+ out SPCR,_0
ret
@@ -1225,449 +1212,207 @@ resetwait:
; ------------------ DRAM routines -------------
-; TODO:
-
-#if DRAM_DQ_ORDER == 1
- #define CLASSIC_DRAM 0
-#else
- #define CLASSIC_DRAM 1 /* Change manualy, if you want new hw w/ old sw */
-#endif
-
-
-#if DRAM_DQ_ORDER == 0
- #if CLASSIC_DRAM == 1
- #error "Old harware can not work with new software!"
- #endif
-#endif
-
-; ****************************************************************************
-
-#if CLASSIC_DRAM
-
-; ********************** DRAM routines from Sprite_tm ************************
-
-;Sends the address in zh:zl to the ram
-dram_setaddr:
- push temp
- in temp,portd
- andi temp,0x17
- out portd,temp
- in temp,portb
- andi temp,0xE0
- out portb,temp
- sbrc zl,0
- sbi portb,ram_a0
- sbrc zl,1
- sbi portb,ram_a1
- sbrc zl,2
- sbi portb,ram_a2
- sbrc zl,3
- sbi portb,ram_a3
- sbrc zl,4
- sbi portb,ram_a4
- sbrc zl,5
- sbi portd,ram_a5
- sbrc zl,6
- sbi portd,ram_a6
- sbrc zl,7
- sbi portd,ram_a7
- sbrc zh,0
- sbi portd,ram_a8
- pop temp
- ret
-
-dram_getnibble:
- andi temp,0xf0
- sbic pinc,ram_d0
- ori temp,0x1
- sbic pinc,ram_d1
- ori temp,0x2
- sbic pinc,ram_d2
- ori temp,0x4
- sbic pinc,ram_d3
- ori temp,0x8
- ret
-
-dram_sendnibble:
- push temp2
- in temp2,portc
- andi temp2,~RAM_DQ_MASK
-
- sbrc temp,0
- ori temp2,(1< |Rotate left/right |
+;| [ ] |Indirect addressing |
+;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|
+;| { } |Combination of operands |
+;| # |Also BC=BC-1,DE=DE-1 |
+;| ## |Only lower 4 bits of accumulator A used |
+;----------------------------------------------------------------
.equ AVR_T = 6
@@ -2784,11 +2585,8 @@ opjumps:
; (6 words, 8 cycles)
.macro ldpmx
- ldi zl,low (@1*2)
- ldi zh,high(@1*2)
- add zl,@2
- brcc PC+2
- inc zh
+ ldi zh,high(@1*2) ; table must be page aligned
+ mov zl,@2
lpm @0,z
.endm
@@ -2894,10 +2692,7 @@ do_op_dec:
;
;
do_op_inc16:
- inc opl
- brne op_i16x
- inc oph
-op_i16x:
+ adiw opl,1
ret
;----------------------------------------------------------------
@@ -3133,20 +2928,18 @@ do_op_addhl:
;
;
do_op_sthl: ;store hl to mem loc in opl:h
- mov adrl,opl
- mov adrh,oph
+ movw adrl,opl
+#if DRAM_WORD_ACCESS
+ mov temp,z_l
+ mov temp2,z_h
+ rcall memWriteWord
+#else
mov temp,z_l
rcall memWriteByte
-
- inc opl
- brne op_sthlx
- inc oph
-op_sthlx:
- mov adrl,opl
- mov adrh,oph
+ adiw adrl,1
mov temp,z_h
rcall memWriteByte
-
+#endif
ret
;----------------------------------------------------------------
@@ -3156,16 +2949,17 @@ op_sthlx:
;
;
do_op_rmem16:
- mov adrl,opl
- mov adrh,oph
+ movw adrl,opl
+#if DRAM_WORD_ACCESS
+ rcall memReadWord
+ movw opl,temp
+#else
rcall memReadByte
mov opl,temp
- ldi temp,1
- add adrl,temp
- ldi temp,0
- adc adrh,temp
+ adiw adrl,1
rcall memReadByte
mov oph,temp
+#endif
ret
;----------------------------------------------------------------
@@ -3175,8 +2969,7 @@ do_op_rmem16:
;
;
do_op_rmem8:
- mov adrl,opl
- mov adrh,oph
+ movw adrl,opl
rcall memReadByte
mov opl,temp
ret
@@ -3361,42 +3154,19 @@ do_op_cpl:
;
;
do_op_push16:
-#if 1
- ldi temp,1
- ldi temp2,0
- sub z_spl,temp
- sbc z_sph,temp2
-
- mov adrl,z_spl
- mov adrh,z_sph
- mov temp,oph
- rcall memWriteByte
-
- ldi temp,1
- ldi temp2,0
- sub z_spl,temp
- sbc z_sph,temp2
-
- mov adrl,z_spl
- mov adrh,z_sph
+ movw adrl,z_spl
+ subi adrl,2
+ sbci adrh,0
+ movw z_spl,adrl
+#if DRAM_WORD_ACCESS
+ movw temp,opl
+ rcall memWriteWord
+#else
mov temp,opl
rcall memWriteByte
-#else
- subi z_spl,1
- sbci z_sph,0
-
- mov adrl,z_spl
- mov adrh,z_sph
+ adiw adrl,1
mov temp,oph
rcall memWriteByte
-
- subi z_spl,1
- sbci z_sph,0
-
- mov adrl,z_spl
- mov adrh,z_sph
- mov temp,opl
- rcall memWriteByte
#endif
.if STACK_DBG
@@ -3426,25 +3196,21 @@ do_op_push16:
;
;
do_op_pop16:
- mov adrl,z_spl
- mov adrh,z_sph
+ movw adrl,z_spl
+#if DRAM_WORD_ACCESS
+ rcall memReadWord
+ movw opl,temp
+#else
rcall memReadByte
mov opl,temp
-
- ldi temp,1
- ldi temp2,0
- add z_spl,temp
- adc z_sph,temp2
-
- mov adrl,z_spl
- mov adrh,z_sph
+ adiw adrl,1
rcall memReadByte
mov oph,temp
+#endif
- ldi temp,1
- ldi temp2,0
+ ldi temp,2
add z_spl,temp
- adc z_sph,temp2
+ adc z_sph,_0
.if STACK_DBG
rcall printstr
@@ -3668,30 +3434,6 @@ do_op_in: ; in a,(opl)
.endif
ret
-;----------------------------------------------------------------
-
-#if 0
-do_op_calcparity:
- ldi temp2,1
- sbrc parityb,0
- inc temp2
- sbrc parityb,1
- inc temp2
- sbrc parityb,2
- inc temp2
- sbrc parityb,3
- inc temp2
- sbrc parityb,4
- inc temp2
- sbrc parityb,5
- inc temp2
- sbrc parityb,6
- inc temp2
- sbrc parityb,7
- inc temp2
- andi temp2,1
- ret
-#endif
;----------------------------------------------------------------
do_op_inv:
@@ -3711,6 +3453,7 @@ haltinv:
; http://z80ex.sourceforge.net/
; The S, Z, 5 and 3 bits and the parity of the lookup value
+.org (PC+255) & 0xff00
sz53p_tab:
.db 0x44,0x00,0x00,0x04,0x00,0x04,0x04,0x00
.db 0x08,0x0c,0x0c,0x08,0x0c,0x08,0x08,0x0c
@@ -3754,27 +3497,28 @@ sz53p_tab:
; the fetch operation (bit 0-4), the processing operation (bit 10-16) and the store
; operation (bit 5-9).
+.org (PC+255) & 0xff00
inst_table:
-.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 00 NOP
-.dw (FETCH_DIR16| OP_NOP | STORE_BC ) ; 01 nn nn LD BC,nn
-.dw (FETCH_A | OP_NOP | STORE_MBC ) ; 02 LD (BC),A
-.dw (FETCH_BC | OP_INC16 | STORE_BC ) ; 03 INC BC
-.dw (FETCH_B | OP_INC | STORE_B ) ; 04 INC B
-.dw (FETCH_B | OP_DEC | STORE_B ) ; 05 DEC B
-.dw (FETCH_DIR8 | OP_NOP | STORE_B ) ; 06 nn LD B,n
-.dw (FETCH_A | OP_RLC | STORE_A ) ; 07 RLCA
-.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 08 EX AF,AF' (Z80)
-.dw (FETCH_BC | OP_ADDHL | STORE_HL ) ; 09 ADD HL,BC
-.dw (FETCH_MBC | OP_NOP | STORE_A ) ; 0A LD A,(BC)
-.dw (FETCH_BC | OP_DEC16 | STORE_BC ) ; 0B DEC BC
-.dw (FETCH_C | OP_INC | STORE_C ) ; 0C INC C
-.dw (FETCH_C | OP_DEC | STORE_C ) ; 0D DEC C
-.dw (FETCH_DIR8 | OP_NOP | STORE_C ) ; 0E nn LD C,n
-.dw (FETCH_A | OP_RRC | STORE_A ) ; 0F RRCA
-.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 10 oo DJNZ o (Z80)
+.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 00 NOP
+.dw (FETCH_DIR16| OP_NOP | STORE_BC ) ; 01 nn nn LD BC,nn
+.dw (FETCH_A | OP_NOP | STORE_MBC) ; 02 LD (BC),A
+.dw (FETCH_BC | OP_INC16 | STORE_BC ) ; 03 INC BC
+.dw (FETCH_B | OP_INC | STORE_B ) ; 04 INC B
+.dw (FETCH_B | OP_DEC | STORE_B ) ; 05 DEC B
+.dw (FETCH_DIR8 | OP_NOP | STORE_B ) ; 06 nn LD B,n
+.dw (FETCH_A | OP_RLC | STORE_A ) ; 07 RLCA
+.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 08 EX AF,AF' (Z80)
+.dw (FETCH_BC | OP_ADDHL | STORE_HL ) ; 09 ADD HL,BC
+.dw (FETCH_MBC | OP_NOP | STORE_A ) ; 0A LD A,(BC)
+.dw (FETCH_BC | OP_DEC16 | STORE_BC ) ; 0B DEC BC
+.dw (FETCH_C | OP_INC | STORE_C ) ; 0C INC C
+.dw (FETCH_C | OP_DEC | STORE_C ) ; 0D DEC C
+.dw (FETCH_DIR8 | OP_NOP | STORE_C ) ; 0E nn LD C,n
+.dw (FETCH_A | OP_RRC | STORE_A ) ; 0F RRCA
+.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 10 oo DJNZ o (Z80)
.dw (FETCH_DIR16| OP_NOP | STORE_DE ) ; 11 nn nn LD DE,nn
.dw (FETCH_A | OP_NOP | STORE_MDE) ; 12 LD (DE),A
-.dw (FETCH_DE | OP_INC16 | STORE_DE ) ; 13 INC DE
+.dw (FETCH_DE | OP_INC16 | STORE_DE ) ; 13 INC DE
.dw (FETCH_D | OP_INC | STORE_D ) ; 14 INC D
.dw (FETCH_D | OP_DEC | STORE_D ) ; 15 DEC D
.dw (FETCH_DIR8 | OP_NOP | STORE_D ) ; 16 nn LD D,n
@@ -3972,7 +3716,7 @@ inst_table:
.dw (FETCH_DIR8 | OP_SUBFA | STORE_A ) ; D6 nn SUB n
.dw (FETCH_RST | OP_NOP | STORE_CALL) ; D7 RST 10H
.dw (FETCH_NOP | OP_IFC | STORE_RET) ; D8 RET C
-.dw (FETCH_NOP | OP_INV | STORE_NOP) ; D9 EXX (Z80)
+.dw (FETCH_NOP | OP_INV | STORE_NOP) ; D9 EXX (Z80)
.dw (FETCH_DIR16| OP_IFC | STORE_PC ) ; DA nn nn JP C,nn
.dw (FETCH_DIR8 | OP_IN | STORE_A ) ; DB nn IN A,(n)
.dw (FETCH_DIR16| OP_IFC | STORE_CALL) ; DC nn nn CALL C,nn