X-Git-Url: http://cloudbase.mooo.com/gitweb/avrcpm.git/blobdiff_plain/cf6e81d85b1f79ff86d856950f3395cc1ff1c488..2217c8551dde4e881d8e25ac7472c7fc1f103092:/avr/config.inc

diff --git a/avr/config.inc b/avr/config.inc
index afc89cc..5f52182 100644
--- a/avr/config.inc
+++ b/avr/config.inc
@@ -23,7 +23,7 @@
 
 
 #define VMAJOR 2		/* Version number */
-#define VMINOR 2
+#define VMINOR 3
 
 #ifndef DRAM_8BIT
   #define DRAM_8BIT 1		/* 1 = 8bit wide DRAM */
@@ -41,6 +41,8 @@
 ;#define RAMSIZE 256*K*4	/* 1 chip 256Kx4 */
 #define  RAMSIZE   4*M*4 * 2	/* 2 chips 4Mx4  */
 
+#define EM_Z80	0		/* Emulate Z80 if true */
+
 #ifndef FAT16_SUPPORT
   #define FAT16_SUPPORT 1	/* Include Support for FAT16 Partitions */
 #endif				/*  which may contain CP/M image files. */ 
@@ -58,8 +60,11 @@
 #define	TXBUFSIZE 128		/* USART transmit buffer size. Must be power of 2 */
 
 
-
-#define EM_Z80	0		/* we don't have any z80 instructions yet */
+#if EM_Z80
+  #define CPUSTR "Z80"
+#else
+  #define CPUSTR "8080"
+#endif
 
 .equ BOOTWAIT      = 1
 .equ MEMTEST       = 1
@@ -78,7 +83,7 @@
 
 #define MMC_SPI2X  1		/* 0 = SPI CLK/4, 1 = SPI CLK/2 */
 
-#define MEMFILL_VAL      0xCB	/* Fill ram with cbs, which will trigger an invalid opcode error. */
+#define MEMFILL_VAL      0x76	/* Fill ram with HALT opcode. */
 #define DBG_TRACE_BOTTOM 0x01	/* Page boundaries for INS_DEBUG and PRINT_PC  */
 #define DBG_TRACE_TOP	 0xdc	/* Trace is off, below bottom page and above top page. */
 
@@ -205,11 +210,12 @@
 .def	z_a	= r9
 ;.def	stx_bitcount  = r9
 ;.def	stx_dr	      = r10
+
 .def	srx_lastedgel = r10
 .def	srx_lastedgeh = r11
-
-.def	insstore= r8	;
+;.def	insstore= r8	;
 ;.def	insop	= r13	;
+
 .def	insdecl	= r12	;
 .def	insdech	= r13	;
 .def	z_spl	= r14
@@ -219,7 +225,7 @@
 .def	temp3	= r18
 .def	temp4	= r19
 .def	z_flags	= r20	;
-			;
+.def	intstat	= r21	; interpreter status / interrupt status
 .def	opl	= r22	;
 .def	oph	= r23	;
 .def	z_pcl	= r24	;
@@ -232,6 +238,9 @@
 ; zh		;r31	;
 
 
+.equ	i_break = 0			;break detected flag
+.equ	i_trace = 1			;cpu interpreter trace flag
+.equ	i_halt  = 2			;executing halt instruction
 
 #if defined __ATmega8__
 .equ	flags	= TWBR
@@ -246,7 +255,9 @@
 	.equ	hostwrt	= 6		;host written flag
 	.equ	rsflag	= 5		;read sector flag
 	.equ	readop	= 4		;1 if read operation
-	.equ	trace	= 0
+
+	.equ	prefixfd = 1		;Opcode prefix DD=0, FD=1
+	.equ	trace	 = 0
 
 ; This is the base z80 port address for clock access
 #define	TIMERPORT   0x40
@@ -259,6 +270,12 @@
 #define printTimerCmd	15
 #define uptimeCmd	16
 
+#define DEBUGPORT   0x4F
+
+#define startTraceCmd 1
+#define stopTraceCmd  0
+
+
 #if defined __ATmega8__
 .equ	RXTXDR0	= UDR
 .equ	UCSR0A	= UCSRA