X-Git-Url: http://cloudbase.mooo.com/gitweb/avrcpm.git/blobdiff_plain/ff2a0cd0d33de48dc9eac4cf4211e30818e52bf3..21347864605f3d413cc202fc7316064554f60c09:/z80.asm diff --git a/z80.asm b/z80.asm old mode 100755 new mode 100644 index 873c922..43ad4e0 --- a/z80.asm +++ b/z80.asm @@ -20,14 +20,14 @@ #if defined atmega8 .include "m8def.inc" #elif defined atmega168 - .include "m8def.inc" + .include "m168def.inc" #else /* default */ .include "m88def.inc" ;FUSE_H=0xDF ;FUSE_L=0xF7 #endif .list - +.listmac #ifndef DRAM_DQ_ORDER /* If this is set to 1, the portbits */ #define DRAM_DQ_ORDER 0 /* for DRAM D1 and WE are swapped. */ @@ -59,6 +59,7 @@ .equ refr_vect = OC2Aaddr #endif +#define DRAM_WORD_ACCESS 1 /* experimental */ #define EM_Z80 0 /* we don't have any z80 instructions yet */ @@ -84,8 +85,13 @@ .equ ram_a6 = 6 .equ ram_a7 = 7 -.equ RAM_AH_MASK = 0xE0 ; ram_a[7..5] -.equ PD_OUTPUT_MASK = 0xFE +.equ P_OE = PORTD +.equ P_AH = PORTD +.equ P_A8 = PORTD +.equ P_MMC_CS = PORTD + ; ram_a[7..5] +.equ RAM_AH_MASK = (1< 0xFF + ;the first answer must be 0x01 (Idle-Mode) cpi temp,0 - breq mmcInitOcrLoopDone + breq mmcInitOcrLoopDone ;second answer is 0x00 (Idle-Mode leave) CMD1 is OK - sbi PORTD,mmc_cs - rcall mmcByteNoSend + sbi P_MMC_CS,mmc_cs ;disable /CS + +; rcall mmcByteNoSend ;unnecessary + + ldi temp,10 + rcall delay_ms pop temp2 dec temp2 cpi temp2,0 - brne mmcInitOcrLoop + brne mmcInitOcrLoop ;repeat - ldi temp,4 + ldi temp2,4 rjmp mmcWaitErr mmcInitOcrLoopDone: pop temp2 - sbi PORTD,mmc_cs + sbi P_MMC_CS,mmc_cs ;disable /CS rcall mmcByteNoSend - ldi temp,0 - out SPCR,temp + out SPCR,_0 ret @@ -1078,7 +1076,7 @@ mmcReadSect: ldi temp,0x50 out SPCR,temp - cbi PORTD,mmc_cs + cbi P_MMC_CS,mmc_cs rcall mmcByteNoSend ldi temp,0x51 ;cmd (read sector) rcall mmcByte @@ -1121,11 +1119,10 @@ mmcreadloop: rcall mmcByteNoSend rcall mmcByteNoSend - sbi PORTD,mmc_cs + sbi P_MMC_CS,mmc_cs rcall mmcByteNoSend - ldi temp,0 - out SPCR,temp + out SPCR,_0 ret @@ -1135,7 +1132,7 @@ mmcWriteSect: ldi temp,0x50 out SPCR,temp - cbi PORTD,mmc_cs + cbi P_MMC_CS,mmc_cs rcall mmcByteNoSend ldi temp,0x58 ;cmd (write sector) @@ -1188,11 +1185,10 @@ mmcwaitwritten: cpi temp,0xff brne mmcwaitwritten - sbi PORTD,mmc_cs + sbi P_MMC_CS,mmc_cs rcall mmcByteNoSend - ldi temp,0 - out SPCR,temp + out SPCR,_0 ret @@ -1216,463 +1212,237 @@ resetwait: ; ------------------ DRAM routines ------------- -; TODO: - -#if DRAM_DQ_ORDER == 1 - #define CLASSIC_DRAM 0 -#else - #define CLASSIC_DRAM 1 /* Change manualy, if you want new hw w/ old sw */ -#endif - - -#if DRAM_DQ_ORDER == 0 - #if CLASSIC_DRAM == 1 - #error "Old harware can not work with new software!" - #endif -#endif - -; **************************************************************************** - -#if CLASSIC_DRAM - -; ********************** DRAM routines from Sprite_tm ************************ - -;Sends the address in zh:zl to the ram -dram_setaddr: - push temp - in temp,portd - andi temp,0x17 - out portd,temp - in temp,portb - andi temp,0xE0 - out portb,temp - sbrc zl,0 - sbi portb,ram_a0 - sbrc zl,1 - sbi portb,ram_a1 - sbrc zl,2 - sbi portb,ram_a2 - sbrc zl,3 - sbi portb,ram_a3 - sbrc zl,4 - sbi portb,ram_a4 - sbrc zl,5 - sbi portd,ram_a5 - sbrc zl,6 - sbi portd,ram_a6 - sbrc zl,7 - sbi portd,ram_a7 - sbrc zh,0 - sbi portd,ram_a8 - pop temp - ret - -dram_getnibble: - andi temp,0xf0 - sbic pinc,ram_d0 - ori temp,0x1 - sbic pinc,ram_d1 - ori temp,0x2 - sbic pinc,ram_d2 - ori temp,0x4 - sbic pinc,ram_d3 - ori temp,0x8 - ret - -dram_sendnibble: - push temp2 - in temp2,portc - andi temp2,~RAM_DQ_MASK - - sbrc temp,0 - ori temp2,(1< 21 cycles ; **************************************************************************** ; ------------- system timer 10ms --------------- .dseg +delay_timer: + .byte 1 timer_base: timer_ms: .byte 2 @@ -1700,6 +1470,11 @@ sysclockint: push zl push zh + lds zl,delay_timer + subi zl,1 + brcs syscl1 + sts delay_timer,zl +syscl1: lds zl,cnt_1ms lds zh,cnt_1ms+1 adiw z,1 @@ -1711,9 +1486,8 @@ sysclockint: cpc zh,zl brlo syscl_end - ldi zl,0 - sts cnt_1ms,zl - sts cnt_1ms+1,zl + sts cnt_1ms,_0 + sts cnt_1ms+1,_0 lds zl,uptime+0 inc zl @@ -1738,6 +1512,17 @@ syscl_end: pop zl reti +; wait for temp ms + +delay_ms: + sts delay_timer,temp +dly_loop: + lds temp,delay_timer + cpi temp,0 + brne dly_loop + ret + +; clockget: ldi temp,0xFF @@ -1898,7 +1683,7 @@ tp_s: pop temp2 rcall print_ultoa rcall printstr - .db "s. ",0,0 + .db "s.",0,0 pop opl pop oph @@ -1954,11 +1739,11 @@ uptime_print: print_ultoa: push adrh push adrl - push yl + push insdech clr adrl ;adrl = stack level -ultoa1: ldi yl, 32 ;adrh = oph:temp % 10 +ultoa1: ldi insdech, 32 ;adrh = oph:temp % 10 clr adrh ;oph:temp /= 10 ultoa2: lsl temp rol temp2 @@ -1969,25 +1754,31 @@ ultoa2: lsl temp brcs ultoa3 subi adrh,10 inc temp -ultoa3: dec yl +ultoa3: dec insdech brne ultoa2 cpi adrh, 10 ;adrh is a numeral digit '0'-'9' subi adrh, -'0' push adrh ;Stack it inc adrl - ldi yl,0 - cp temp,yl ;Repeat until oph:temp gets zero - cpc temp2,yl - cpc opl,yl - cpc oph,yl + cp temp,_0 ;Repeat until oph:temp gets zero + cpc temp2,_0 + cpc opl,_0 + cpc oph,_0 brne ultoa1 + + ldi temp, '0' +ultoa5: cpi adrl,3 ; at least 3 digits (ms) + brge ultoa6 + push temp + inc adrl + rjmp ultoa5 ultoa6: pop temp ;Flush stacked digits rcall uartputc dec adrl brne ultoa6 - pop yl + pop insdech pop adrl pop adrh ret @@ -2052,6 +1843,10 @@ printstr_end: .equ memReadByte = dram_read .equ memWriteByte = dram_write +#if DRAM_WORD_ACCESS +.equ memReadWord = dram_read_w +.equ memWriteWord = dram_write_w +#endif ; -------------------------------------------------------------- @@ -2084,23 +1879,23 @@ rxint: #else lds temp,UDR0 #endif - lds zh,rxcount - cpi zh,RXBUFSIZE - brsh rxi_ov - inc zh - sts rxcount,zh - - ldi zl,low(rxfifo) - lds zh,rxidx_w - add zl,zh - inc zh - andi zh,RXBUFMASK - sts rxidx_w,zh - ldi zh,high(rxfifo) - brcc PC+2 - inc zh - st z,temp -rxi_ov: + lds zh,rxcount ;if rxcount < RXBUFSIZE + cpi zh,RXBUFSIZE ; (room for at least 1 char?) + brsh rxi_ov ; + inc zh ; + sts rxcount,zh ; rxcount++ + + ldi zl,low(rxfifo) ; + lds zh,rxidx_w ; + add zl,zh ; + inc zh ; + andi zh,RXBUFMASK ; + sts rxidx_w,zh ; rxidx_w = ++rxidx_w % RXBUFSIZE + ldi zh,high(rxfifo) ; + brcc PC+2 ; + inc zh ; + st z,temp ; rxfifo[rxidx_w] = char +rxi_ov: ;endif pop zl pop zh pop temp @@ -2183,26 +1978,26 @@ uartputc_l: ;Jump table for fetch routines. Make sure to keep this in sync with the .equs! fetchjumps: -.dw do_fetch_nop -.dw do_fetch_a -.dw do_fetch_b -.dw do_fetch_c -.dw do_fetch_d -.dw do_fetch_e -.dw do_fetch_h -.dw do_fetch_l -.dw do_fetch_af -.dw do_fetch_bc -.dw do_fetch_de -.dw do_fetch_hl -.dw do_fetch_sp -.dw do_fetch_mbc -.dw do_fetch_mde -.dw do_fetch_mhl -.dw do_fetch_msp -.dw do_fetch_dir8 -.dw do_fetch_dir16 -.dw do_fetch_rst + rjmp do_fetch_nop + rjmp do_fetch_a + rjmp do_fetch_b + rjmp do_fetch_c + rjmp do_fetch_d + rjmp do_fetch_e + rjmp do_fetch_h + rjmp do_fetch_l + rjmp do_fetch_af + rjmp do_fetch_bc + rjmp do_fetch_de + rjmp do_fetch_hl + rjmp do_fetch_sp + rjmp do_fetch_mbc + rjmp do_fetch_mde + rjmp do_fetch_mhl + rjmp do_fetch_msp + rjmp do_fetch_dir8 + rjmp do_fetch_dir16 + rjmp do_fetch_rst do_fetch_nop: ret @@ -2256,8 +2051,7 @@ do_fetch_hl: ret do_fetch_sp: - mov opl,z_spl - mov oph,z_sph + movw opl,z_spl ret do_fetch_mbc: @@ -2282,43 +2076,44 @@ do_fetch_mhl: ret do_fetch_msp: - mov adrh,z_sph - mov adrl,z_spl + movw adrl,z_spl +#if DRAM_WORD_ACCESS + rcall memReadWord + movw opl,temp +#else rcall memReadByte mov opl,temp - ldi temp,1 - ldi temp2,0 - add adrl,temp - adc adrh,temp2 + adiw adrl,1 rcall memReadByte mov oph,temp +#endif ret do_fetch_dir8: - mov adrl,z_pcl - mov adrh,z_pch + movw adrl,z_pcl rcall memReadByte adiw z_pcl,1 mov opl,temp ret do_fetch_dir16: - mov adrl,z_pcl - mov adrh,z_pch + movw adrl,z_pcl +#if DRAM_WORD_ACCESS + rcall memReadWord + movw opl,temp +#else rcall memReadByte mov opl,temp - adiw z_pcl,1 - mov adrl,z_pcl - mov adrh,z_pch + adiw adrl,1 rcall memReadByte - adiw z_pcl,1 mov oph,temp +#endif + adiw z_pcl,2 ret do_fetch_rst: - mov adrl,z_pcl - mov adrh,z_pch + movw adrl,z_pcl subi adrl,1 sbci adrh,0 rcall memReadByte @@ -2355,27 +2150,27 @@ do_fetch_rst: ;Jump table for store routines. Make sure to keep this in sync with the .equs! storejumps: -.dw do_store_nop -.dw do_store_a -.dw do_store_b -.dw do_store_c -.dw do_store_d -.dw do_store_e -.dw do_store_h -.dw do_store_l -.dw do_store_af -.dw do_store_bc -.dw do_store_de -.dw do_store_hl -.dw do_store_sp -.dw do_store_pc -.dw do_store_mbc -.dw do_store_mde -.dw do_store_mhl -.dw do_store_msp -.dw do_store_ret -.dw do_store_call -.dw do_store_am + rjmp do_store_nop + rjmp do_store_a + rjmp do_store_b + rjmp do_store_c + rjmp do_store_d + rjmp do_store_e + rjmp do_store_h + rjmp do_store_l + rjmp do_store_af + rjmp do_store_bc + rjmp do_store_de + rjmp do_store_hl + rjmp do_store_sp + rjmp do_store_pc + rjmp do_store_mbc + rjmp do_store_mde + rjmp do_store_mhl + rjmp do_store_msp + rjmp do_store_ret + rjmp do_store_call + rjmp do_store_am do_store_nop: @@ -2451,49 +2246,43 @@ do_store_mhl: ret do_store_msp: - mov adrh,z_sph - mov adrl,z_spl + movw adrl,z_spl +#if DRAM_WORD_ACCESS + movw temp,opl + rcall memWriteWord +#else mov temp,opl rcall memWriteByte - - ldi temp,1 - ldi temp2,0 - add adrl,temp - adc adrh,temp2 + adiw adrl,1 mov temp,oph rcall memWriteByte - +#endif ret do_store_sp: - mov z_sph,oph - mov z_spl,opl + movw z_spl,opl ret do_store_pc: - mov z_pch,oph - mov z_pcl,opl + movw z_pcl,opl ret do_store_ret: rcall do_op_pop16 - mov z_pcl,opl - mov z_pch,oph + movw z_pcl,opl ret do_store_call: push opl push oph - mov opl,z_pcl - mov oph,z_pch + movw opl,z_pcl rcall do_op_push16 pop z_pch pop z_pcl ret do_store_am: - mov adrh,oph - mov adrl,opl + movw adrl,opl mov temp,z_a rcall memWriteByte ret @@ -2544,46 +2333,46 @@ do_store_am: .equ OP_INV = (39<<10) opjumps: -.dw do_op_nop -.dw do_op_inc -.dw do_op_dec -.dw do_op_inc16 -.dw do_op_dec16 -.dw do_op_rlc -.dw do_op_rrc -.dw do_op_rr -.dw do_op_rl -.dw do_op_adda -.dw do_op_adca -.dw do_op_subfa -.dw do_op_sbcfa -.dw do_op_anda -.dw do_op_ora -.dw do_op_xora -.dw do_op_addhl -.dw do_op_sthl -.dw do_op_rmem16 -.dw do_op_rmem8 -.dw do_op_da -.dw do_op_scf -.dw do_op_cpl -.dw do_op_ccf -.dw do_op_pop16 -.dw do_op_push16 -.dw do_op_ifnz -.dw do_op_ifz -.dw do_op_ifnc -.dw do_op_ifc -.dw do_op_ifpo -.dw do_op_ifpe -.dw do_op_ifp -.dw do_op_ifm -.dw do_op_outa -.dw do_op_in -.dw do_op_exhl -.dw do_op_di -.dw do_op_ei -.dw do_op_inv + rjmp do_op_nop + rjmp do_op_inc + rjmp do_op_dec + rjmp do_op_inc16 + rjmp do_op_dec16 + rjmp do_op_rlc + rjmp do_op_rrc + rjmp do_op_rr + rjmp do_op_rl + rjmp do_op_adda + rjmp do_op_adca + rjmp do_op_subfa + rjmp do_op_sbcfa + rjmp do_op_anda + rjmp do_op_ora + rjmp do_op_xora + rjmp do_op_addhl + rjmp do_op_sthl + rjmp do_op_rmem16 + rjmp do_op_rmem8 + rjmp do_op_da + rjmp do_op_scf + rjmp do_op_cpl + rjmp do_op_ccf + rjmp do_op_pop16 + rjmp do_op_push16 + rjmp do_op_ifnz + rjmp do_op_ifz + rjmp do_op_ifnc + rjmp do_op_ifc + rjmp do_op_ifpo + rjmp do_op_ifpe + rjmp do_op_ifp + rjmp do_op_ifm + rjmp do_op_outa + rjmp do_op_in + rjmp do_op_exhl + rjmp do_op_di + rjmp do_op_ei + rjmp do_op_inv ;How the flags are supposed to work: @@ -2707,6 +2496,66 @@ opjumps: ;|SUB s |***V1*|Subtract |A=A-s | ;|XOR s |**0P00|Logical Exclusive OR |A=Axs | ;|----------+------+--------------------------------------------| +;| F |-*01? |Flag unaffected/affected/reset/set/unknown | +;| S |S |Sign flag (Bit 7) | +;| Z | Z |Zero flag (Bit 6) | +;| HC | H |Half Carry flag (Bit 4) | +;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) | +;| N | N |Add/Subtract flag (Bit 1) | +;| CY | C|Carry flag (Bit 0) | +;|-----------------+--------------------------------------------| +;| n |Immediate addressing | +;| nn |Immediate extended addressing | +;| e |Relative addressing (PC=PC+2+offset) | +;| [nn] |Extended addressing | +;| [xx+d] |Indexed addressing | +;| r |Register addressing | +;| [rr] |Register indirect addressing | +;| |Implied addressing | +;| b |Bit addressing | +;| p |Modified page zero addressing (see RST) | +;|-----------------+--------------------------------------------| +;|DEFB n(,...) |Define Byte(s) | +;|DEFB 'str'(,...) |Define Byte ASCII string(s) | +;|DEFS nn |Define Storage Block | +;|DEFW nn(,...) |Define Word(s) | +;|-----------------+--------------------------------------------| +;| A B C D E |Registers (8-bit) | +;| AF BC DE HL |Register pairs (16-bit) | +;| F |Flag register (8-bit) | +;| I |Interrupt page address register (8-bit) | +;| IX IY |Index registers (16-bit) | +;| PC |Program Counter register (16-bit) | +;| R |Memory Refresh register | +;| SP |Stack Pointer register (16-bit) | +;|-----------------+--------------------------------------------| +;| b |One bit (0 to 7) | +;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) | +;| d |One-byte expression (-128 to +127) | +;| dst |Destination s, ss, [BC], [DE], [HL], [nn] | +;| e |One-byte expression (-126 to +129) | +;| m |Any register r, [HL] or [xx+d] | +;| n |One-byte expression (0 to 255) | +;| nn |Two-byte expression (0 to 65535) | +;| pp |Register pair BC, DE, IX or SP | +;| qq |Register pair AF, BC, DE or HL | +;| qq' |Alternative register pair AF, BC, DE or HL | +;| r |Register A, B, C, D, E, H or L | +;| rr |Register pair BC, DE, IY or SP | +;| s |Any register r, value n, [HL] or [xx+d] | +;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] | +;| ss |Register pair BC, DE, HL or SP | +;| xx |Index register IX or IY | +;|-----------------+--------------------------------------------| +;| + - * / ^ |Add/subtract/multiply/divide/exponent | +;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR | +;| <- -> |Rotate left/right | +;| [ ] |Indirect addressing | +;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement| +;| { } |Combination of operands | +;| # |Also BC=BC-1,DE=DE-1 | +;| ## |Only lower 4 bits of accumulator A used | +;---------------------------------------------------------------- .equ AVR_T = 6 @@ -2736,11 +2585,8 @@ opjumps: ; (6 words, 8 cycles) .macro ldpmx - ldi zl,low (@1*2) - ldi zh,high(@1*2) - add zl,@2 - brcc PC+2 - inc zh + ldi zh,high(@1*2) ; table must be page aligned + mov zl,@2 lpm @0,z .endm @@ -2846,10 +2692,7 @@ do_op_dec: ; ; do_op_inc16: - inc opl - brne op_i16x - inc oph -op_i16x: + adiw opl,1 ret ;---------------------------------------------------------------- @@ -3085,20 +2928,18 @@ do_op_addhl: ; ; do_op_sthl: ;store hl to mem loc in opl:h - mov adrl,opl - mov adrh,oph + movw adrl,opl +#if DRAM_WORD_ACCESS + mov temp,z_l + mov temp2,z_h + rcall memWriteWord +#else mov temp,z_l rcall memWriteByte - - inc opl - brne op_sthlx - inc oph -op_sthlx: - mov adrl,opl - mov adrh,oph + adiw adrl,1 mov temp,z_h rcall memWriteByte - +#endif ret ;---------------------------------------------------------------- @@ -3108,16 +2949,17 @@ op_sthlx: ; ; do_op_rmem16: - mov adrl,opl - mov adrh,oph + movw adrl,opl +#if DRAM_WORD_ACCESS + rcall memReadWord + movw opl,temp +#else rcall memReadByte mov opl,temp - ldi temp,1 - add adrl,temp - ldi temp,0 - adc adrh,temp + adiw adrl,1 rcall memReadByte mov oph,temp +#endif ret ;---------------------------------------------------------------- @@ -3127,8 +2969,7 @@ do_op_rmem16: ; ; do_op_rmem8: - mov adrl,opl - mov adrh,oph + movw adrl,opl rcall memReadByte mov opl,temp ret @@ -3313,42 +3154,19 @@ do_op_cpl: ; ; do_op_push16: -#if 1 - ldi temp,1 - ldi temp2,0 - sub z_spl,temp - sbc z_sph,temp2 - - mov adrl,z_spl - mov adrh,z_sph - mov temp,oph - rcall memWriteByte - - ldi temp,1 - ldi temp2,0 - sub z_spl,temp - sbc z_sph,temp2 - - mov adrl,z_spl - mov adrh,z_sph + movw adrl,z_spl + subi adrl,2 + sbci adrh,0 + movw z_spl,adrl +#if DRAM_WORD_ACCESS + movw temp,opl + rcall memWriteWord +#else mov temp,opl rcall memWriteByte -#else - subi z_spl,1 - sbci z_sph,0 - - mov adrl,z_spl - mov adrh,z_sph + adiw adrl,1 mov temp,oph rcall memWriteByte - - subi z_spl,1 - sbci z_sph,0 - - mov adrl,z_spl - mov adrh,z_sph - mov temp,opl - rcall memWriteByte #endif .if STACK_DBG @@ -3378,25 +3196,21 @@ do_op_push16: ; ; do_op_pop16: - mov adrl,z_spl - mov adrh,z_sph + movw adrl,z_spl +#if DRAM_WORD_ACCESS + rcall memReadWord + movw opl,temp +#else rcall memReadByte mov opl,temp - - ldi temp,1 - ldi temp2,0 - add z_spl,temp - adc z_sph,temp2 - - mov adrl,z_spl - mov adrh,z_sph + adiw adrl,1 rcall memReadByte mov oph,temp +#endif - ldi temp,1 - ldi temp2,0 + ldi temp,2 add z_spl,temp - adc z_sph,temp2 + adc z_sph,_0 .if STACK_DBG rcall printstr @@ -3620,30 +3434,6 @@ do_op_in: ; in a,(opl) .endif ret -;---------------------------------------------------------------- - -#if 0 -do_op_calcparity: - ldi temp2,1 - sbrc parityb,0 - inc temp2 - sbrc parityb,1 - inc temp2 - sbrc parityb,2 - inc temp2 - sbrc parityb,3 - inc temp2 - sbrc parityb,4 - inc temp2 - sbrc parityb,5 - inc temp2 - sbrc parityb,6 - inc temp2 - sbrc parityb,7 - inc temp2 - andi temp2,1 - ret -#endif ;---------------------------------------------------------------- do_op_inv: @@ -3663,6 +3453,7 @@ haltinv: ; http://z80ex.sourceforge.net/ ; The S, Z, 5 and 3 bits and the parity of the lookup value +.org (PC+255) & 0xff00 sz53p_tab: .db 0x44,0x00,0x00,0x04,0x00,0x04,0x04,0x00 .db 0x08,0x0c,0x0c,0x08,0x0c,0x08,0x08,0x0c @@ -3706,27 +3497,28 @@ sz53p_tab: ; the fetch operation (bit 0-4), the processing operation (bit 10-16) and the store ; operation (bit 5-9). +.org (PC+255) & 0xff00 inst_table: -.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 00 NOP -.dw (FETCH_DIR16| OP_NOP | STORE_BC ) ; 01 nn nn LD BC,nn -.dw (FETCH_A | OP_NOP | STORE_MBC ) ; 02 LD (BC),A -.dw (FETCH_BC | OP_INC16 | STORE_BC ) ; 03 INC BC -.dw (FETCH_B | OP_INC | STORE_B ) ; 04 INC B -.dw (FETCH_B | OP_DEC | STORE_B ) ; 05 DEC B -.dw (FETCH_DIR8 | OP_NOP | STORE_B ) ; 06 nn LD B,n -.dw (FETCH_A | OP_RLC | STORE_A ) ; 07 RLCA -.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 08 EX AF,AF' (Z80) -.dw (FETCH_BC | OP_ADDHL | STORE_HL ) ; 09 ADD HL,BC -.dw (FETCH_MBC | OP_NOP | STORE_A ) ; 0A LD A,(BC) -.dw (FETCH_BC | OP_DEC16 | STORE_BC ) ; 0B DEC BC -.dw (FETCH_C | OP_INC | STORE_C ) ; 0C INC C -.dw (FETCH_C | OP_DEC | STORE_C ) ; 0D DEC C -.dw (FETCH_DIR8 | OP_NOP | STORE_C ) ; 0E nn LD C,n -.dw (FETCH_A | OP_RRC | STORE_A ) ; 0F RRCA -.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 10 oo DJNZ o (Z80) +.dw (FETCH_NOP | OP_NOP | STORE_NOP) ; 00 NOP +.dw (FETCH_DIR16| OP_NOP | STORE_BC ) ; 01 nn nn LD BC,nn +.dw (FETCH_A | OP_NOP | STORE_MBC) ; 02 LD (BC),A +.dw (FETCH_BC | OP_INC16 | STORE_BC ) ; 03 INC BC +.dw (FETCH_B | OP_INC | STORE_B ) ; 04 INC B +.dw (FETCH_B | OP_DEC | STORE_B ) ; 05 DEC B +.dw (FETCH_DIR8 | OP_NOP | STORE_B ) ; 06 nn LD B,n +.dw (FETCH_A | OP_RLC | STORE_A ) ; 07 RLCA +.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 08 EX AF,AF' (Z80) +.dw (FETCH_BC | OP_ADDHL | STORE_HL ) ; 09 ADD HL,BC +.dw (FETCH_MBC | OP_NOP | STORE_A ) ; 0A LD A,(BC) +.dw (FETCH_BC | OP_DEC16 | STORE_BC ) ; 0B DEC BC +.dw (FETCH_C | OP_INC | STORE_C ) ; 0C INC C +.dw (FETCH_C | OP_DEC | STORE_C ) ; 0D DEC C +.dw (FETCH_DIR8 | OP_NOP | STORE_C ) ; 0E nn LD C,n +.dw (FETCH_A | OP_RRC | STORE_A ) ; 0F RRCA +.dw (FETCH_NOP | OP_INV | STORE_NOP) ; 10 oo DJNZ o (Z80) .dw (FETCH_DIR16| OP_NOP | STORE_DE ) ; 11 nn nn LD DE,nn .dw (FETCH_A | OP_NOP | STORE_MDE) ; 12 LD (DE),A -.dw (FETCH_DE | OP_INC16 | STORE_DE ) ; 13 INC DE +.dw (FETCH_DE | OP_INC16 | STORE_DE ) ; 13 INC DE .dw (FETCH_D | OP_INC | STORE_D ) ; 14 INC D .dw (FETCH_D | OP_DEC | STORE_D ) ; 15 DEC D .dw (FETCH_DIR8 | OP_NOP | STORE_D ) ; 16 nn LD D,n @@ -3924,7 +3716,7 @@ inst_table: .dw (FETCH_DIR8 | OP_SUBFA | STORE_A ) ; D6 nn SUB n .dw (FETCH_RST | OP_NOP | STORE_CALL) ; D7 RST 10H .dw (FETCH_NOP | OP_IFC | STORE_RET) ; D8 RET C -.dw (FETCH_NOP | OP_INV | STORE_NOP) ; D9 EXX (Z80) +.dw (FETCH_NOP | OP_INV | STORE_NOP) ; D9 EXX (Z80) .dw (FETCH_DIR16| OP_IFC | STORE_PC ) ; DA nn nn JP C,nn .dw (FETCH_DIR8 | OP_IN | STORE_A ) ; DB nn IN A,(n) .dw (FETCH_DIR16| OP_IFC | STORE_CALL) ; DC nn nn CALL C,nn