From: Leo Date: Thu, 21 Mar 2013 09:23:11 +0000 (+0000) Subject: * MMC/SD Bootloader support X-Git-Tag: 3.1~2 X-Git-Url: http://cloudbase.mooo.com/gitweb/avrcpm.git/commitdiff_plain/623dd899f6326f34aaf298fd4f83dbd69d7ef750?ds=sidebyside * MMC/SD Bootloader support - Files: config.inc, avrcpm.asm, Makefile * sw-uart.asm - TX Bugfix: don't miss bit timeout at end of character (OC1 int) * Z80int-jmp.asm - reorganization to reduce flash footprint git-svn-id: svn://cu.loc/avr-cpm/avrcpm/trunk@201 57430480-672e-4586-8877-bcf8adbbf3b7 --- diff --git a/avr/Makefile b/avr/Makefile index efc5b1c..e4802cc 100644 --- a/avr/Makefile +++ b/avr/Makefile @@ -6,12 +6,23 @@ MCU = atmega328P F_CPU = 20000000 #BAUD = 19200 -BAUD = 57600 -#BAUD = 115200 +#BAUD = 57600 +BAUD = 115200 DRAM_8BIT = 1 #I2C = 1 +#MMC/SD bootloader +# undef/comment 'DEVID_S' if not used +DEVID_S = ACPM + +# Version defined in 'config.inc'. +VMAJOR = $(call conf-val, VMAJOR, config.inc) +VMINOR = $(call conf-val, VMINOR, config.inc) + +TESTVERSION = 1 +BOOTLDRSIZE = 2048 #Byte + TARGET = avrcpm ASRC0 = avrcpm.asm @@ -26,14 +37,25 @@ else ASRC0 += dram-4bit.inc dram-4bit.asm hw-uart.asm endif +ASRC = $(ASRC0) svnrev.inc #ASRC := $(ASRC0) svnrev.inc -ASRC := $(ASRC0) svnrev.inc # Place -D or -U options here CDEFS = -DF_CPU=$(F_CPU) -DBAUD=$(BAUD) -D$(MCU) -DDRAM_8BIT=$(DRAM_8BIT) + ifdef I2C CDEFS += -DI2C=$(I2C) endif +ifdef FAT16_SUPPORT + CDEFS += -DFAT16_SUPPORT=$(FAT16_SUPPORT) +endif +ifdef EM_Z80 + CDEFS += -DEM_Z80=$(EM_Z80) +endif +ifdef DEVID_S + CDEFS += -DDEVID_S=\"$(DEVID_S)\" -DBOOTLDRSIZE=$(BOOTLDRSIZE) -DTESTVERSION=$(TESTVERSION) +endif + ASPATH = C:/Programme/Atmel/AVR\ Tools/AvrAssembler2 DEFS = $(ASPATH)/Appnotes @@ -52,6 +74,17 @@ endif AS = $(WINE) $(ASPATH)/avrasm2.exe ASFLAGS = -I $(DEFS) $(CDEFS) +AWK = gawk +OBJCOPY = avr-objcopy +CRCGEN = crcgen + +HEXTOBIN = $(OBJCOPY) -I ihex -O binary --gap-fill 0xff + +#(call conf-val,config-id,config-file) +#conf-val = $(shell awk -vID=$(strip $1) '$$0 ~ "^[ \t]*\#define[ \t]+" ID "[ \t]+" {print $$3}' $2 ) +conf-val = $(shell awk -vID=$(strip $1) '$$1$$2 ~ "\#define"ID {print $$3}' $2) + + # Programming support using avrdude. Settings and variables. AVRDUDE_PROGRAMMER = dragon_isp @@ -82,23 +115,16 @@ AVRDUDE = avrdude REMOVE = rm -f MV = mv -f - -# Define all listing files. -#LST = $(ASRC:.asm=.lst) - -# Combine all necessary flags and optional flags. -# Add target processor to flags. -ALL_ASFLAGS = $(ASFLAGS) - -.PHONY: all hex eep lst map program flash eeprom tags clean +.PHONY: all bin hex eep lst map program flash eeprom tags clean # Default target. all: hex lst -hex: $(TARGET).hex $(ASRC) -eep: $(TARGET).eep $(ASRC) -lst: $(TARGET).lst $(ASRC) -map: $(TARGET).map $(ASRC) +hex: $(TARGET).hex +eep: $(TARGET).eep +lst: $(TARGET).lst +map: $(TARGET).map +bin: $(TARGET)-$(VMAJOR).$(VMINOR).bin # Program the device. @@ -117,25 +143,31 @@ $(TARGET).eep: $(ASRC) $(TARGET).lst: $(ASRC) $(TARGET).map: $(ASRC) -#.SUFFIXES: .hex .eep .lst + .SUFFIXES: +%-$(VMAJOR).$(VMINOR).bin: %.hex + $(HEXTOBIN) $< $@ + $(CRCGEN) $@ + %.hex: %.asm - $(AS) $(ALL_ASFLAGS) -fI -o $@ $< + $(AS) $(ASFLAGS) -fI -o $@ $< %.lst: %.asm - @$(AS) $(ALL_ASFLAGS) -v0 -f- -l $@ $< + @$(AS) $(ASFLAGS) -v0 -f- -l $@ $< %.map: %.asm - $(AS) $(ALL_ASFLAGS) -v0 -f- -m $@ $< + $(AS) $(ASFLAGS) -v0 -f- -m $@ $< tags: $(SRC) $(ASRC) ctags $(SRC) $(ASRC) svnrev.inc: $(ASRC0) - @svnrev -osvnrev.inc $^ + svnrev -osvnrev.inc $^ + touch svnrev.inc # Target: clean project. clean: - $(REMOVE) $(TARGET).hex $(TARGET).eep $(TARGET).obj $(TARGET).map $(TARGET).lst + $(REMOVE) $(TARGET).hex $(TARGET).eep $(TARGET).obj $(TARGET).map $(TARGET).lst \ + $(TARGET)-$(VMAJOR).$(VMINOR).bin diff --git a/avr/Z80int-jmp.asm b/avr/Z80int-jmp.asm index 7b17fa4..e68db28 100644 --- a/avr/Z80int-jmp.asm +++ b/avr/Z80int-jmp.asm @@ -24,12 +24,6 @@ ; $Id$ ; -#if EM_Z80 - #define OPC_TABSTART 0x1B00 -#else - #define OPC_TABSTART 0x1200 -#endif - .dseg z_regs: z_b: .byte 1 @@ -164,33 +158,78 @@ int_nobreak: ;-------------------------------------------------- ; init opcode table ; -; opctable opc_name +; opctable opc_name, pos ; -#if EM_Z80 - .equ numtabs_ = 5 -#else - .equ numtabs_ = 1 -#endif .macro opctable + + .set opcjmp_table_pos_ = (@1 + 255) & -0x100 ;0xff00 + .ifndef opc_tabnext_ - .if OPC_TABSTART & 0x00ff - .error "OPC_TABSTART is not page aligned!" - .endif - .set opc_tabnext_ = OPC_TABSTART - .equ opc_tablow_ = opc_tabnext_ - .equ opc_tabend_ = opc_tablow_ + (256 * numtabs_) + 128 - .equ sz53p_table_pos = opc_tablow_ + (256 * numtabs_) + .set opc_tabnext_ = opcjmp_table_pos_ + + .set opc_tablow_0 = 0 + .set opc_tablen_0 = 0 + .set opc_tablow_1 = 0 + .set opc_tablen_1 = 0 + .endif + + .if opcjmp_table_pos_ < opc_tabnext_ + .set opcjmp_table_pos_ = opc_tabnext_ .endif - .set opcjmp_table_pos_ = opc_tabnext_ - .set opc_tabnext_ = opc_tabnext_ + 256 + .if opc_tablow_0 == 0 + .set opc_tablow_0 = opcjmp_table_pos_ + .set opc_tablen_0 = 256 +;.message "add tab_0" + .elif opc_tablow_1 == 0 + .if (opc_tablow_0 + opc_tablen_0) == opcjmp_table_pos_ + .set opc_tablen_0 = opc_tablen_0 + 256 +;.message " tab_0++" + .else + .set opc_tablow_1 = opcjmp_table_pos_ + .set opc_tablen_1 = 256 +;.message "add tab_1" + .endif + .else + .if (opc_tablow_1 + opc_tablen_1) == opcjmp_table_pos_ + .set opc_tablen_1 = opc_tablen_1 + 256 +;.message "tab_1++" + .else + .error "Tab full_" + .endif + .endif + .set opc_tabnext_ = opcjmp_table_pos_ + 256 .equ @0 = opcjmp_table_pos_ - .set todo_table_pos_ = 0 +.endm +;-------------------------------------------------- +; +; checkspace frompos, size +; +.macro checkspace + + .ifdef opc_tablow_0 + .if @0 <= opc_tablow_0 + .if (@0 + @1) > opc_tablow_0 + .org opc_tablow_0 + opc_tablen_0 +; .message "skip tab, remove tab_0" + .if opc_tablow_1 == 0 + .set opc_tablow_0 = 0 + .set opc_tablen_0 = 0 + .else + .set opc_tablow_0 = opc_tablow_1 + .set opc_tablen_0 = opc_tablen_1 + .set opc_tablow_1 = 0 + .set opc_tablen_1 = 0 +; .message "remove tab_1" + .endif + .endif + .endif + .endif .endm ;-------------------------------------------------- @@ -205,11 +244,16 @@ int_nobreak: .set store_ = (do_@2 != do_store_nop) ; must jump to store action .set cnt_ = fetch_ + op_ + store_ ; number of actions for this instruction - .set action_1_ = 0 - .set action_2_ = 0 - .set action_3_ = 0 - .if cnt_ == 1 + .set done_ = 0 + .set pc_save_ = PC + + .if cnt_ == 0 ; nothing to do (nop) + .org opcjmp_table_pos_ + ret ; go back to main + .org pc_save_ + .set done_ = 1 + .elif cnt_ == 1 ; jump direct to action .if fetch_ .set action_1_ = do_@0 .elif op_ @@ -217,79 +261,38 @@ int_nobreak: .else .set action_1_ = do_@2 .endif - .elif cnt_ == 2 - .if fetch_ - .set action_1_ = do_@0 - .if op_ - .set action_2_ = do_@1 - .else - .set action_2_ = do_@2 - .endif - .else - .set action_1_ = do_@1 - .set action_2_ = do_@2 - .endif - .elif cnt_ == 3 - .set action_1_ = do_@0 - .set action_2_ = do_@1 - .set action_3_ = do_@2 - .endif - - .set longdist_ = 0 - .set pc_save_ = PC - - .org opcjmp_table_pos_ - .set opcjmp_table_pos_ = opcjmp_table_pos_ + 1 - - - .if cnt_ == 0 ; nothing to do (nop) - ret ; go back to main - .elif cnt_ == 1 ; jump direct to action - .if (PC - action_1_) > 2047 - .set longdist_ = 1 ; target action out of reach for rel jump - .else + .if (opcjmp_table_pos_ - action_1_) <= 2047 + .org opcjmp_table_pos_ rjmp action_1_ ; do op and return to main + .org pc_save_ + .set done_ = 1 .endif .endif + .if !done_ - .set done_ = 0 - .if (cnt_ > 1) || longdist_ - ; two or tree actions .if defined (l_@0_@1_@2) - .if (PC - l_@0_@1_@2) <= 2047 - rjmp l_@0_@1_@2 ; generate a jump to action table - .set done_ = 1 - .endif - .endif - .if !done_ - - .if todo_table_pos_ == 0 - .set todo_table_pos_ = opcjmp_table_pos_ - 2048 - .if todo_table_pos_ < pc_save_ - .set todo_table_pos_ = pc_save_ - .endif - .endif - - .if todo_table_pos_ < opc_tablow_ - .if todo_table_pos_ + 2*cnt_ > opc_tablow_ - .set todo_table_pos_ = opc_tabend_ - .endif - .endif - - .if defined (l_@0_@1_@2) - rjmp todo_table_pos_ - .org todo_table_pos_ + .if (opcjmp_table_pos_ - l_@0_@1_@2) <= 2047 + .org opcjmp_table_pos_ + rjmp l_@0_@1_@2 ; generate a jump to action table + .org pc_save_ + .else + checkspace pc_save_, 2 + .set pc_save_ = PC + .org opcjmp_table_pos_ + rjmp pc_save_ + .org pc_save_ jmp l_@0_@1_@2 - .set todo_table_pos_ = PC - .set done_ = 1 .endif - .endif - .if !done_ + .else + + checkspace pc_save_, 2*cnt_ + .set pc_save_ = PC - .equ l_@0_@1_@2 = todo_table_pos_ ; make a label + .org opcjmp_table_pos_ + .equ l_@0_@1_@2 = pc_save_ ; make a label rjmp l_@0_@1_@2 ; generate a jump to action table .org l_@0_@1_@2 @@ -335,16 +338,10 @@ int_nobreak: .endif .endif - .set todo_table_pos_ = PC - .endif .endif - .if todo_table_pos_ == 0 - .org pc_save_ - .else - .org todo_table_pos_ - .endif + .set opcjmp_table_pos_ = opcjmp_table_pos_ + 1 .endm @@ -354,9 +351,17 @@ do_x_nop: ; ------------ Fetch phase stuff ----------------- + fetch_ops: .equ do_fetch_nop = do_x_nop +do_fetch_rst: + movw x,z_pcl + sbiw x,1 + mem_read_d opl + andi opl,0x38 + ldi oph,0 + ret .macro m_do_fetch_a mov opl,z_a @@ -479,14 +484,6 @@ do_fetch_dir16: adiw z_pcl,1 ret -do_fetch_rst: - movw x,z_pcl - sbiw x,1 - mem_read_d opl - andi opl,0x38 - ldi oph,0 - ret - ; ------------ Store phase stuff ----------------- store_ops: @@ -1959,14 +1956,11 @@ do_op_EXX: #if EM_Z80 -do_op_noni: - sbiw z_pcl,1 ;--z_pc - ret - do_op_prefixED: mem_read_ds zl,z_pc ;zl = memReadByte(z_pc) adiw z_pcl,1 ;++z_pc ldi zh,high(EDjmp) ; +;;; ldi zh,high(0) ; ijmp @@ -2031,23 +2025,24 @@ do_op_prefixCB: #endif + ; ----------------------- Opcode decoding ------------------------- ; Lookup table for Z80 opcodes. Translates the first byte of the instruction word into three ; operations: fetch, do something, store. ; The table is made of 256 words. - opctable opcjmp + opctable opcjmp, PC ;+3*256 instr fetch_nop, op_nop, store_nop ;00 ;NOP instr fetch_DIR16, op_nop, store_BC ;01 nn nn ;LD BC,nn instr fetch_nop, op_nop, store_MBC ;02 ;LD (BC),A instr fetch_BC, op_INC16, store_BC ;03 ;INC BC instr fetch_B, op_INC, store_B ;04 ;INC B -instr fetch_B, op_DEC, store_B ;05 ;DEC B +instr fetch_B, op_DEC, store_B ;05 ;DEC B instr fetch_DIR8, op_nop, store_B ;06 ;LD B,n instr fetch_nop, op_RLCA, store_nop ;07 ;RLCA -instr fetch_nop, op_EXAF, store_nop ;08 ;EX AF,AF' +instr fetch_nop, op_EXAF, store_nop ;08 ;EX AF,AF' instr fetch_BC, op_ADDHL, store_nop ;09 ;ADD HL,BC instr fetch_MBC, op_nop, store_nop ;0A ;LD A,(BC) instr fetch_BC, op_DEC16, store_BC ;0B ;DEC BC @@ -2060,49 +2055,49 @@ instr fetch_DIR16, op_nop, store_DE ;11 nn nn ;LD DE,nn instr fetch_nop, op_nop, store_MDE ;12 ;LD (DE),A instr fetch_DE, op_INC16, store_DE ;13 ;INC DE instr fetch_D, op_INC, store_D ;14 ;INC D -instr fetch_D, op_DEC, store_D ;15 ;DEC D +instr fetch_D, op_DEC, store_D ;15 ;DEC D instr fetch_DIR8, op_nop, store_D ;16 nn ;LD D,n instr fetch_nop, op_RLA, store_nop ;17 ;RLA instr fetch_DIR8, op_nop, store_pcrel ;18 oo ;JR o instr fetch_DE, op_ADDHL, store_nop ;19 ;ADD HL,DE instr fetch_MDE, op_nop, store_nop ;1A ;LD A,(DE) -instr fetch_DE, op_DEC16, store_DE ;1B ;DEC DE +instr fetch_DE, op_DEC16, store_DE ;1B ;DEC DE instr fetch_E, op_INC, store_E ;1C ;INC E -instr fetch_E, op_DEC, store_E ;1D ;DEC E +instr fetch_E, op_DEC, store_E ;1D ;DEC E instr fetch_DIR8, op_nop, store_E ;1E nn ;LD E,n instr fetch_nop, op_RRA, store_nop ;1F ;RRA instr fetch_DIR8, op_IFNZ, store_pcrel ;20 oo ;JR NZ,o instr fetch_DIR16, op_nop, store_HL ;21 nn nn ;LD HL,nn instr fetch_DIR16, op_STHL, store_nop ;22 nn nn ;LD (nn),HL instr fetch_HL, op_INC16, store_HL ;23 ;INC HL -instr fetch_H, op_INC, store_H ;24 ;INC H -instr fetch_H, op_DEC, store_H ;25 ;DEC H -instr fetch_DIR8, op_nop, store_H ;26 nn ;LD H,n -instr fetch_A, op_DAA, store_A ;27 ;DAA +instr fetch_H, op_INC, store_H ;24 ;INC H +instr fetch_H, op_DEC, store_H ;25 ;DEC H +instr fetch_DIR8, op_nop, store_H ;26 nn ;LD H,n +instr fetch_A, op_DAA, store_A ;27 ;DAA instr fetch_DIR8, op_IFZ, store_pcrel ;28 oo ;JR Z,o instr fetch_HL, op_ADDHL, store_nop ;29 ;ADD HL,HL instr fetch_DIR16, op_RMEM16, store_HL ;2A nn nn ;LD HL,(nn) -instr fetch_HL, op_DEC16, store_HL ;2B ;DEC HL -instr fetch_L, op_INC, store_L ;2C ;INC L -instr fetch_L, op_DEC, store_L ;2D ;DEC L -instr fetch_DIR8, op_nop, store_L ;2E nn ;LD L,n -instr fetch_nop, op_CPL, store_nop ;2F ;CPL +instr fetch_HL, op_DEC16, store_HL ;2B ;DEC HL +instr fetch_L, op_INC, store_L ;2C ;INC L +instr fetch_L, op_DEC, store_L ;2D ;DEC L +instr fetch_DIR8, op_nop, store_L ;2E nn ;LD L,n +instr fetch_nop, op_CPL, store_nop ;2F ;CPL instr fetch_DIR8, op_IFNC, store_pcrel ;30 oo ;JR NC,o instr fetch_DIR16, op_nop, store_SP ;31 nn nn ;LD SP,nn instr fetch_DIR16, op_nop, store_AM ;32 nn nn ;LD (nn),A instr fetch_SP, op_INC16, store_SP ;33 ;INC SP instr fetch_MHL, op_INC, store_MHL ;34 ;INC (HL) -instr fetch_MHL, op_DEC, store_MHL ;35 ;DEC (HL) +instr fetch_MHL, op_DEC, store_MHL ;35 ;DEC (HL) instr fetch_DIR8, op_nop, store_MHL ;36 nn ;LD (HL),n instr fetch_nop, op_SCF, store_nop ;37 ;SCF instr fetch_DIR8, op_IFC, store_pcrel ;38 oo ;JR C,o instr fetch_SP, op_ADDHL, store_nop ;39 ;ADD HL,SP -instr fetch_DIR16, op_RMEM8, store_A ;3A nn nn ;LD A,(nn) -instr fetch_SP, op_DEC16, store_SP ;3B ;DEC SP +instr fetch_DIR16, op_RMEM8, store_A ;3A nn nn ;LD A,(nn) +instr fetch_SP, op_DEC16, store_SP ;3B ;DEC SP instr fetch_nop, op_INCA, store_nop ;3C ;INC A -instr fetch_nop, op_DECA, store_nop ;3D ;DEC A -instr fetch_DIR8, op_nop, store_A ;3E nn ;LD A,n -instr fetch_nop, op_CCF, store_nop ;3F ;CCF (Complement Carry Flag, gvd) +instr fetch_nop, op_DECA, store_nop ;3D ;DEC A +instr fetch_DIR8, op_nop, store_A ;3E nn ;LD A,n +instr fetch_nop, op_CCF, store_nop ;3F ;CCF (Complement Carry Flag, gvd) instr fetch_nop, op_nop, store_nop ;40 ;LD B,B instr fetch_C, op_nop, store_B ;41 ;LD B,C instr fetch_D, op_nop, store_B ;42 ;LD B,D @@ -2223,14 +2218,14 @@ instr fetch_H, op_ORA, store_nop ;B4 ;OR A,H instr fetch_L, op_ORA, store_nop ;B5 ;OR A,L instr fetch_MHL, op_ORA, store_nop ;B6 ;OR A,(HL) instr fetch_A, op_ORA, store_nop ;B7 ;OR A,A -instr fetch_B, op_CPFA, store_nop ;B8 ;CP A,B -instr fetch_C, op_CPFA, store_nop ;B9 ;CP A,C -instr fetch_D, op_CPFA, store_nop ;BA ;CP A,D -instr fetch_E, op_CPFA, store_nop ;BB ;CP A,E -instr fetch_H, op_CPFA, store_nop ;BC ;CP A,H -instr fetch_L, op_CPFA, store_nop ;BD ;CP A,L -instr fetch_MHL, op_CPFA, store_nop ;BE ;CP A,(HL) -instr fetch_A, op_CPFA, store_nop ;BF ;CP A,A +instr fetch_B, op_CPFA, store_nop ;B8 ;CP A,B +instr fetch_C, op_CPFA, store_nop ;B9 ;CP A,C +instr fetch_D, op_CPFA, store_nop ;BA ;CP A,D +instr fetch_E, op_CPFA, store_nop ;BB ;CP A,E +instr fetch_H, op_CPFA, store_nop ;BC ;CP A,H +instr fetch_L, op_CPFA, store_nop ;BD ;CP A,L +instr fetch_MHL, op_CPFA, store_nop ;BE ;CP A,(HL) +instr fetch_A, op_CPFA, store_nop ;BF ;CP A,A instr fetch_nop, op_IFNZ, store_RET ;C0 ;RET NZ instr fetch_nop, op_POP16, store_BC ;C1 ;POP BC instr fetch_DIR16, op_IFNZ, store_PC ;C2 nn nn ;JP NZ,nn @@ -2256,7 +2251,7 @@ instr fetch_DE, op_PUSH16, store_nop ;D5 ;PUSH DE instr fetch_DIR8, op_SUBFA, store_nop ;D6 nn ;SUB n instr fetch_RST, op_nop, store_CALL ;D7 ;RST 10H instr fetch_nop, op_IFC, store_RET ;D8 ;RET C -instr fetch_nop, op_EXX, store_nop ;D9 ;EXX +instr fetch_nop, op_EXX, store_nop ;D9 ;EXX instr fetch_DIR16, op_IFC, store_PC ;DA nn nn ;JP C,nn instr fetch_DIR8, op_INA, store_nop ;DB nn ;IN A,(n) instr fetch_DIR16, op_IFC, store_CALL ;DC nn nn ;CALL C,nn @@ -2266,7 +2261,7 @@ instr fetch_RST, op_nop, store_CALL ;DF ;RST 18H instr fetch_nop, op_IFPO, store_RET ;E0 ;RET PO instr fetch_nop, op_POP16, store_HL ;E1 ;POP HL instr fetch_DIR16, op_IFPO, store_PC ;E2 nn nn ;JP PO,nn -instr fetch_MSP, op_EXHL, store_MSP ;E3 ;EX (SP),HL +instr fetch_MSP, op_EXHL, store_MSP ;E3 ;EX (SP),HL instr fetch_DIR16, op_IFPO, store_CALL ;E4 nn nn ;CALL PO,nn instr fetch_HL, op_PUSH16, store_nop ;E5 ;PUSH HL instr fetch_DIR8, op_ANDA, store_nop ;E6 nn ;AND n @@ -2274,7 +2269,7 @@ instr fetch_RST, op_nop, store_CALL ;E7 ;RST 20H instr fetch_nop, op_IFPE, store_RET ;E8 ;RET PE instr fetch_HL, op_nop, store_PC ;E9 ;JP HL instr fetch_DIR16, op_IFPE, store_PC ;EA nn nn ;JP PE,nn -instr fetch_DE, op_EXHL, store_DE ;EB ;EX DE,HL +instr fetch_DE, op_EXHL, store_DE ;EB ;EX DE,HL instr fetch_DIR16, op_IFPE, store_CALL ;EC nn nn ;CALL PE,nn instr fetch_nop, op_prefixED, store_nop ;ED ;(ED opcode prefix) instr fetch_DIR8, op_XORA, store_nop ;EE nn ;XOR n @@ -2282,7 +2277,7 @@ instr fetch_RST, op_nop, store_CALL ;EF ;RST 28H instr fetch_nop, op_IFP, store_RET ;F0 ;RET P instr fetch_nop, op_POP16, store_AF ;F1 ;POP AF instr fetch_DIR16, op_IFP, store_PC ;F2 nn nn ;JP P,nn -instr fetch_nop, op_DI, store_nop ;F3 ;DI +instr fetch_nop, op_DI, store_nop ;F3 ;DI instr fetch_DIR16, op_IFP, store_CALL ;F4 nn nn ;CALL P,nn instr fetch_AF, op_PUSH16, store_nop ;F5 ;PUSH AF instr fetch_DIR8, op_ORA, store_nop ;F6 nn ;OR n @@ -2290,10 +2285,10 @@ instr fetch_RST, op_nop, store_CALL ;F7 ;RST 30H instr fetch_nop, op_IFM, store_RET ;F8 ;RET M instr fetch_HL, op_nop, store_SP ;F9 ;LD SP,HL instr fetch_DIR16, op_IFM, store_PC ;FA nn nn ;JP M,nn -instr fetch_nop, op_EI, store_nop ;FB ;EI +instr fetch_nop, op_EI, store_nop ;FB ;EI instr fetch_DIR16, op_IFM, store_CALL ;FC nn nn ;CALL M,nn instr fetch_nop, op_prefixFD, store_nop ;FD ;(FD opcode prefix) -instr fetch_DIR8, op_CPFA, store_nop ;FE nn ;CP n +instr fetch_DIR8, op_CPFA, store_nop ;FE nn ;CP n instr fetch_RST, op_nop, store_CALL ;FF ;RST 38H @@ -2301,359 +2296,96 @@ instr fetch_RST, op_nop, store_CALL ;FF ;RST 38H -do_fetch_0: - ldi opl,0 + checkspace PC, 2 + +do_op_noni: + sbiw z_pcl,1 ;--z_pc ret + checkspace PC, 16 + do_fetch_dir8_2: movw xl,z_pcl adiw xl,1 mem_read_d opl ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|IN r,[C] |***P0-|Input |r=[C] | -; + checkspace PC, 5 -do_op_in: ; in opl,(opl) -.if PORT_DEBUG - push opl - cp opl,_0 ; don't debug port 0 (con stat) - breq dbg_op_in_1 - printnewline - printstring "Port read: (" - mov temp,opl - lcall printhex - printstring ") -> " -dbg_op_in_1: -.endif +do_fetch_xh: + sbis flags,prefixfd + ldd opl,y+oz_xh + sbic flags,prefixfd + ldd opl,y+oz_yh + ret - mov temp2,opl - lcall portRead - mov opl,temp - bst z_flags,ZFL_C ;save Carry - ldpmx z_flags,sz53p_tab,temp ;S,Z,P - bld z_flags,ZFL_C + checkspace PC, 5 -.if PORT_DEBUG - pop temp - cp temp,_0 - breq dbg_op_in_2 - lcall printhex - printstring " " -dbg_op_in_2: -.endif +do_fetch_xl: + sbis flags,prefixfd + ldd opl,y+oz_xl + sbic flags,prefixfd + ldd opl,y+oz_yl ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|OUT [C],r |------|Output |[C]=r | -; -do_op_out: ; out (c),opl -.if PORT_DEBUG - printnewline - printstring "Port write: " - mov temp,opl - lcall printhex - printstring " -> (" - ldd temp,y+oz_c - lcall printhex - printstring ") " -.endif - mov temp,opl - ldd temp2,y+oz_c - lcall portWrite - ret + checkspace PC, 41 -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|LD dst,src|------|Load |dst=src | -; +do_fetch_mxx: + sbic flags,prefixfd + rjmp fetchmxx_fd + ldd xh,y+oz_xh + ldd xl,y+oz_xl + rjmp fetchmxx1 +fetchmxx_fd: + ldd xh,y+oz_yh + ldd xl,y+oz_yl +fetchmxx1: + mem_read_ds opl, z_pc ;get displacement + adiw z_pcl,1 + clr oph ;sign extend + tst opl + brpl fetchmxx2 + com oph +fetchmxx2: + add xl,opl ;add displacement + adc xh,oph + mem_read_d opl ;get operand + ret ;(Ix+d) still in xl,xh -do_op_stbc: ;store bc to mem loc in opl:h - movw xl,opl - ldd temp,y+oz_c - mem_write - adiw xl,1 - ldd temp,y+oz_b - mem_write + + checkspace PC, 8 + +do_fetch_xx: + sbic flags,prefixfd + rjmp fetchxx_fd + ldd opl,y+oz_xl + ldd oph,y+oz_xh + ret +fetchxx_fd: + ldd opl,y+oz_yl + ldd oph,y+oz_yh ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|LD dst,src|------|Load |dst=src | -; -; -do_op_stde: ;store de to mem loc in opl:h - movw xl,opl - ldd temp,y+oz_e - mem_write - adiw xl,1 - ldd temp,y+oz_d - mem_write + checkspace PC, 5 + +do_store_xh: + sbis flags,prefixfd + std y+oz_xh,opl + sbic flags,prefixfd + std y+oz_yh,opl ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|LD dst,src|------|Load |dst=src | -; -; -do_op_stsp: ;store sp to mem loc in opl:h - movw xl,opl - mem_write_s z_spl - adiw xl,1 - mem_write_s z_sph + checkspace PC, 5 + +do_store_xl: + sbis flags,prefixfd + std y+oz_xl,opl + sbic flags,prefixfd + std y+oz_yl,opl ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|ADC HL,ss |***V0*|Add with Carry |HL=HL+ss+CY | -; - -do_op_ADCHL: - ldd temp,y+oz_l - ldd temp2,y+oz_h - clc - sbrc z_flags,ZFL_C - sec - adc opl,temp - in temp,sreg ; save lower Z - adc oph,temp2 - in temp2,sreg - std y+oz_l,opl - std y+oz_h,oph - and temp,temp2 ; 16bit Z - ldi z_flags,0 ; clear N - bmov z_flags,ZFL_C, temp2,AVR_C - bmov z_flags,ZFL_P, temp2,AVR_V - bmov z_flags,ZFL_H, temp2,AVR_H - bmov z_flags,ZFL_Z, temp,AVR_Z - bmov z_flags,ZFL_S, temp2,AVR_N - ret - -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|SBC HL,ss |***V1*|Subtract with carry |HL=HL-ss-CY | -; -; -do_op_sbchl: - ldd temp,y+oz_l - ldd temp2,y+oz_h - cp temp,opl ; set z - clc - sbrc z_flags,ZFL_C - sec - sbc temp,opl - sbc temp2,oph - std y+oz_l,temp - std y+oz_h,temp2 - in temp,sreg - ldi z_flags,(1< P | -;|LD i,A |------|Load |(i=I,R) | - -do_op_ldai: - ldd z_a,y+oz_i - rjmp op_ldar1 - -do_op_ldar: - ldd z_a,y+oz_r -op_ldar1: - bst z_flags,ZFL_C ;save C - ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N - bld z_flags,ZFL_C ; - ldd temp,y+oz_istat - bmov z_flags,ZFL_P, temp,IFF2 - ret - -do_op_ldia: - std y+oz_i,z_a - ret - -do_op_ldra: - std y+oz_r,z_a - ret - -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##| -;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##| - -do_op_rld: - swap opl - mov oph,opl - andi opl,0xf0 - andi oph,0x0f - mov temp,z_a - andi temp,0x0f - or opl,temp - mov temp,z_a - andi temp,0xf0 - or temp,oph - mov z_a,temp - bst z_flags,ZFL_C ;save C - ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N - bld z_flags,ZFL_C ; - ret - -do_op_rrd: - mov oph,opl - andi opl,0xf0 - andi oph,0x0f - mov temp,z_a - andi temp,0x0f - or opl,temp - swap opl - mov temp,z_a - andi temp,0xf0 - or temp,oph - mov z_a,temp - bst z_flags,ZFL_C ;save C - ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N - bld z_flags,ZFL_C ; - ret - - -do_fetch_xh: - sbis flags,prefixfd - ldd opl,y+oz_xh - sbic flags,prefixfd - ldd opl,y+oz_yh - ret - -do_fetch_xl: - sbis flags,prefixfd - ldd opl,y+oz_xl - sbic flags,prefixfd - ldd opl,y+oz_yl - ret - - -do_fetch_mxx: - sbic flags,prefixfd - rjmp fetchmxx_fd - ldd xh,y+oz_xh - ldd xl,y+oz_xl - rjmp fetchmxx1 -fetchmxx_fd: - ldd xh,y+oz_yh - ldd xl,y+oz_yl -fetchmxx1: - mem_read_ds opl, z_pc ;get displacement - adiw z_pcl,1 - clr oph ;sign extend - tst opl - brpl fetchmxx2 - com oph -fetchmxx2: - add xl,opl ;add displacement - adc xh,oph - mem_read_d opl ;get operand - ret ;(Ix+d) still in xl,xh - - -do_fetch_xx: - sbic flags,prefixfd - rjmp fetchxx_fd - ldd opl,y+oz_xl - ldd oph,y+oz_xh - ret -fetchxx_fd: - ldd opl,y+oz_yl - ldd oph,y+oz_yh - ret - -do_store_xh: - sbis flags,prefixfd - std y+oz_xh,opl - sbic flags,prefixfd - std y+oz_yh,opl - ret - -do_store_xl: - sbis flags,prefixfd - std y+oz_xl,opl - sbic flags,prefixfd - std y+oz_yl,opl - ret + checkspace PC, 37 do_store_mxx: sbic flags,prefixfd @@ -2677,10 +2409,14 @@ storemxx2: mem_write_s opl ;store operand ret + checkspace PC, 10 + do_store_mxx_0: mem_write_s opl ;store operand ret + checkspace PC, 38 + do_store_mxx_2: sbic flags,prefixfd rjmp storemxx2_fd @@ -2704,6 +2440,8 @@ storemxx22: mem_write_s opl ;store operand ret + checkspace PC, 8 + do_store_xx: sbic flags,prefixfd rjmp storexx_fd @@ -2720,10 +2458,12 @@ storexx_fd: ;---------------------------------------------------------------- ;|LD dst,src|------|Load |dst=src | ; -; + + checkspace PC, 30 + do_op_stxx: ;store xx to mem loc in opl:h - movw xl,opl + movw xl,opl sbis flags,prefixfd ldd temp,y+oz_xl sbic flags,prefixfd @@ -2744,6 +2484,8 @@ do_op_stxx: ;store xx to mem loc in opl:h ;|EX [SP],IX|------|Exchange |[SP]<->IX | ;|EX [SP],IY|------|Exchange |[SP]<->IY | ; + checkspace PC, 13 + do_op_EXxx: sbic flags,prefixfd rjmp opexxx_fd @@ -2767,7 +2509,9 @@ opexxxe: ;|ADD IX,pp |--*-0*|Add |IX=IX+pp | ;|ADD IY,rr |--*-0*|Add |IY=IY+rr | ; -; + + checkspace PC, 25 + do_op_addxx: sbic flags,prefixfd rjmp opadx_fd @@ -2792,1043 +2536,565 @@ opadx_e: do_z80_flags_clear_N ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# | -;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 | -;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# | -;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 | -; -op_LDxx_common: - ldd zh,y+oz_h ;H - ldd zl,y+oz_l ;L - ldd xh,y+oz_d ;D - ldd xl,y+oz_e ;E - ldd oph,y+oz_b ;B - ldd opl,y+oz_c ;C - mem_read_ds temp, z - mem_write_ds x, temp - cbr z_flags,(1<m | +;|RL m |**0P0*|Rotate Left |m={CY,m}<- | +;|RR m |**0P0*|Rotate Right |m=->{CY,m} | +;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 | +;|SRA m |**0P0*|Shift Right Arith. |m=m/2 | +;|SLL m |**0P0*|Shift Right Logical | +;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} | -op_CPxx_common: - ldd xh,y+oz_h ; H - ldd xl,y+oz_l ; L - ldd zh,y+oz_b ; B - ldd zl,y+oz_c ; C - cbr z_flags,(1< Bit 7 + ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N + bmov z_flags,ZFL_C, temp,AVR_C ; ret -do_op_INI: - rcall op_INxx_common - adiw x,1 - std y+oz_l,xl ;L - std y+oz_h,xh ;H + checkspace PC, 8 + +do_op_sla: + lsl opl + in temp,sreg + ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N + bmov z_flags,ZFL_C, temp,AVR_C ; ret -do_op_IND: - rcall op_INxx_common - sbiw x,1 - std y+oz_l,xl ;L - std y+oz_h,xh ;H + checkspace PC, 9 + +do_op_sra: + lsr opl + in temp,sreg + bmov opl,7, opl,6 ;old CY --> Bit 7 + ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N + bmov z_flags,ZFL_C, temp,AVR_C ; ret -do_op_INIR: - rcall do_op_INI - sbrc z_flags,ZFL_Z - ret - sbiw z_pcl,2 + checkspace PC, 9 + +do_op_sll: + sec + rol opl + in temp,sreg + ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N + bmov z_flags,ZFL_C, temp,AVR_C ; ret -do_op_INDR: - rcall do_op_IND - sbrc z_flags,ZFL_Z - ret - sbiw z_pcl,2 + checkspace PC, 8 + +do_op_srl: + lsr opl + in temp,sreg + ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N + bmov z_flags,ZFL_C, temp,AVR_C ; ret ;---------------------------------------------------------------- ;|Mnemonic |SZHPNC|Description |Notes | ;---------------------------------------------------------------- -;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1| -;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1| -;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 | -;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 | +;|BIT b,m |?*1?0-|Test Bit |m&{2^b} | +;|RES b,m |------|Reset bit |m=m&{~2^b} | +;|SET b,m |------|Set bit |m=mv{2^b} | -op_OUTxx_common: - cbr z_flags,(1<m | -;|RL m |**0P0*|Rotate Left |m={CY,m}<- | -;|RR m |**0P0*|Rotate Right |m=->{CY,m} | -;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 | -;|SRA m |**0P0*|Shift Right Arith. |m=m/2 | -;|SLL m |**0P0*|Shift Right Logical | -;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} | - - -do_op_rlc: - ;Rotate Left Cyclical. All bits move 1 to the - ;left, the msb becomes c and lsb. - clr temp - lsl opl - adc temp,_0 - or opl,temp - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - or z_flags,temp - ret - -do_op_rrc: - ;Rotate Right Cyclical. All bits move 1 to the - ;right, the lsb becomes c and msb. - lsr opl - brcc PC+2 - ori opl,0x80 - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, opl,7 - ret - - -do_op_rl: - ;Rotate Left. All bits move 1 to the left, the msb - ;becomes c, c becomes lsb. - clc - sbrc z_flags,ZFL_C - sec - rol opl - in temp,sreg - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, temp,AVR_C - ret - - -do_op_rr: - ;Rotate Right. All bits move 1 to the right, the lsb - ;becomes c, c becomes msb. - - ror opl - in temp,sreg ;CY - bmov opl,7, z_flags,ZFL_C ;old CY --> Bit 7 - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, temp,AVR_C ; - ret - -do_op_sla: - lsl opl - in temp,sreg - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, temp,AVR_C ; - ret - -do_op_sra: - lsr opl - in temp,sreg - bmov opl,7, opl,6 ;old CY --> Bit 7 - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, temp,AVR_C ; - ret - -do_op_sll: - sec - rol opl - in temp,sreg - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, temp,AVR_C ; - ret - -do_op_srl: - lsr opl - in temp,sreg - ldpmx z_flags,sz53p_tab,opl ;S,Z,H,P,N - bmov z_flags,ZFL_C, temp,AVR_C ; +do_store2_a: + mov z_a,opl ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|BIT b,m |?*1?0-|Test Bit |m&{2^b} | -;|RES b,m |------|Reset bit |m=m&{~2^b} | -;|SET b,m |------|Set bit |m=mv{2^b} | - - -do_op_BIT7: - ldi temp,0x80 - rjmp opbit -do_op_BIT6: - ldi temp,0x40 - rjmp opbit -do_op_BIT5: - ldi temp,0x20 - rjmp opbit -do_op_BIT4: - ldi temp,0x10 - rjmp opbit -do_op_BIT3: - ldi temp,0x08 - rjmp opbit -do_op_BIT2: - ldi temp,0x04 - rjmp opbit -do_op_BIT1: - ldi temp,0x02 - rjmp opbit -do_op_BIT0: - ldi temp,0x01 -opbit: - and temp,opl - in temp,sreg - ori z_flags,(1< " +dbg_op_in_1: +.endif + + mov temp2,opl + lcall portRead + mov opl,temp + bst z_flags,ZFL_C ;save Carry + ldpmx z_flags,sz53p_tab,temp ;S,Z,P + bld z_flags,ZFL_C + +.if PORT_DEBUG + pop temp + cp temp,_0 + breq dbg_op_in_2 + lcall printhex + printstring " " +dbg_op_in_2: +.endif + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|OUT [C],r |------|Output |[C]=r | +; + +do_op_out: ; out (c),opl +.if PORT_DEBUG + printnewline + printstring "Port write: " + mov temp,opl + lcall printhex + printstring " -> (" + ldd temp,y+oz_c + lcall printhex + printstring ") " +.endif + mov temp,opl + ldd temp2,y+oz_c + lcall portWrite + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|LD dst,src|------|Load |dst=src | +; + +do_op_stbc: ;store bc to mem loc in opl:h + movw xl,opl + ldd temp,y+oz_c + mem_write + adiw xl,1 + ldd temp,y+oz_b + mem_write + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|LD dst,src|------|Load |dst=src | +; +; +do_op_stde: ;store de to mem loc in opl:h + movw xl,opl + ldd temp,y+oz_e + mem_write + adiw xl,1 + ldd temp,y+oz_d + mem_write + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|LD dst,src|------|Load |dst=src | +; +; +do_op_stsp: ;store sp to mem loc in opl:h + movw xl,opl + mem_write_s z_spl + adiw xl,1 + mem_write_s z_sph + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|ADC HL,ss |***V0*|Add with Carry |HL=HL+ss+CY | +; + +do_op_ADCHL: + ldd temp,y+oz_l + ldd temp2,y+oz_h + clc + sbrc z_flags,ZFL_C + sec + adc opl,temp + in temp,sreg ; save lower Z + adc oph,temp2 + in temp2,sreg + std y+oz_l,opl + std y+oz_h,oph + and temp,temp2 ; 16bit Z + ldi z_flags,0 ; clear N + bmov z_flags,ZFL_C, temp2,AVR_C + bmov z_flags,ZFL_P, temp2,AVR_V + bmov z_flags,ZFL_H, temp2,AVR_H + bmov z_flags,ZFL_Z, temp,AVR_Z + bmov z_flags,ZFL_S, temp2,AVR_N + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|SBC HL,ss |***V1*|Subtract with carry |HL=HL-ss-CY | +; + + checkspace PC, 24 + +do_op_sbchl: + ldd temp,y+oz_l + ldd temp2,y+oz_h + cp temp,opl ; set z + clc + sbrc z_flags,ZFL_C + sec + sbc temp,opl + sbc temp2,oph + std y+oz_l,temp + std y+oz_h,temp2 + in temp,sreg + ldi z_flags,(1< P | +;|LD i,A |------|Load |(i=I,R) | + +do_op_ldai: + ldd z_a,y+oz_i + rjmp op_ldar1 + +do_op_ldar: + ldd z_a,y+oz_r +op_ldar1: + bst z_flags,ZFL_C ;save C + ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N + bld z_flags,ZFL_C ; + ldd temp,y+oz_istat + bmov z_flags,ZFL_P, temp,IFF2 + ret + +do_op_ldia: + std y+oz_i,z_a + ret + +do_op_ldra: + std y+oz_r,z_a + ret + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##| +;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##| + +do_op_rld: + swap opl + mov oph,opl + andi opl,0xf0 + andi oph,0x0f + mov temp,z_a + andi temp,0x0f + or opl,temp + mov temp,z_a + andi temp,0xf0 + or temp,oph + mov z_a,temp + bst z_flags,ZFL_C ;save C + ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N + bld z_flags,ZFL_C ; + ret + +do_op_rrd: + mov oph,opl + andi opl,0xf0 + andi oph,0x0f + mov temp,z_a + andi temp,0x0f + or opl,temp + swap opl + mov temp,z_a + andi temp,0xf0 + or temp,oph + mov z_a,temp + bst z_flags,ZFL_C ;save C + ldpmx z_flags,sz53p_tab,z_a ;S,Z,H,P,N + bld z_flags,ZFL_C ; + ret + + +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# | +;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 | +;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# | +;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 | +; + + checkspace PC, 19 + +op_LDxx_common: + ldd xh,y+oz_h ;H + ldd xl,y+oz_l ;L +; mem_read_ds temp, z + lcall dram_read ; temp = (HL) + movw z,x + + ldd xh,y+oz_d ;D + ldd xl,y+oz_e ;E +; mem_write_ds x, temp + lcall dram_write ; (DE) = temp + + ldd oph,y+oz_b ;B + ldd opl,y+oz_c ;C + + cbr z_flags,(1<>>-------------------------------------- Virtual Devices - .include "virt_ports.asm" ; Virtual Ports for BIOS -; <<<-------------------------------------- Virtual Devices - ; >>>-------------------------------------- File System Management .include "dsk_fsys.asm" ; Basic Filesystem definitions .include "dsk_mgr.asm" ; Disk- Manager .include "dsk_cpm.asm" ; CPM- Disk Interaktion .include "dsk_fat16.asm" ; FAT16-DISK Interaktion .include "dsk_ram.asm" ; RAM- Disk Interaktion + .include "virt_ports.asm" ; Virtual Ports for BIOS ; <<<-------------------------------------- File System Management + ; .include "8080int-orig.asm" ;Old 8080 interpreter. ; .include "8080int.asm" ;New 8080 interpreter. ; .include "8080int-t3.asm" ;Another 8080 interpreter diff --git a/avr/config.inc b/avr/config.inc index 5917a06..192ecb4 100644 --- a/avr/config.inc +++ b/avr/config.inc @@ -29,19 +29,21 @@ #define DRAM_8BIT 1 /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/ #endif /* 0 = only one 4 bit wide DRAM chip */ #ifndef F_CPU - #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ + #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ #endif #ifndef BAUD #define BAUD 38400 /* console baud rate */ #endif #ifndef I2C - #define I2C 0 /* I2C requires 8 bit DRAM */ + #define I2C 0 /* I2C requires 8 bit DRAM */ #endif #if I2C && !DRAM_8BIT #error "I2C requires 8 bit DRAM (DRAM_8BIT=1)!" #endif -#define EM_Z80 1 /* Emulate Z80 if true, else 8080 */ +#ifndef EM_Z80 + #define EM_Z80 1 /* Emulate Z80 if true, else 8080 */ +#endif #ifndef FAT16_SUPPORT #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */ @@ -57,7 +59,7 @@ #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */ /* Most drams need 1/15.6µs. */ #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */ -#define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */ +#define TXBUFSIZE 32 /* USART transmit buffer size. Must be power of 2 */ #define I2C_CLOCK 100000 /* 100kHz */ #define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */ @@ -242,12 +244,20 @@ .equ i_halt = 2 ;executing halt instruction #if defined __ATmega8__ -.equ flags = TWBR -.equ P_PUD = SFIOR -#else -.equ flags = GPIOR0 -.equ P_PUD = MCUCR -#endif + #if DRAM_8BIT + + .equ flags = UBRRL ;UART is unused with 8-Bit RAM + #else + .equ flags = TWBR ;TWI is unused with 4-Bit RAM + #endif + .equ P_PUD = SFIOR + +#else + + .equ flags = GPIOR0 + .equ P_PUD = MCUCR + +#endif /* __ATmega8__ */ ; Flags: .equ hostact = 7 ;host active flag diff --git a/avr/dsk_fsys.asm b/avr/dsk_fsys.asm index 1ba9f7d..f2d656b 100644 --- a/avr/dsk_fsys.asm +++ b/avr/dsk_fsys.asm @@ -451,38 +451,6 @@ cpydpb_l: ret -; String compare (z, y), one z-string in flash. - -strcmp_p: - lpm _tmp0,z+ - tst _tmp0 - breq strcmp_pex - - ld temp, y+ - lpm _tmp0, z+ - sub temp,_tmp0 - brne strcmp_pex - tst _tmp0 - brne strcmp_p -strcmp_pex: - ret - -; String compare (x, y, temp2). Max temp2 bytes are compared. - -strncmp_p: - subi temp2,1 - brcs strncmp_peq - ld temp,y+ - lpm _tmp0, z+ - sub temp,_tmp0 - brne strncmp_pex - tst _tmp0 - brne strncmp_p -strncmp_peq: - sub temp,temp -strncmp_pex: - ret - ; ==================================================================== ; Function: get drive table entry pointer for drive # in temp ; ==================================================================== @@ -615,7 +583,7 @@ dsk_tst_yaze: ldiw y,hostbuf ldiw z,str_CPM_Disk*2 lpm temp2,z+ ; get length - rcall strncmp_p + lcall strncmp_p brne dsk_tyze_not ldiw z,hostbuf+32 @@ -696,7 +664,7 @@ dsk_tst_simhd: ldiw y,hostbuf+128-10 ldiw z,str_CPM_Disk*2 lpm temp2,z+ ; get length - rcall strncmp_p + lcall strncmp_p breq dsk_tsimhd_found ldiw z,hostbuf diff --git a/avr/macros.inc b/avr/macros.inc index 03360c6..74c9f21 100644 --- a/avr/macros.inc +++ b/avr/macros.inc @@ -135,6 +135,7 @@ .endif .endm + ;------------------------------------------------ ; ; @@ -142,7 +143,7 @@ .if FLASHEND > 0x0fff .ifdef @0 .if abs(PC - @0) > 2047 - call @0 + call @0 .else rcall @0 .endif @@ -159,11 +160,7 @@ ; printstring "String" .macro printstring - .if FLASHEND > 0x0fff - call printstr - .else - rcall printstr - .endif + lcall printstr .if strlen(@0) % 2 .db @0,0 .else diff --git a/avr/sw-uart.asm b/avr/sw-uart.asm index df25d09..7e81d98 100644 --- a/avr/sw-uart.asm +++ b/avr/sw-uart.asm @@ -21,6 +21,10 @@ ; $Id$ ; +#ifdef __ATmega8__ + #error "ATmega8 is not supported (yet)! Please update this driver, or buy an ATmega88." +#endif + #define SSER_BIT_TC (F_CPU+BAUD/2) / BAUD #define RXBUFMASK RXBUFSIZE-1 @@ -34,8 +38,8 @@ srx_char_to: .byte 1 srx_dr: .byte 1 -;srx_lastedge: -; .byte 2 +srx_lastedge: + .byte 2 stx_bitcount: .byte 1 stx_dr: @@ -70,14 +74,20 @@ uart_init: ; - Soft UART RX (ICP1/ICR1). ; - 1ms System timer is already configured at this point. + + cbi P_TXD-1,TXD ;TXD pin as input ldi temp,(1<