From 3c3744f11ae4402e060b58d5002894749105e954 Mon Sep 17 00:00:00 2001 From: Leo Date: Fri, 2 Jul 2010 13:49:13 +0000 Subject: [PATCH] added Atmega8 support added a Makefile git-svn-id: svn://cu.loc/avr-cpm/trunk@4 57430480-672e-4586-8877-bcf8adbbf3b7 --- avrcpm/avr/Makefile | 104 ++++ avrcpm/avr/z80.asm | 1100 +++++++++++++++++++++++-------------------- avrcpm/avr/z80.hex | 402 ++++++++-------- 3 files changed, 896 insertions(+), 710 deletions(-) create mode 100644 avrcpm/avr/Makefile diff --git a/avrcpm/avr/Makefile b/avrcpm/avr/Makefile new file mode 100644 index 0000000..27b3b0c --- /dev/null +++ b/avrcpm/avr/Makefile @@ -0,0 +1,104 @@ +# AVR-ASM Makefile, derived from the WinAVR template (which +# is public domain), believed to be neutral to any flavor of "make" +# (GNU make, BSD make, SysV make) + +MCU = atmega8 +F_CPU = 12288000 +#BAUD = 38400 +BAUD = 57600 +DRAM_DQ_ORDER = 1 + +TARGET = z80 +ASRC = z80.asm + +# Place -D or -U options here +CDEFS = -DF_CPU=$(F_CPU) -DBAUD=$(BAUD) -D$(MCU) -DDRAM_DQ_ORDER=$(DRAM_DQ_ORDER) + +WINEPATH = C:/Programme/Atmel/AVR\ Tools/AvrAssembler2 +DEFS = $(WINEPATH)/Appnotes + +AS = wine $(WINEPATH)/avrasm2.exe +ASFLAGS = -I $(DEFS) $(CDEFS) + +# Programming support using avrdude. Settings and variables. + +AVRDUDE_PROGRAMMER = dragon_isp +AVRDUDE_PORT = usb + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE_COUNTER = -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_NO_VERIFY = -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_VERBOSE = -v -v + +AVRDUDE_BASIC = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) +AVRDUDE_FLAGS = $(AVRDUDE_BASIC) $(AVRDUDE_NO_VERIFY) $(AVRDUDE_VERBOSE) $(AVRDUDE_ERASE_COUNTER) + +AVRDUDE = avrdude +REMOVE = rm -f +MV = mv -f + + +# Define all listing files. +LST = $(ASRC:.asm=.lst) + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_ASFLAGS = $(ASFLAGS) + +# Default target. +all: hex lst + +hex: $(TARGET).hex +eep: $(TARGET).eep +lst: $(TARGET).lst +map: $(TARGET).map + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + +flash: $(TARGET).hex + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) + +eeprom: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_EEPROM) + + + +.SUFFIXES: .hex .eep .lst + +%.hex: %.asm + $(AS) $(ALL_ASFLAGS) -fI -o $@ $< + +%.lst: %.asm + @$(AS) $(ALL_ASFLAGS) -v0 -f- -l $@ $< + +%.map: %.asm + $(AS) $(ALL_ASFLAGS) -v0 -f- -m $@ $< + +tags: $(SRC) $(ASRC) + ctags $(SRC) $(ASRC) + + + +# Target: clean project. +clean: + $(REMOVE) $(TARGET).hex $(TARGET).eep $(TARGET).obj $(TARGET).map $(TARGET).lst + + +.PHONY: all hex eep lst map program flash eeprom tags clean + diff --git a/avrcpm/avr/z80.asm b/avrcpm/avr/z80.asm index 6e8d57b..9911e8c 100755 --- a/avrcpm/avr/z80.asm +++ b/avrcpm/avr/z80.asm @@ -17,10 +17,39 @@ ; along with this program. If not, see . -;FUSE_H=0xDF -;FUSE_L=0xF7 -.include "m88def.inc" -;device ATmega88 +#if defined atmega8 + .include "m8def.inc" + +#elif defined atmega48 + .include "m48def.inc" +#else /* default */ + .include "m88def.inc" + ;FUSE_H=0xDF + ;FUSE_L=0xF7 +#endif + +#ifndef F_CPU + #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ +#endif +#ifndef BAUD + #define BAUD 38400 /* console baud rate */ +#endif + +; +.equ UBRR_VAL = ((F_CPU+BAUD*8)/(BAUD*16)-1) ; clever rounding + +#define REFR_RATE 64000 /* dram refresh rate. most drams need 1/15.6µs */ +#define REFR_PRE 8 /* timer prescale factor */ +#define REFR_CS 0x02 /* timer clock select for 1/8 */ +#define REFR_CNT F_CPU / REFR_RATE / REFR_PRE + + +#if defined __ATmega8__ + .equ refr_vect = OC2addr +#else + .equ refr_vect = OC2Aaddr +#endif + .equ MMC_DEBUG = 0 .equ INS_DEBUG = 0 @@ -44,6 +73,7 @@ .equ ram_a6 = 6 .equ ram_a7 = 7 + ;Port B .equ ram_a4 = 0 .equ ram_a3 = 1 @@ -105,21 +135,20 @@ ;SRAM +.dseg ;Sector buffer for 512 byte reads/writes from/to SD-card -.equ sectbuff = 0x200 +sectbuff: + .byte 512 + + +.cseg .org 0 rjmp start ; reset vector - nop ; ext int 0 - nop ; ext int 1 - nop ; pcint0 - nop ; pcint1 - nop ; pcint2 - nop ; wdt +.org refr_vect rjmp refrint ; tim2cmpa - nop ; tim2cmpb - nop ; tim2ovf +.org INT_VECTORS_SIZE start: ldi temp,low(RAMEND) ; top of memory out SPL,temp ; init stack pointer @@ -128,13 +157,23 @@ start: ; - Kill wdt wdr +#if defined __ATmega8__ + ldi temp,0 + out MCUCSR,temp + + ldi temp,(1<HL | -;|EX [SP],xx|------|Exchange |[SP]<->xx | -;|EX AF,AF' |------|Exchange |AF<->AF' | -;|EX DE,HL |------|Exchange |DE<->HL | -;|EXX |------|Exchange |qq<->qq' (except AF)| -;|HALT |------|Halt | | -;|IM n |------|Interrupt Mode | (n=0,1,2)| -;|IN A,[n] |------|Input |A=[n] | -;|IN r,[C] |***P0-|Input |r=[C] | -;|INC r |***V0-|Increment |r=r+1 | -;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 | -;|INC xx |------|Increment |xx=xx+1 | -;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 | -;|INC ss |------|Increment |ss=ss+1 | -;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1| -;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 | -;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1| -;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 | -;|JP [HL] |------|Unconditional Jump |PC=[HL] | -;|JP [xx] |------|Unconditional Jump |PC=[xx] | -;|JP nn |------|Unconditional Jump |PC=nn | -;|JP cc,nn |------|Conditional Jump |If cc JP | -;|JR e |------|Unconditional Jump |PC=PC+e | -;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)| -;|LD dst,src|------|Load |dst=src | -;|LD A,i |**0*0-|Load |A=i (i=I,R)| -;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# | -;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 | -;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# | -;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 | -;|NEG |***V1*|Negate |A=-A | -;|NOP |------|No Operation | | -;|OR s |***P00|Logical inclusive OR |A=Avs | -;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 | -;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 | -;|OUT [C],r |------|Output |[C]=r | -;|OUT [n],A |------|Output |[n]=A | -;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1| -;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1| -;|POP xx |------|Pop |xx=[SP]+ | -;|POP qq |------|Pop |qq=[SP]+ | -;|PUSH xx |------|Push |-[SP]=xx | -;|PUSH qq |------|Push |-[SP]=qq | -;|RES b,m |------|Reset bit |m=m&{~2^b} | -;|RET |------|Return |PC=[SP]+ | -;|RET cc |------|Conditional Return |If cc RET | -;|RETI |------|Return from Interrupt|PC=[SP]+ | -;|RETN |------|Return from NMI |PC=[SP]+ | -;|RL m |**0P0*|Rotate Left |m={CY,m}<- | -;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- | -;|RLC m |**0P0*|Rotate Left Circular |m=m<- | -;|RLCA |--0-0*|Rotate Left Circular |A=A<- | -;---------------------------------------------------------------- -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;|----------+------+---------------------+----------------------| -;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##| -;|RR m |**0P0*|Rotate Right |m=->{CY,m} | -;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} | -;|RRC m |**0P0*|Rotate Right Circular|m=->m | -;|RRCA |--0-0*|Rotate Right Circular|A=->A | -;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##| -;|RST p |------|Restart | (p=0H,8H,10H,...,38H)| -;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY | -;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY | -;|SCF |--0-01|Set Carry Flag |CY=1 | -;|SET b,m |------|Set bit |m=mv{2^b} | -;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 | -;|SRA m |**0P0*|Shift Right Arith. |m=m/2 | -;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} | -;|SUB s |***V1*|Subtract |A=A-s | -;|XOR s |***P00|Logical Exclusive OR |A=Axs | -;|----------+------+--------------------------------------------| -;| F |-*01? |Flag unaffected/affected/reset/set/unknown | -;| S |S |Sign flag (Bit 7) | -;| Z | Z |Zero flag (Bit 6) | -;| HC | H |Half Carry flag (Bit 4) | -;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) | -;| N | N |Add/Subtract flag (Bit 1) | -;| CY | C|Carry flag (Bit 0) | -;|-----------------+--------------------------------------------| -;| n |Immediate addressing | -;| nn |Immediate extended addressing | -;| e |Relative addressing (PC=PC+2+offset) | -;| [nn] |Extended addressing | -;| [xx+d] |Indexed addressing | -;| r |Register addressing | -;| [rr] |Register indirect addressing | -;| |Implied addressing | -;| b |Bit addressing | -;| p |Modified page zero addressing (see RST) | -;|-----------------+--------------------------------------------| -;|DEFB n(,...) |Define Byte(s) | -;|DEFB 'str'(,...) |Define Byte ASCII string(s) | -;|DEFS nn |Define Storage Block | -;|DEFW nn(,...) |Define Word(s) | -;|-----------------+--------------------------------------------| -;| A B C D E |Registers (8-bit) | -;| AF BC DE HL |Register pairs (16-bit) | -;| F |Flag register (8-bit) | -;| I |Interrupt page address register (8-bit) | -;| IX IY |Index registers (16-bit) | -;| PC |Program Counter register (16-bit) | -;| R |Memory Refresh register | -;| SP |Stack Pointer register (16-bit) | -;|-----------------+--------------------------------------------| -;| b |One bit (0 to 7) | -;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) | -;| d |One-byte expression (-128 to +127) | -;| dst |Destination s, ss, [BC], [DE], [HL], [nn] | -;| e |One-byte expression (-126 to +129) | -;| m |Any register r, [HL] or [xx+d] | -;| n |One-byte expression (0 to 255) | -;| nn |Two-byte expression (0 to 65535) | -;| pp |Register pair BC, DE, IX or SP | -;| qq |Register pair AF, BC, DE or HL | -;| qq' |Alternative register pair AF, BC, DE or HL | -;| r |Register A, B, C, D, E, H or L | -;| rr |Register pair BC, DE, IY or SP | -;| s |Any register r, value n, [HL] or [xx+d] | -;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] | -;| ss |Register pair BC, DE, HL or SP | -;| xx |Index register IX or IY | -;|-----------------+--------------------------------------------| -;| + - * / ^ |Add/subtract/multiply/divide/exponent | -;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR | -;| <- -> |Rotate left/right | -;| [ ] |Indirect addressing | -;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement| -;| { } |Combination of operands | -;| # |Also BC=BC-1,DE=DE-1 | -;| ## |Only lower 4 bits of accumulator A used | -;---------------------------------------------------------------- - +;---------------------------------------------------------------- +;| | +;| Zilog | +;| | +;| ZZZZZZZ 88888 000 | +;| Z 8 8 0 0 | +;| Z 8 8 0 0 0 | +;| Z 88888 0 0 0 | +;| Z 8 8 0 0 0 | +;| Z 8 8 0 0 | +;| ZZZZZZZ 88888 000 | +;| | +;| Z80 MICROPROCESSOR Instruction Set Summary | +;| | +;---------------------------------------------------------------- +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;|----------+------+---------------------+----------------------| +;|ADC A,s |***V0*|Add with Carry |A=A+s+CY | +;|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY | +;|ADD A,s |***V0*|Add |A=A+s | +;|ADD HL,ss |--?-0*|Add |HL=HL+ss | +;|ADD IX,pp |--?-0*|Add |IX=IX+pp | +;|ADD IY,rr |--?-0*|Add |IY=IY+rr | +;|AND s |***P00|Logical AND |A=A&s | +;|BIT b,m |?*1?0-|Test Bit |m&{2^b} | +;|CALL cc,nn|------|Conditional Call |If cc CALL | +;|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn | +;|CCF |--?-0*|Complement Carry Flag|CY=~CY | +;|CP s |***V1*|Compare |A-s | +;|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1| +;|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0| +;|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1| +;|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0| +;|CPL |--1-1-|Complement |A=~A | +;|DAA |***P-*|Decimal Adjust Acc. |A=BCD format | +;|DEC s |***V1-|Decrement |s=s-1 | +;|DEC xx |------|Decrement |xx=xx-1 | +;|DEC ss |------|Decrement |ss=ss-1 | +;|DI |------|Disable Interrupts | | +;|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 | +;|EI |------|Enable Interrupts | | +;|EX [SP],HL|------|Exchange |[SP]<->HL | +;|EX [SP],xx|------|Exchange |[SP]<->xx | +;|EX AF,AF' |------|Exchange |AF<->AF' | +;|EX DE,HL |------|Exchange |DE<->HL | +;|EXX |------|Exchange |qq<->qq' (except AF)| +;|HALT |------|Halt | | +;|IM n |------|Interrupt Mode | (n=0,1,2)| +;|IN A,[n] |------|Input |A=[n] | +;|IN r,[C] |***P0-|Input |r=[C] | +;|INC r |***V0-|Increment |r=r+1 | +;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 | +;|INC xx |------|Increment |xx=xx+1 | +;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 | +;|INC ss |------|Increment |ss=ss+1 | +;|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1| +;|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 | +;|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1| +;|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 | +;|JP [HL] |------|Unconditional Jump |PC=[HL] | +;|JP [xx] |------|Unconditional Jump |PC=[xx] | +;|JP nn |------|Unconditional Jump |PC=nn | +;|JP cc,nn |------|Conditional Jump |If cc JP | +;|JR e |------|Unconditional Jump |PC=PC+e | +;|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)| +;|LD dst,src|------|Load |dst=src | +;|LD A,i |**0*0-|Load |A=i (i=I,R)| +;|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# | +;|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 | +;|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# | +;|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 | +;|NEG |***V1*|Negate |A=-A | +;|NOP |------|No Operation | | +;|OR s |***P00|Logical inclusive OR |A=Avs | +;|OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 | +;|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 | +;|OUT [C],r |------|Output |[C]=r | +;|OUT [n],A |------|Output |[n]=A | +;|OUTD |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1| +;|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1| +;|POP xx |------|Pop |xx=[SP]+ | +;|POP qq |------|Pop |qq=[SP]+ | +;|PUSH xx |------|Push |-[SP]=xx | +;|PUSH qq |------|Push |-[SP]=qq | +;|RES b,m |------|Reset bit |m=m&{~2^b} | +;|RET |------|Return |PC=[SP]+ | +;|RET cc |------|Conditional Return |If cc RET | +;|RETI |------|Return from Interrupt|PC=[SP]+ | +;|RETN |------|Return from NMI |PC=[SP]+ | +;|RL m |**0P0*|Rotate Left |m={CY,m}<- | +;|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- | +;|RLC m |**0P0*|Rotate Left Circular |m=m<- | +;|RLCA |--0-0*|Rotate Left Circular |A=A<- | +;---------------------------------------------------------------- +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;|----------+------+---------------------+----------------------| +;|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##| +;|RR m |**0P0*|Rotate Right |m=->{CY,m} | +;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} | +;|RRC m |**0P0*|Rotate Right Circular|m=->m | +;|RRCA |--0-0*|Rotate Right Circular|A=->A | +;|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##| +;|RST p |------|Restart | (p=0H,8H,10H,...,38H)| +;|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY | +;|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY | +;|SCF |--0-01|Set Carry Flag |CY=1 | +;|SET b,m |------|Set bit |m=mv{2^b} | +;|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 | +;|SRA m |**0P0*|Shift Right Arith. |m=m/2 | +;|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} | +;|SUB s |***V1*|Subtract |A=A-s | +;|XOR s |***P00|Logical Exclusive OR |A=Axs | +;|----------+------+--------------------------------------------| +;| F |-*01? |Flag unaffected/affected/reset/set/unknown | +;| S |S |Sign flag (Bit 7) | +;| Z | Z |Zero flag (Bit 6) | +;| HC | H |Half Carry flag (Bit 4) | +;| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) | +;| N | N |Add/Subtract flag (Bit 1) | +;| CY | C|Carry flag (Bit 0) | +;|-----------------+--------------------------------------------| +;| n |Immediate addressing | +;| nn |Immediate extended addressing | +;| e |Relative addressing (PC=PC+2+offset) | +;| [nn] |Extended addressing | +;| [xx+d] |Indexed addressing | +;| r |Register addressing | +;| [rr] |Register indirect addressing | +;| |Implied addressing | +;| b |Bit addressing | +;| p |Modified page zero addressing (see RST) | +;|-----------------+--------------------------------------------| +;|DEFB n(,...) |Define Byte(s) | +;|DEFB 'str'(,...) |Define Byte ASCII string(s) | +;|DEFS nn |Define Storage Block | +;|DEFW nn(,...) |Define Word(s) | +;|-----------------+--------------------------------------------| +;| A B C D E |Registers (8-bit) | +;| AF BC DE HL |Register pairs (16-bit) | +;| F |Flag register (8-bit) | +;| I |Interrupt page address register (8-bit) | +;| IX IY |Index registers (16-bit) | +;| PC |Program Counter register (16-bit) | +;| R |Memory Refresh register | +;| SP |Stack Pointer register (16-bit) | +;|-----------------+--------------------------------------------| +;| b |One bit (0 to 7) | +;| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) | +;| d |One-byte expression (-128 to +127) | +;| dst |Destination s, ss, [BC], [DE], [HL], [nn] | +;| e |One-byte expression (-126 to +129) | +;| m |Any register r, [HL] or [xx+d] | +;| n |One-byte expression (0 to 255) | +;| nn |Two-byte expression (0 to 65535) | +;| pp |Register pair BC, DE, IX or SP | +;| qq |Register pair AF, BC, DE or HL | +;| qq' |Alternative register pair AF, BC, DE or HL | +;| r |Register A, B, C, D, E, H or L | +;| rr |Register pair BC, DE, IY or SP | +;| s |Any register r, value n, [HL] or [xx+d] | +;| src |Source s, ss, [BC], [DE], [HL], nn, [nn] | +;| ss |Register pair BC, DE, HL or SP | +;| xx |Index register IX or IY | +;|-----------------+--------------------------------------------| +;| + - * / ^ |Add/subtract/multiply/divide/exponent | +;| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR | +;| <- -> |Rotate left/right | +;| [ ] |Indirect addressing | +;| [ ]+ -[ ] |Indirect addressing auto-increment/decrement| +;| { } |Combination of operands | +;| # |Also BC=BC-1,DE=DE-1 | +;| ## |Only lower 4 bits of accumulator A used | +;---------------------------------------------------------------- + ;ToDo: Parity at more instructions... @@ -1962,14 +2048,14 @@ opjumps: do_op_nop: ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|INC r |***V0-|Increment |r=r+1 | -;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 | -;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 | -; -; OK +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|INC r |***V0-|Increment |r=r+1 | +;|INC [HL] |***V0-|Increment |[HL]=[HL]+1 | +;|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 | +; +; OK do_op_inc: andi z_flags, (1<A | -; -; OK +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|RRCA |--0-0*|Rotate Right Circular|A=->A | +; +; OK do_op_rrc: ;Rotate Right Cyclical. All bits move 1 to the ;right, the lsb becomes c and msb. @@ -2072,12 +2158,12 @@ do_op_rrc: do_op_rrc_noc: ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} | -; -; OK +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +;|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} | +; +; OK do_op_rr: ;Rotate Right. All bits move 1 to the right, the lsb ;becomes c, c becomes msb. @@ -2091,11 +2177,11 @@ do_op_rr: bld z_flags,ZFL_C ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -; -; Not yet checked +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +; +; Not yet checked do_op_rl: ;Rotate Left. All bits move 1 to the left, the msb ;becomes c, c becomes lsb. @@ -2109,11 +2195,11 @@ do_op_rl: bld z_flags,ZFL_C ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -; -; Not yet checked +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +; +; Not yet checked do_op_adda: ldi z_flags,0 add opl,z_a @@ -2133,11 +2219,11 @@ adda_no_s: bld z_flags,ZFL_C ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -; -; Not yet checked +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +; +; Not yet checked do_op_adca: clc sbrc z_flags,ZFL_C @@ -2158,11 +2244,11 @@ do_op_adca: andi z_flags,~(1< todo rcall do_op_inv @@ -2343,40 +2429,40 @@ do_op_da: ret -;---------------------------------------------------------------- -;|Mnemonic |SZHPNC|Description |Notes | -;---------------------------------------------------------------- -; -; Not yet checked +;---------------------------------------------------------------- +;|Mnemonic |SZHPNC|Description |Notes | +;---------------------------------------------------------------- +; +; Not yet checked do_op_scf: ori z_flags,(1<