-?const: jp 0 ; return console input status\r
-?conin: jp 0 ; return console input character\r
-?cono: jp 0 ; send console output character\r
-?list: jp 0 ; send list output character\r
-?auxo: jp 0 ; send auxiliary output character\r
-?auxi: jp 0 ; return auxiliary input character\r
+as0init:\r
+ ld hl,initab0\r
+ jp ioiniml\r
+\r
+as1init:\r
+ ld hl,initab1\r
+ jp ioiniml\r
+\r
+\r
+ ld a,M_MPBT\r
+ out0 (cntlb1),a\r
+ ld a,M_RE + M_TE + M_MOD2 ;Rx/Tx enable\r
+ out0 (cntla1),a\r
+ ld a,M_RIE\r
+ out0 (stat1),a ;Enable rx interrupts\r
+\r
+ ret ;\r
+\r
+\r
+initab0:\r
+ db 1,stat0,0 ;Disable rx/tx interrupts\r
+ ;Enable baud rate generator\r
+ db 1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS\r
+ db 2,astc0l,low 28, high 28\r
+ db 1,cntlb0,M_MPBT ;No MP Mode, X16\r
+ db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
+ db 0\r
+\r
+initab1:\r
+ db 1,stat1,0 ;Disable rx/tx ints, disable CTS1\r
+ db 1,asext1,M_BRGMOD ;Enable baud rate generator\r
+ db 2,astc1l,low 3, high 3\r
+ db 1,cntlb1,M_MPBT ;No MP Mode, X16\r
+ db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r
+ db 0\r
+\r
+;-------------------------------------------------------------------------------\r
+\r
+ioiniml:\r
+ push bc\r
+ xor a\r
+ioml_lp:\r
+ ld b,(hl)\r
+ inc hl\r
+ cp b\r
+ jr z,ioml_e\r
+\r
+ ld c,(hl)\r
+ inc hl\r
+ otimr\r
+ jr ioml_lp\r
+ioml_e:\r
+ pop bc\r
+ ret\r
+\r
+;-------------------------------------------------------------------------------\r
+\r
+as0ista:\r
+ in0 a,(stat0)\r
+ rlca\r
+ sbc a,a\r
+ ret\r
+\r
+as1ista:\r
+ in0 a,(stat1)\r
+ rlca\r
+ sbc a,a\r
+ ret\r
+\r
+as0inp:\r
+ in0 a,(stat0)\r
+ rlca\r
+ jr nc,as0inp\r
+ in0 a,rdr0\r
+ ret\r
+\r
+as1inp:\r
+ in0 a,(stat1)\r
+ rlca\r
+ jr nc,as1inp\r
+ in0 a,rdr1\r
+ ret\r
+\r
+as0out:\r
+ in0 a,(stat0)\r
+ and M_TDRE\r
+ jr z,as0out\r
+ out0 (tdr0),c\r
+ ld a,c\r
+ ret\r
+\r
+as1out:\r
+ in0 a,(stat1)\r
+ and M_TDRE\r
+ jr z,as1out\r
+ out0 (tdr1),c\r
+ ld a,c\r
+ ret\r
+\r
+;-------------------------------------------------------------------------------\r
+\r
+\r
+csio_rx_tmp: db 0ffh\r
+\r
+csio_ista:\r
+ ld hl,csio_rx_tmp\r
+ ld a,(hl)\r
+ cp 0ffh\r
+ jr nz,csist_1\r
+ ld a,01\r
+ call csio_wr\r
+ call csio_rd\r
+ call csio_rd\r
+ ld (hl),a\r
+ sub a,0ffh\r
+ ret z\r
+csist_1:\r
+ or 0ffh\r
+ ret\r
+\r
+csio_inp:\r
+ ld hl,csio_rx_tmp\r
+ ld a,(hl)\r
+ ld (hl),0ffh\r
+ cp 0ffh\r
+ ret nz\r
+csin_1:\r
+ ld a,01\r
+ call csio_wr\r
+ call csio_rd\r
+ call csio_rd\r
+ cp 0ffh\r
+ jr z,csin_1\r
+ ret\r
+\r
+csio_rd:\r
+ ld a,M_CSIO_RE\r
+ call csio_cmd_wait\r
+ in0 a,(trdr)\r
+ ret\r
+\r
+csio_out:\r
+ ld a,02\r
+ call csio_wr\r
+ call csio_rd\r
+ call csio_rd\r
+ or a\r
+ jr z,csio_out\r
+\r
+ ld a,c\r
+ inc a ;ff..02 --> 00..03\r
+ cp 04h\r
+ jr nc,csout_1\r
+ ld a,00h\r
+ call csio_wr\r
+csout_1:\r
+ ld a,c\r
+csio_wr:\r
+ out0 (trdr),a\r
+ ld a,M_CSIO_TE\r
+csio_cmd_wait:\r
+ out0 (cntr),a\r
+cswr_wait:\r
+ in0 a,(cntr)\r
+ and M_CSIO_TE+M_CSIO_RE\r
+ jr nz,cswr_wait\r
+ ret\r
+\r
+ endif ; CPM\r
+\r
+;-------------------------------------------------------------------------------\r