From dfd599a0a08f4aaabb0553c944eea38e82ef9da1 Mon Sep 17 00:00:00 2001 From: Leo C Date: Thu, 23 May 2019 10:18:17 +0200 Subject: [PATCH] Add iobyte and console i/o drivers. WIP; Make CP/M or standalone version --- Makefile | 28 ++++-- ddt180.z80 | 247 +++++++++++++++++++++++++++++++++++++++++++++-- filter-unref.awk | 219 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 479 insertions(+), 15 deletions(-) diff --git a/Makefile b/Makefile index 0bf356d..0d11916 100644 --- a/Makefile +++ b/Makefile @@ -1,17 +1,23 @@ # Build ddt180.com from ddt180.z80 +CPM := 0 + PROG := ddt180 +OBJ := $(PROG).rel -SRC := $(PROG).z80 +ifneq ($(CPM),0) + SUFFIX := z80 +else + SUFFIX := 180 +endif EXTRA_DIST := autorevision.cache version.inc -OBJ := $(SRC:.z80=.rel) DIST_NAME = $(PROG)_$(VERS).zip PREFIX = $(PROG)_$(VERS) -ASM := zxcc slrz80.com +ASM := zxcc slr$(SUFFIX).com LINK := zxcc link80.com CP := cp RM := rm -f @@ -23,7 +29,10 @@ AS_OPT := MFSX .phony: all all: $(PROG).com +.intermediate: $(PROG).180 +$(PROG).180: $(PROG).z80 + cp $< $@ $(PROG).com: $(PROG).prl Makefile @# Remove the PRL header record (256 bytes) @@ -32,7 +41,7 @@ $(PROG).com: $(PROG).prl Makefile $(PROG).prl: $(OBJ) $(LINK) -'$(PROG)[op]' -$(PROG).rel: version.inc +$(PROG).rel: config.inc version.inc $(foreach X,$(subst =,:=,$(subst ",,$(filter VCS_%,\ $(shell autorevision -t sh -o $(CURDIR)/autorevision.cache)))),$(eval $X)) @@ -57,6 +66,11 @@ version.inc: autorevision.cache db '$(VERS)'\r\n\ endm\r\n\032" > $@ +config.inc: Makefile + @printf "\ + CPM equ $(CPM)\r\n\ + \032" > $@ + .phony: dist dist: $(PROG).com version.inc $(GIT) archive --format=zip --prefix=$(PREFIX)/ -9 -o $(DIST_NAME) HEAD^{tree} @@ -67,10 +81,10 @@ dist: $(PROG).com version.inc .phony: clean clean: - rm -f $(PROG).com *.rel *.lst *.prl + rm -f $(PROG).com $(PROG).180 *.rel *.lst *.prl .SUFFIXES: -.SUFFIXES: .z80 .rel .prl +.SUFFIXES: .z80 .180 .rel .prl define cpm-asm = @@ -83,5 +97,5 @@ else awk -f filter-unref.awk ddt180.lst; fi ; \ exit $${ERROR} endef -%.rel %lst: %.z80 +%.rel %lst: %.$(SUFFIX) @$(cpm-asm) diff --git a/ddt180.z80 b/ddt180.z80 index 6f701ff..ef1dd6c 100644 --- a/ddt180.z80 +++ b/ddt180.z80 @@ -7,6 +7,8 @@ ; - Cut the .PRL header (first 256 byte) end rename the result to DDTZ.COM. + maclib config.inc + ; Some greneral definitions BS equ 08h @@ -43,11 +45,6 @@ di_or_ei: ;ints enabled/disabled while ddtz is running nop ret -convec: -const: jp cist ; return console input status -conin: jp ci ; return console input character -conout: jp co ; send console output character - ;------------------------------------------------------------------------------- signon: @@ -142,6 +139,8 @@ reloc_next: init:: LD SP,stack + if CPM + ld hl,(1) ;wboot addr ld de,convec ex de,hl @@ -156,7 +155,26 @@ vini_l: ld (hl),d inc hl djnz vini_l + else + xor a + dec a + daa ; Z80: 099H, x180+: 0F9H + cp 99h ; Result on 180 type cpus is F9 here. Thanks Hitachi + jr z,ini_z80 + xor a + call cinit + ld a,1 + call cinit + jr ini_sign +ini_z80: +; if ... +; .printx Error: Not yet implemented! +; db "Stop +; endif + endif ; CPM + +ini_sign: ld hl,signon call pstr ld hl,ddtz_base @@ -185,11 +203,224 @@ l0093h: ;------------------------------------------------------------------------------- -cist: -ci: -co: + if CPM + +convec: +const: jp 0 ; return console input status +conin: jp 0 ; return console input character +conout: jp 0 ; send console output character + + else + + include z180reg.inc + +iobyte equ 3 + +max_device equ 3 + +;------------------------------------------------------------------------------- + +; init device +cinit: ; a = device + call vector_io_0 + dw as0init + dw rret + dw rret + dw rret + +; character input status +const: ; return a != 0 if character waiting + call vector_io + dw as0ista + dw null$status + dw csio_ista + dw null$status + +; character input +conin: ; return a = input char + call vector_io + dw as0inp + dw null$input + dw csio_inp + dw null$input + +; character output +conout: ; c = output char + call vector_io + dw as0out + dw rret + dw csio_out + dw rret + +;------------------------------------------------------------------------------- + +vector_io: + ld a,(iobyte) +vector_io_0: + pop hl + cp max_device + jr c,exist + ld a,max_device ; use null device if a >= max$device +exist: + call add_hl_a2 + ld a,(hl) + inc hl + ld h,(hl) + ld l,a + jp (hl) + +;------------------------------------------------------------------------------- + +null$input: + ld a,1Ah +rret: + ret +ret$true: + or 0FFh + ret + +null$status: + xor a + ret + +;------------------------------------------------------------------------------- +; +; TC = (f PHI /(2*baudrate*Clock_mode)) - 2 +; +; TC = (f PHI / (32 * baudrate)) - 2 +; +; Init Serial I/O for console input and output (ASCI1) +; + + + +as0init: + ld hl,initab0 + jp ioiniml + +as1init: + ld hl,initab1 + jp ioiniml + + + ld a,M_MPBT + out0 (cntlb1),a + ld a,M_RE + M_TE + M_MOD2 ;Rx/Tx enable + out0 (cntla1),a + ld a,M_RIE + out0 (stat1),a ;Enable rx interrupts + + ret ; + + +initab0: + db 1,stat0,0 ;Disable rx/tx interrupts + ;Enable baud rate generator + db 1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS + db 2,astc0l,low 28, high 28 + db 1,cntlb0,M_MPBT ;No MP Mode, X16 + db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1 + db 0 + +initab1: + db 1,stat1,0 ;Disable rx/tx ints, disable CTS1 + db 1,asext1,M_BRGMOD ;Enable baud rate generator + db 2,astc1l,low 3, high 3 + db 1,cntlb1,M_MPBT ;No MP Mode, X16 + db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1 + db 0 + +;------------------------------------------------------------------------------- + +ioiniml: + push bc + xor a +ioml_lp: + ld b,(hl) + inc hl + cp b + jr z,ioml_e + + ld c,(hl) + inc hl + otimr + jr ioml_lp +ioml_e: + pop bc + ret + +;------------------------------------------------------------------------------- + +as0ista: + in0 a,(stat0) + rlca + sbc a,a + ret + +as1ista: + in0 a,(stat1) + rlca + sbc a,a + ret + +as0inp: + in0 a,(stat0) + rlca + jr nc,as0inp + in0 a,rdr0 + ret + +as1inp: + in0 a,(stat1) + rlca + jr nc,as1inp + in0 a,rdr1 + ret + +as0out: + in0 a,(stat0) + and M_TDRE + jr z,as0out + out0 (tdr0),c + ld a,c + ret + +as1out: + in0 a,(stat1) + and M_TDRE + jr z,as1out + out0 (tdr1),c + ld a,c + ret + +;------------------------------------------------------------------------------- + +csio_ista: +csio_inp: +csio_out: + xor a + ret + + + ld a,0ffh +do_csio: + push af + call csio_wait_te + pop af + out0 (trdr),a + ld a,M_CSIO_TE + out0 (cntr),a + call csio_wait_te + in0 a,(trdr) + ret + +csio_wait_te: + in0 a,(cntr) + and M_CSIO_TE + jr nz,csio_wait_te ret + endif ; CPM ;------------------------------------------------------------------------------- diff --git a/filter-unref.awk b/filter-unref.awk index 3188f4a..3fe784f 100644 --- a/filter-unref.awk +++ b/filter-unref.awk @@ -83,6 +83,225 @@ BEGIN { ign["I_TST"] = 1 ign["I_TSTIO"] = 1 ign["I_XOR"] = 1 + + ign["ALTC"] = 1 + ign["ALTE"] = 1 + ign["ASTC0H"] = 1 + ign["ASTC1H"] = 1 + ign["BBR"] = 1 + ign["BCR0H"] = 1 + ign["BCR0L"] = 1 + ign["BCR1H"] = 1 + ign["BCR1L"] = 1 + ign["BREAK"] = 1 + ign["BREAKEN"] = 1 + ign["BRGMOD"] = 1 + ign["CBAR"] = 1 + ign["CBR"] = 1 + ign["CCR"] = 1 + ign["CKA1D"] = 1 + ign["CMR"] = 1 + ign["CSIO_EF"] = 1 + ign["CSIO_EIE"] = 1 + ign["CSIO_RE"] = 1 + ign["CSIO_SS0"] = 1 + ign["CSIO_SS1"] = 1 + ign["CSIO_SS2"] = 1 + ign["CSIO_TE"] = 1 + ign["CTS"] = 1 + ign["CTS0DIS"] = 1 + ign["CTS1E"] = 1 + ign["CYC0"] = 1 + ign["CYC1"] = 1 + ign["DAR0B"] = 1 + ign["DAR0H"] = 1 + ign["DAR0L"] = 1 + ign["DCD0"] = 1 + ign["DCD0DIS"] = 1 + ign["DCNTL"] = 1 + ign["DE0"] = 1 + ign["DE1"] = 1 + ign["DIE0"] = 1 + ign["DIE1"] = 1 + ign["DIM0"] = 1 + ign["DIM1"] = 1 + ign["DM0"] = 1 + ign["DM1"] = 1 + ign["DME"] = 1 + ign["DMODE"] = 1 + ign["DMS0"] = 1 + ign["DMS1"] = 1 + ign["DR"] = 1 + ign["DSTAT"] = 1 + ign["EFR"] = 1 + ign["FE"] = 1 + ign["FRC"] = 1 + ign["IAR1B"] = 1 + ign["IAR1H"] = 1 + ign["IAR1L"] = 1 + ign["ICR"] = 1 + ign["IL"] = 1 + ign["IOC"] = 1 + ign["IOSTP"] = 1 + ign["ITC"] = 1 + ign["ITE0"] = 1 + ign["ITE1"] = 1 + ign["ITE2"] = 1 + ign["IV$ASCI0"] = 1 + ign["IV$ASCI1"] = 1 + ign["IV$CSIO"] = 1 + ign["IV$DMA0"] = 1 + ign["IV$DMA1"] = 1 + ign["IV$INT1"] = 1 + ign["IV$INT2"] = 1 + ign["IV$PRT0"] = 1 + ign["IV$PRT1"] = 1 + ign["IWI0"] = 1 + ign["IWI1"] = 1 + ign["LNC"] = 1 + ign["M1E"] = 1 + ign["M1TE"] = 1 + ign["MAR1B"] = 1 + ign["MAR1H"] = 1 + ign["MAR1L"] = 1 + ign["MMOD"] = 1 + ign["MOD0"] = 1 + ign["MOD1"] = 1 + ign["MOD2"] = 1 + ign["MP"] = 1 + ign["MPBR"] = 1 + ign["MPBT"] = 1 + ign["MPE"] = 1 + ign["MWI0"] = 1 + ign["MWI1"] = 1 + ign["M_ALTC"] = 1 + ign["M_ALTE"] = 1 + ign["M_BREAK"] = 1 + ign["M_BREAKEN"] = 1 + ign["M_CKA1D"] = 1 + ign["M_CSIO_EF"] = 1 + ign["M_CSIO_EIE"] = 1 + ign["M_CSIO_RE"] = 1 + ign["M_CSIO_SS0"] = 1 + ign["M_CSIO_SS1"] = 1 + ign["M_CSIO_SS2"] = 1 + ign["M_CTS"] = 1 + ign["M_CTS1E"] = 1 + ign["M_CYC0"] = 1 + ign["M_CYC1"] = 1 + ign["M_DCD0"] = 1 + ign["M_DE0"] = 1 + ign["M_DE1"] = 1 + ign["M_DIE0"] = 1 + ign["M_DIE1"] = 1 + ign["M_DIM0"] = 1 + ign["M_DIM1"] = 1 + ign["M_DM0"] = 1 + ign["M_DM1"] = 1 + ign["M_DME"] = 1 + ign["M_DMS0"] = 1 + ign["M_DMS1"] = 1 + ign["M_DR"] = 1 + ign["M_EFR"] = 1 + ign["M_FE"] = 1 + ign["M_IOC"] = 1 + ign["M_IOSTP"] = 1 + ign["M_ITE0"] = 1 + ign["M_ITE1"] = 1 + ign["M_ITE2"] = 1 + ign["M_IWI"] = 1 + ign["M_LNC"] = 1 + ign["M_M1E"] = 1 + ign["M_M1TE"] = 1 + ign["M_MMOD"] = 1 + ign["M_MOD0"] = 1 + ign["M_MOD1"] = 1 + ign["M_MP"] = 1 + ign["M_MPBR"] = 1 + ign["M_MPE"] = 1 + ign["M_MWI"] = 1 + ign["M_NCD"] = 1 + ign["M_NDWE0"] = 1 + ign["M_NDWE1"] = 1 + ign["M_OVRN"] = 1 + ign["M_PEO"] = 1 + ign["M_PERR"] = 1 + ign["M_PS"] = 1 + ign["M_RDRF"] = 1 + ign["M_REFE"] = 1 + ign["M_REFW"] = 1 + ign["M_REQ1SEL0"] = 1 + ign["M_REQ1SEL1"] = 1 + ign["M_REQ1SEL2"] = 1 + ign["M_RTS0"] = 1 + ign["M_SENDBREAK"] = 1 + ign["M_SM0"] = 1 + ign["M_SM1"] = 1 + ign["M_SS"] = 1 + ign["M_TDE0"] = 1 + ign["M_TDE1"] = 1 + ign["M_TIE"] = 1 + ign["M_TIE0"] = 1 + ign["M_TIE1"] = 1 + ign["M_TIF0"] = 1 + ign["M_TIF1"] = 1 + ign["M_TOC0"] = 1 + ign["M_TOC1"] = 1 + ign["M_TRAP"] = 1 + ign["M_UFO"] = 1 + ign["M_X1"] = 1 + ign["M_X2CM"] = 1 + ign["NCD"] = 1 + ign["NDWE0"] = 1 + ign["NDWE1"] = 1 + ign["OMCR"] = 1 + ign["OVRN"] = 1 + ign["PEO"] = 1 + ign["PERR"] = 1 + ign["PS"] = 1 + ign["RCR"] = 1 + ign["RDRF"] = 1 + ign["RE"] = 1 + ign["REFE"] = 1 + ign["REFW"] = 1 + ign["REQ1SEL0"] = 1 + ign["REQ1SEL1"] = 1 + ign["REQ1SEL2"] = 1 + ign["RIE"] = 1 + ign["RLDR0H"] = 1 + ign["RLDR0L"] = 1 + ign["RLDR1H"] = 1 + ign["RLDR1L"] = 1 + ign["RTS0"] = 1 + ign["SAR0B"] = 1 + ign["SAR0H"] = 1 + ign["SAR0L"] = 1 + ign["SENDBREAK"] = 1 + ign["SM0"] = 1 + ign["SM1"] = 1 + ign["SS0"] = 1 + ign["SS1"] = 1 + ign["SS2"] = 1 + ign["TCR"] = 1 + ign["TDE0"] = 1 + ign["TDE1"] = 1 + ign["TDRE"] = 1 + ign["TE"] = 1 + ign["TIE"] = 1 + ign["TIE0"] = 1 + ign["TIE1"] = 1 + ign["TIF0"] = 1 + ign["TIF1"] = 1 + ign["TMDR0H"] = 1 + ign["TMDR0L"] = 1 + ign["TMDR1H"] = 1 + ign["TMDR1L"] = 1 + ign["TOC0"] = 1 + ign["TOC1"] = 1 + ign["TRAP"] = 1 + ign["UFO"] = 1 + ign["X1"] = 1 + ign["X2CM"] = 1 } /\x1A/ { exit } -- 2.39.2