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Version 1.2.1: added APPLE_PROTOCOL to irsnd
[irmp.git] / irsnd.c
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4225a882 1/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
2 * @file irsnd.c\r
3 *\r
4 * Copyright (c) 2010 Frank Meyer - frank(at)fli4l.de\r
5 *\r
46dd89b7 6 * $Id: irsnd.c,v 1.9 2010/04/28 14:58:59 fm Exp $\r
5481e9cd 7 *\r
4225a882 8 * This program is free software; you can redistribute it and/or modify\r
9 * it under the terms of the GNU General Public License as published by\r
10 * the Free Software Foundation; either version 2 of the License, or\r
11 * (at your option) any later version.\r
12 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
13 */\r
14\r
15#ifdef unix // test/debug on linux/unix\r
16#include <stdio.h>\r
17#include <unistd.h>\r
18#include <stdlib.h>\r
19#include <string.h>\r
20#include <inttypes.h>\r
21\r
22#define DEBUG\r
23#define F_CPU 8000000L\r
24\r
25#else // not unix:\r
26\r
27#ifdef WIN32 // test/debug on windows\r
28#include <stdio.h>\r
29#define F_CPU 8000000L\r
30typedef unsigned char uint8_t;\r
31typedef unsigned short uint16_t;\r
32#define DEBUG\r
33\r
34#else\r
35\r
36#ifdef CODEVISION\r
37 #define COM2A0 6\r
38 #define WGM21 1\r
39 #define CS20 0\r
40#else\r
41 #include <inttypes.h>\r
42 #include <avr/io.h>\r
43 #include <util/delay.h>\r
44 #include <avr/pgmspace.h>\r
45#endif // CODEVISION\r
46\r
47#endif // WIN32\r
48#endif // unix\r
49\r
50#include "irmp.h"\r
46dd89b7 51#include "irsndconfig.h"\r
4225a882 52#include "irsnd.h"\r
53\r
4225a882 54#define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)\r
55#define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)\r
56#define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)\r
57#define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)\r
58#define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)\r
59#define SIRCS_REPETITION_LEN (uint16_t)(F_INTERRUPTS * SIRCS_REPETITION_TIME + 0.5) // use uint16_t!\r
60\r
61#define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)\r
62#define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)\r
63#define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)\r
64#define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)\r
65#define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)\r
66\r
67#define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)\r
68#define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)\r
69#define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)\r
70#define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)\r
71#define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)\r
72\r
73#define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)\r
74#define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)\r
75#define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)\r
76#define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)\r
77#define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)\r
78\r
79#define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)\r
80#define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)\r
81#define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)\r
82#define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)\r
83#define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)\r
84\r
85#define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
86#define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)\r
87\r
88#define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)\r
89#define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)\r
90#define RC6_TOGGLE_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_TOGGLE_BIT_TIME + 0.5)\r
91#define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)\r
92\r
93#define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)\r
94#define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)\r
95#define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)\r
96#define DENON_REPETITION_LEN (uint16_t)(F_INTERRUPTS * DENON_REPETITION_TIME + 0.5) // use uint16_t!\r
97\r
98#define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)\r
99#define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)\r
100#define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)\r
101#define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)\r
102#define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)\r
103\r
104#define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)\r
105#define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)\r
106#define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)\r
107#define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)\r
108#define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)\r
109#define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)\r
110#define NUBERT_REPETITION_LEN (uint16_t)(F_INTERRUPTS * NUBERT_REPETITION_TIME + 0.5) // use uint16_t!\r
111\r
5481e9cd 112#define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)\r
113#define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)\r
114#define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)\r
115#define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)\r
116#define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)\r
117#define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)\r
118#define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)\r
119#define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)\r
120#define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)\r
121#define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)\r
122#define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)\r
123\r
4225a882 124#define IRSND_FREQ_32_KHZ (uint8_t) ((F_CPU / 32000 / 2) - 1)\r
125#define IRSND_FREQ_36_KHZ (uint8_t) ((F_CPU / 36000 / 2) - 1)\r
126#define IRSND_FREQ_38_KHZ (uint8_t) ((F_CPU / 38000 / 2) - 1)\r
127#define IRSND_FREQ_40_KHZ (uint8_t) ((F_CPU / 40000 / 2) - 1)\r
128#define IRSND_FREQ_56_KHZ (uint8_t) ((F_CPU / 56000 / 2) - 1)\r
5481e9cd 129#define IRSND_FREQ_455_KHZ (uint8_t) ((F_CPU / 455000 / 2) - 1)\r
4225a882 130\r
131static volatile uint8_t irsnd_busy;\r
132static volatile uint8_t irsnd_protocol;\r
133static volatile uint8_t irsnd_buffer[5];\r
134static volatile uint8_t irsnd_is_on = FALSE;\r
135\r
136/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
137 * Switch PWM on\r
138 * @details Switches PWM on with a narrow spike on all 3 channels -> leds glowing\r
139 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
140 */\r
141static void\r
142irsnd_on (void)\r
143{\r
144 if (! irsnd_is_on)\r
145 {\r
146#ifndef DEBUG\r
147#if defined (__AVR_ATmega32__)\r
148 TCCR2 |= (1<<COM20)|(1<<WGM21); // = 0x42: toggle OC2A on compare match, clear Timer 2 at compare match OCR2A\r
149#else\r
150 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // = 0x42: toggle OC2A on compare match, clear Timer 2 at compare match OCR2A\r
46dd89b7 151#endif // __AVR...\r
4225a882 152#endif // DEBUG\r
153 irsnd_is_on = TRUE;\r
154 }\r
155}\r
156\r
157/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
158 * Switch PWM off\r
159 * @details Switches PWM off\r
160 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
161 */\r
162static void\r
163irsnd_off (void)\r
164{\r
165 if (irsnd_is_on)\r
166 {\r
167#ifndef DEBUG\r
168#if defined (__AVR_ATmega32__)\r
169 TCCR2 &= ~(1<<COM20); // normal port operation, OC2A disconnected.\r
170#else\r
171 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.\r
46dd89b7 172#endif // __AVR...\r
4225a882 173 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
174#endif // DEBUG\r
175 irsnd_is_on = FALSE;\r
176 }\r
177}\r
178\r
179/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
180 * Set PWM frequency\r
181 * @details sets pwm frequency\r
182 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
183 */\r
184static void\r
185irsnd_set_freq (uint8_t freq)\r
186{\r
187#ifndef DEBUG\r
188#if defined (__AVR_ATmega32__)\r
189 OCR2 = freq;\r
190#else\r
191 OCR2A = freq;\r
46dd89b7 192#endif // __AVR...\r
4225a882 193#endif // DEBUG\r
194}\r
195\r
196/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
197 * Initialize the PWM\r
198 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels\r
199 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
200 */\r
201void\r
202irsnd_init (void)\r
203{\r
204#ifndef DEBUG\r
205 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
206 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
207\r
208#if defined (__AVR_ATmega32__)\r
209 TCCR2 = (1<<WGM21); // CTC mode\r
210 TCCR2 |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r
211#else\r
212 TCCR2A = (1<<WGM21); // CTC mode\r
213 TCCR2B |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r
46dd89b7 214#endif // __AVR... \r
4225a882 215\r
216 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
217#endif // DEBUG\r
218}\r
219\r
220uint8_t\r
221irsnd_is_busy (void)\r
222{\r
223 return irsnd_busy;\r
224}\r
225\r
226static uint16_t\r
227bitsrevervse (uint16_t x, uint8_t len)\r
228{\r
229 uint16_t xx = 0;\r
230\r
231 while(len)\r
232 {\r
233 xx <<= 1;\r
234 if (x & 1)\r
235 {\r
236 xx |= 1;\r
237 }\r
238 x >>= 1;\r
239 len--;\r
240 }\r
241 return xx;\r
242}\r
243\r
244\r
245uint8_t\r
246irsnd_send_data (IRMP_DATA * irmp_data_p)\r
247{\r
248#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
249 static uint8_t toggle_bit_recs80;\r
250#endif\r
251#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
252 static uint8_t toggle_bit_recs80ext;\r
253#endif\r
254#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
255 static uint8_t toggle_bit_rc5;\r
256#endif\r
257 uint16_t address;\r
258 uint16_t command;\r
259\r
260 while (irsnd_busy)\r
261 {\r
262 ;\r
263 }\r
264\r
265 irsnd_protocol = irmp_data_p->protocol;\r
266\r
267 switch (irsnd_protocol)\r
268 {\r
269#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
270 case IRMP_SIRCS_PROTOCOL:\r
271 {\r
272 command = bitsrevervse (irmp_data_p->command, SIRCS_MINIMUM_DATA_LEN);\r
273\r
4225a882 274 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
275 irsnd_buffer[1] = (command & 0x000F) << 4; // CCCC0000\r
276 irsnd_busy = TRUE;\r
277 break;\r
278 }\r
279#endif\r
280#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
281 case IRMP_NEC_PROTOCOL:\r
46dd89b7 282 case IRMP_APPLE_PROTOCOL:\r
4225a882 283 {\r
284 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);\r
285 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);\r
286\r
4225a882 287 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
288 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
289 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
46dd89b7 290\r
291 if (irsnd_protocol == IRMP_APPLE_PROTOCOL)\r
292 {\r
293 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with fix bitmask instead of inverted command\r
294 irsnd_buffer[3] = 0x8B; // 10001011\r
295 }\r
296 else\r
297 {\r
298 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc\r
299 }\r
300\r
4225a882 301 irsnd_busy = TRUE;\r
302 break;\r
303 }\r
304#endif\r
305#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
306 case IRMP_SAMSUNG_PROTOCOL:\r
307 {\r
308 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
309 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);\r
310\r
4225a882 311 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
312 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
313 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC\r
314 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc\r
315 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000\r
316 irsnd_busy = TRUE;\r
317 break;\r
318 }\r
319 case IRMP_SAMSUNG32_PROTOCOL:\r
320 {\r
321 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);\r
322 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);\r
323\r
4225a882 324 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
325 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
326 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC\r
327 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC\r
328 irsnd_busy = TRUE;\r
329 break;\r
330 }\r
331#endif\r
332#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
333 case IRMP_MATSUSHITA_PROTOCOL:\r
334 {\r
335 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);\r
336 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);\r
337\r
4225a882 338 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
339 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA\r
340 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA\r
341 irsnd_busy = TRUE;\r
342 break;\r
343 }\r
344#endif\r
345#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
346 case IRMP_RECS80_PROTOCOL:\r
347 {\r
348 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x40;\r
349\r
4225a882 350 irsnd_buffer[0] = 0x80 | toggle_bit_recs80 | ((irmp_data_p->address & 0x0007) << 3) |\r
351 ((irmp_data_p->command & 0x0038) >> 3); // STAAACCC\r
352 irsnd_buffer[1] = (irmp_data_p->command & 0x07) << 5; // CCC00000\r
353 irsnd_busy = TRUE;\r
354 break;\r
355 }\r
356#endif\r
357#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
358 case IRMP_RECS80EXT_PROTOCOL:\r
359 {\r
360 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;\r
361\r
4225a882 362 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |\r
363 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC\r
364 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000\r
365 irsnd_busy = TRUE;\r
366 break;\r
367 }\r
368#endif\r
369#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
370 case IRMP_RC5_PROTOCOL:\r
371 {\r
372 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;\r
373\r
4225a882 374 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |\r
375 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC\r
376 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000\r
377 irsnd_busy = TRUE;\r
378 break;\r
379 }\r
380#endif\r
381#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
382 case IRMP_DENON_PROTOCOL:\r
383 {\r
4225a882 384 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC\r
385 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC0\r
386 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAACCC\r
387 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // CCCCCCC0\r
388 irsnd_busy = TRUE;\r
389 break;\r
390 }\r
391#endif\r
392#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
393 case IRMP_NUBERT_PROTOCOL:\r
394 {\r
4225a882 395 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC\r
396 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000\r
397 irsnd_busy = TRUE;\r
398 break;\r
399 }\r
5481e9cd 400#endif\r
401#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
402 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
403 {\r
5481e9cd 404 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC\r
405 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC\r
406 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000\r
407 irsnd_busy = TRUE;\r
408 break;\r
409 }\r
4225a882 410#endif\r
411 default:\r
412 {\r
413 break;\r
414 }\r
415 }\r
416\r
417 return irsnd_busy;\r
418}\r
419\r
420/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
421 * ISR routine\r
422 * @details ISR routine, called 10000 times per second\r
423 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
424 */\r
425uint8_t\r
426irsnd_ISR (void)\r
427{\r
428 static uint8_t current_bit = 0xFF;\r
429 static uint8_t pulse_counter;\r
430 static uint8_t pause_counter;\r
431 static uint8_t startbit_pulse_len;\r
432 static uint8_t startbit_pause_len;\r
433 static uint8_t pulse_1_len;\r
434 static uint8_t pause_1_len;\r
435 static uint8_t pulse_0_len;\r
436 static uint8_t pause_0_len;\r
437 static uint8_t has_stop_bit;\r
438 static uint8_t new_frame = TRUE;\r
439 static uint8_t complete_data_len;\r
5481e9cd 440 static uint8_t n_frames; // number of repetitions\r
441 static uint8_t frame_counter; // repetition counter\r
4225a882 442 static uint16_t repetition_pause; // pause before repetition, uint16_t!\r
443 static uint16_t repetition_pause_counter; // pause before repetition, uint16_t!\r
5481e9cd 444#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
445 static uint8_t last_bit_value;\r
446#endif\r
447 static uint8_t pulse_len = 0xFF;\r
448 static uint8_t pause_len = 0xFF;\r
4225a882 449\r
450 if (irsnd_busy)\r
451 {\r
452 if (current_bit == 0xFF && new_frame) // start of transmission...\r
453 {\r
5481e9cd 454 if (frame_counter > 0)\r
4225a882 455 {\r
456 repetition_pause_counter++;\r
457\r
458 if (repetition_pause_counter >= repetition_pause)\r
459 {\r
460 repetition_pause_counter = 0;\r
461\r
462 if (irsnd_protocol == IRMP_DENON_PROTOCOL)\r
463 {\r
464 current_bit = 16;\r
465 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;\r
466 }\r
467 }\r
468 else\r
469 {\r
470#ifdef DEBUG\r
471 if (irsnd_is_on)\r
472 {\r
473 putchar ('0');\r
474 }\r
475 else\r
476 {\r
477 putchar ('1');\r
478 }\r
479#endif\r
480 return irsnd_busy;\r
481 }\r
482 }\r
483 else\r
484 {\r
5481e9cd 485 pulse_counter = 0;\r
486 pause_counter = 0;\r
487\r
4225a882 488 switch (irsnd_protocol)\r
489 {\r
490#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
491 case IRMP_SIRCS_PROTOCOL:\r
492 {\r
493 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;\r
494 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN;\r
495 pulse_1_len = SIRCS_1_PULSE_LEN;\r
496 pause_1_len = SIRCS_PAUSE_LEN;\r
497 pulse_0_len = SIRCS_0_PULSE_LEN;\r
498 pause_0_len = SIRCS_PAUSE_LEN;\r
499 has_stop_bit = SIRCS_STOP_BIT;\r
500 complete_data_len = SIRCS_MINIMUM_DATA_LEN;\r
5481e9cd 501 n_frames = SIRCS_REPETITION_CNT;\r
4225a882 502 repetition_pause = SIRCS_REPETITION_LEN; // 45 ms pause\r
503 irsnd_set_freq (IRSND_FREQ_40_KHZ);\r
504 break;\r
505 }\r
506#endif\r
507#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
508 case IRMP_NEC_PROTOCOL:\r
509 {\r
510 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;\r
511 startbit_pause_len = NEC_START_BIT_PAUSE_LEN;\r
512 pulse_1_len = NEC_PULSE_LEN;\r
513 pause_1_len = NEC_1_PAUSE_LEN;\r
514 pulse_0_len = NEC_PULSE_LEN;\r
515 pause_0_len = NEC_0_PAUSE_LEN;\r
516 has_stop_bit = NEC_STOP_BIT;\r
517 complete_data_len = NEC_COMPLETE_DATA_LEN;\r
5481e9cd 518 n_frames = 1;\r
4225a882 519 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
520 break;\r
521 }\r
522#endif\r
523#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
524 case IRMP_SAMSUNG_PROTOCOL:\r
525 {\r
526 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
527 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN;\r
528 pulse_1_len = SAMSUNG_PULSE_LEN;\r
529 pause_1_len = SAMSUNG_1_PAUSE_LEN;\r
530 pulse_0_len = SAMSUNG_PULSE_LEN;\r
531 pause_0_len = SAMSUNG_0_PAUSE_LEN;\r
532 has_stop_bit = SAMSUNG_STOP_BIT;\r
533 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;\r
5481e9cd 534 n_frames = 1;\r
4225a882 535 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
536 break;\r
537 }\r
538\r
539 case IRMP_SAMSUNG32_PROTOCOL:\r
540 {\r
541 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;\r
542 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN;\r
543 pulse_1_len = SAMSUNG_PULSE_LEN;\r
544 pause_1_len = SAMSUNG_1_PAUSE_LEN;\r
545 pulse_0_len = SAMSUNG_PULSE_LEN;\r
546 pause_0_len = SAMSUNG_0_PAUSE_LEN;\r
547 has_stop_bit = SAMSUNG_STOP_BIT;\r
548 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;\r
5481e9cd 549 n_frames = 1;\r
4225a882 550 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
551 break;\r
552 }\r
553#endif\r
554#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
555 case IRMP_MATSUSHITA_PROTOCOL:\r
556 {\r
557 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;\r
558 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN;\r
559 pulse_1_len = MATSUSHITA_PULSE_LEN;\r
560 pause_1_len = MATSUSHITA_1_PAUSE_LEN;\r
561 pulse_0_len = MATSUSHITA_PULSE_LEN;\r
562 pause_0_len = MATSUSHITA_0_PAUSE_LEN;\r
563 has_stop_bit = MATSUSHITA_STOP_BIT;\r
564 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;\r
5481e9cd 565 n_frames = 1;\r
4225a882 566 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
567 break;\r
568 }\r
569#endif\r
570#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
571 case IRMP_RECS80_PROTOCOL:\r
572 {\r
573 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;\r
574 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN;\r
575 pulse_1_len = RECS80_PULSE_LEN;\r
576 pause_1_len = RECS80_1_PAUSE_LEN;\r
577 pulse_0_len = RECS80_PULSE_LEN;\r
578 pause_0_len = RECS80_0_PAUSE_LEN;\r
579 has_stop_bit = RECS80_STOP_BIT;\r
580 complete_data_len = RECS80_COMPLETE_DATA_LEN;\r
5481e9cd 581 n_frames = 1;\r
4225a882 582 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
583 break;\r
584 }\r
585#endif\r
586#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
587 case IRMP_RECS80EXT_PROTOCOL:\r
588 {\r
589 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;\r
590 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN;\r
591 pulse_1_len = RECS80EXT_PULSE_LEN;\r
592 pause_1_len = RECS80EXT_1_PAUSE_LEN;\r
593 pulse_0_len = RECS80EXT_PULSE_LEN;\r
594 pause_0_len = RECS80EXT_0_PAUSE_LEN;\r
595 has_stop_bit = RECS80EXT_STOP_BIT;\r
596 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;\r
5481e9cd 597 n_frames = 1;\r
4225a882 598 irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
599 break;\r
600 }\r
601#endif\r
602#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
603 case IRMP_RC5_PROTOCOL:\r
604 {\r
605 startbit_pulse_len = RC5_BIT_LEN;\r
606 startbit_pause_len = RC5_BIT_LEN;\r
607 pulse_1_len = RC5_BIT_LEN;\r
608 pause_1_len = RC5_BIT_LEN;\r
609 pulse_0_len = RC5_BIT_LEN;\r
610 pause_0_len = RC5_BIT_LEN;\r
611 has_stop_bit = RC5_STOP_BIT;\r
612 complete_data_len = RC5_COMPLETE_DATA_LEN;\r
5481e9cd 613 n_frames = 1;\r
4225a882 614 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
615 break;\r
616 }\r
617#endif\r
618#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
619 case IRMP_DENON_PROTOCOL:\r
620 {\r
621 startbit_pulse_len = 0x00;\r
622 startbit_pause_len = 0x00;\r
623 pulse_1_len = DENON_PULSE_LEN;\r
624 pause_1_len = DENON_1_PAUSE_LEN;\r
625 pulse_0_len = DENON_PULSE_LEN;\r
626 pause_0_len = DENON_0_PAUSE_LEN;\r
627 has_stop_bit = DENON_STOP_BIT;\r
628 complete_data_len = DENON_COMPLETE_DATA_LEN;\r
5481e9cd 629 n_frames = 2;\r
4225a882 630 repetition_pause = DENON_REPETITION_LEN; // 65 ms pause after 1st frame (15 bits)\r
631 irsnd_set_freq (IRSND_FREQ_32_KHZ);\r
632 break;\r
633 }\r
634#endif\r
635#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
636 case IRMP_NUBERT_PROTOCOL:\r
637 {\r
638 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;\r
639 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN;\r
640 pulse_1_len = NUBERT_1_PULSE_LEN;\r
641 pause_1_len = NUBERT_1_PAUSE_LEN;\r
642 pulse_0_len = NUBERT_0_PULSE_LEN;\r
643 pause_0_len = NUBERT_0_PAUSE_LEN;\r
644 has_stop_bit = NUBERT_STOP_BIT;\r
645 complete_data_len = NUBERT_COMPLETE_DATA_LEN;\r
5481e9cd 646 n_frames = 2;\r
4225a882 647 repetition_pause = NUBERT_REPETITION_LEN; // 35 ms pause\r
648 irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
649 break;\r
650 }\r
5481e9cd 651#endif\r
652#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
653 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
654 {\r
655 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;\r
656 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN;\r
657 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;\r
658 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN;\r
659 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;\r
660 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN;\r
661 has_stop_bit = BANG_OLUFSEN_STOP_BIT;\r
662 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;\r
663 n_frames = 1;\r
664 last_bit_value = 0;\r
665 irsnd_set_freq (IRSND_FREQ_455_KHZ);\r
666 break;\r
667 }\r
4225a882 668#endif\r
669 default:\r
670 {\r
671 irsnd_busy = FALSE;\r
672 break;\r
673 }\r
674 }\r
675 }\r
676 }\r
677\r
678 if (irsnd_busy)\r
679 {\r
680 new_frame = FALSE;\r
681 switch (irsnd_protocol)\r
682 {\r
683#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1\r
684 case IRMP_SIRCS_PROTOCOL:\r
685#endif\r
686#if IRSND_SUPPORT_NEC_PROTOCOL == 1\r
687 case IRMP_NEC_PROTOCOL:\r
688#endif\r
689#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
690 case IRMP_SAMSUNG_PROTOCOL:\r
691 case IRMP_SAMSUNG32_PROTOCOL:\r
692#endif\r
693#if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1\r
694 case IRMP_MATSUSHITA_PROTOCOL:\r
695#endif\r
696#if IRSND_SUPPORT_RECS80_PROTOCOL == 1\r
697 case IRMP_RECS80_PROTOCOL:\r
698#endif\r
699#if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1\r
700 case IRMP_RECS80EXT_PROTOCOL:\r
701#endif\r
702#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
703 case IRMP_DENON_PROTOCOL:\r
704#endif\r
705#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
706 case IRMP_NUBERT_PROTOCOL:\r
5481e9cd 707#endif\r
708#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
709 case IRMP_BANG_OLUFSEN_PROTOCOL:\r
4225a882 710#endif\r
711 {\r
5481e9cd 712 if (pulse_counter == 0)\r
4225a882 713 {\r
5481e9cd 714 if (current_bit == 0xFF) // send start bit\r
715 {\r
716 pulse_len = startbit_pulse_len;\r
717 pause_len = startbit_pause_len;\r
718 }\r
719 else if (current_bit < complete_data_len) // send n'th bit\r
4225a882 720 {\r
5481e9cd 721#if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1\r
722 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)\r
4225a882 723 {\r
5481e9cd 724 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits\r
725 {\r
726 pulse_len = SAMSUNG_PULSE_LEN;\r
727 pause_len = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ?\r
728 SAMSUNG_1_PAUSE_LEN : SAMSUNG_0_PAUSE_LEN;\r
729 }\r
730 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)\r
731 {\r
732 pulse_len = SAMSUNG_PULSE_LEN;\r
733 pause_len = SAMSUNG_START_BIT_PAUSE_LEN;\r
734 }\r
735 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit\r
736 {\r
737 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !\r
738\r
739 pulse_len = SAMSUNG_PULSE_LEN;\r
740 pause_len = (irsnd_buffer[cur_bit / 8] & (1<<(7-(cur_bit % 8)))) ?\r
741 SAMSUNG_1_PAUSE_LEN : SAMSUNG_0_PAUSE_LEN;\r
742 }\r
4225a882 743 }\r
5481e9cd 744 else\r
745#endif\r
746\r
747#if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1\r
748 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)\r
4225a882 749 {\r
5481e9cd 750 if (current_bit == 0) // send 2nd start bit\r
751 {\r
752 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
753 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN;\r
754 }\r
755 else if (current_bit == 1) // send 3rd start bit\r
756 {\r
757 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;\r
758 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN;\r
759 }\r
760 else if (current_bit == 2) // send 4th start bit\r
761 {\r
762 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;\r
763 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN;\r
764 }\r
765 else if (current_bit == 19) // send trailer bit\r
766 {\r
767 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
768 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN;\r
769 }\r
770 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit\r
771 {\r
772 uint8_t cur_bit_value = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? 1 : 0;\r
773 pulse_len = BANG_OLUFSEN_PULSE_LEN;\r
774\r
775 if (cur_bit_value == last_bit_value)\r
776 {\r
777 pause_len = BANG_OLUFSEN_R_PAUSE_LEN;\r
778 }\r
779 else\r
780 {\r
781 pause_len = cur_bit_value ? BANG_OLUFSEN_1_PAUSE_LEN : BANG_OLUFSEN_0_PAUSE_LEN;\r
782 last_bit_value = cur_bit_value;\r
783 }\r
784 }\r
4225a882 785 }\r
5481e9cd 786 else\r
787#endif\r
788 if (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8))))\r
4225a882 789 {\r
5481e9cd 790 pulse_len = pulse_1_len;\r
791 pause_len = pause_1_len;\r
792 }\r
793 else\r
794 {\r
795 pulse_len = pulse_0_len;\r
796 pause_len = pause_0_len;\r
4225a882 797 }\r
798 }\r
5481e9cd 799 else if (has_stop_bit) // send stop bit\r
4225a882 800 {\r
801 pulse_len = pulse_0_len;\r
4225a882 802\r
5481e9cd 803 if (frame_counter < n_frames)\r
804 {\r
805 pause_len = pause_0_len;\r
806 }\r
807 else\r
808 {\r
809 pause_len = 255; // last frame: pause of 255\r
810 }\r
4225a882 811 }\r
812 }\r
813\r
814 if (pulse_counter < pulse_len)\r
815 {\r
816 if (pulse_counter == 0)\r
817 {\r
818 irsnd_on ();\r
819 }\r
820 pulse_counter++;\r
821 }\r
822 else if (pause_counter < pause_len)\r
823 {\r
824 if (pause_counter == 0)\r
825 {\r
826 irsnd_off ();\r
827 }\r
828 pause_counter++;\r
829 }\r
830 else\r
831 {\r
832 current_bit++;\r
833\r
834 if (current_bit >= complete_data_len + has_stop_bit)\r
835 {\r
836 current_bit = 0xFF;\r
5481e9cd 837 frame_counter++;\r
4225a882 838\r
5481e9cd 839 if (frame_counter == n_frames)\r
4225a882 840 {\r
841 irsnd_busy = FALSE;\r
5481e9cd 842 frame_counter = 0;\r
4225a882 843 }\r
844 new_frame = TRUE;\r
845 }\r
846\r
847 pulse_counter = 0;\r
848 pause_counter = 0;\r
849 }\r
850 break;\r
851 }\r
852#if IRSND_SUPPORT_RC5_PROTOCOL == 1\r
853 case IRMP_RC5_PROTOCOL:\r
854 {\r
855 uint8_t first_pulse;\r
856 uint8_t next_bit = FALSE;\r
857\r
858 if (current_bit == 0xFF) // 1 start bit\r
859 {\r
860 first_pulse = FALSE;\r
861 }\r
862 else // send n'th bit\r
863 {\r
864 first_pulse = (irsnd_buffer[current_bit / 8] & (1<<(7-(current_bit % 8)))) ? FALSE : TRUE;\r
865 }\r
866\r
867 if (first_pulse)\r
868 {\r
869 if (pulse_counter < RC5_BIT_LEN)\r
870 {\r
871 if (pulse_counter == 0)\r
872 {\r
873 irsnd_on ();\r
874 }\r
875 pulse_counter++;\r
876 }\r
877 else if (pause_counter < RC5_BIT_LEN)\r
878 {\r
879 if (pause_counter == 0)\r
880 {\r
881 irsnd_off ();\r
882 }\r
883 pause_counter++;\r
884 }\r
885 else\r
886 {\r
887 next_bit = TRUE;\r
888 }\r
889 }\r
890 else\r
891 {\r
892 if (pause_counter < RC5_BIT_LEN)\r
893 {\r
894 if (pause_counter == 0)\r
895 {\r
896 irsnd_off ();\r
897 }\r
898 pause_counter++;\r
899 }\r
900 else if (pulse_counter < RC5_BIT_LEN)\r
901 {\r
902 if (pulse_counter == 0)\r
903 {\r
904 irsnd_on ();\r
905 }\r
906 pulse_counter++;\r
907 }\r
908 else\r
909 {\r
910 next_bit = TRUE;\r
911 }\r
912 }\r
913\r
914 if (next_bit)\r
915 {\r
916 current_bit++;\r
917\r
918 if (current_bit >= RC5_COMPLETE_DATA_LEN)\r
919 {\r
920 current_bit = 0xFF;\r
921 irsnd_busy = FALSE;\r
922 new_frame = TRUE;\r
923 irsnd_off ();\r
924 }\r
925\r
926 pulse_counter = 0;\r
927 pause_counter = 0;\r
928 }\r
929 break;\r
930 }\r
931#endif // IRSND_SUPPORT_RC5_PROTOCOL\r
932 default:\r
933 {\r
934 irsnd_busy = FALSE;\r
935 break;\r
936 }\r
937 }\r
938 }\r
939 }\r
940\r
941#ifdef DEBUG\r
942 if (irsnd_is_on)\r
943 {\r
944 putchar ('0');\r
945 }\r
946 else\r
947 {\r
948 putchar ('1');\r
949 }\r
950#endif\r
951\r
952 return irsnd_busy;\r
953}\r
954\r
955#ifdef DEBUG\r
956\r
957// main function - for unix/linux + windows only!\r
958// AVR: see main.c!\r
959// Compile it under linux with:\r
960// cc irsnd.c -o irsnd\r
961//\r
962// usage: ./irsnd protocol hex-address hex-command >filename\r
963\r
964int\r
965main (int argc, char ** argv)\r
966{\r
967 int idx;\r
968 int cnt;\r
969 int protocol;\r
970 int address;\r
971 int command;\r
972 int repeat = 1;\r
973 IRMP_DATA irmp_data;\r
974\r
975 if (argc != 4)\r
976 {\r
977 fprintf (stderr, "usage: %s protocol hex-address hex-command > filename\n", argv[0]);\r
978 return 1;\r
979 }\r
980\r
981 if (sscanf (argv[1], "%d", &protocol) == 1 &&\r
982 sscanf (argv[2], "%x", &address) == 1 &&\r
983 sscanf (argv[3], "%x", &command) == 1)\r
984 {\r
985 irmp_data.protocol = protocol;\r
986 irmp_data.address = address;\r
987 irmp_data.command = command;\r
988\r
989 irsnd_init ();\r
990\r
991 for (cnt = 0; cnt < repeat; cnt++)\r
992 {\r
993 (void) irsnd_send_data (&irmp_data);\r
994\r
995 for (idx = 0; idx < 3000; idx++)\r
996 {\r
997 irsnd_ISR ();\r
998 }\r
999 }\r
1000\r
1001 putchar ('\n');\r
1002 }\r
1003 else\r
1004 {\r
1005 fprintf (stderr, "%s: wrong arguments\n", argv[0]);\r
1006 return 1;\r
1007 }\r
1008 return 0;\r
1009}\r
1010\r
1011#endif // DEBUG\r
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)