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4225a882 | 1 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
7365350c | 2 | * irsnd-main-avr.c - demo main module to test IRSND encoder on AVRs\r |
4225a882 | 3 | *\r |
ea29682a | 4 | * Copyright (c) 2010-2016 Frank Meyer - frank(at)fli4l.de\r |
4225a882 | 5 | *\r |
7365350c | 6 | * $Id: irsnd-main-avr.c,v 1.3 2016/09/09 08:01:11 fm Exp $\r |
7 | *\r | |
775fabfa | 8 | * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r |
9 | * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r | |
4225a882 | 10 | *\r |
11 | * This program is free software; you can redistribute it and/or modify\r | |
12 | * it under the terms of the GNU General Public License as published by\r | |
13 | * the Free Software Foundation; either version 2 of the License, or\r | |
14 | * (at your option) any later version.\r | |
15 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
16 | */\r | |
4225a882 | 17 | #include "irsnd.h"\r |
18 | \r | |
4225a882 | 19 | #ifndef F_CPU\r |
061e654c | 20 | # error F_CPU unknown\r |
4225a882 | 21 | #endif\r |
22 | \r | |
23 | void\r | |
1f54e86c | 24 | timer1_init (void)\r |
4225a882 | 25 | {\r |
476267f4 | 26 | #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r |
b743217b | 27 | OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r |
476267f4 | 28 | TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r |
29 | #else // ATmegaXX:\r | |
30 | OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r | |
31 | TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r | |
1f54e86c | 32 | #endif\r |
4225a882 | 33 | \r |
1f54e86c | 34 | #ifdef TIMSK1\r |
476267f4 | 35 | TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r |
4225a882 | 36 | #else\r |
476267f4 | 37 | TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r |
1f54e86c | 38 | #endif\r |
4225a882 | 39 | }\r |
40 | \r | |
775fabfa | 41 | #ifdef TIM1_COMPA_vect // ATtiny84\r |
42 | #define COMPA_VECT TIM1_COMPA_vect\r | |
43 | #else\r | |
44 | #define COMPA_VECT TIMER1_COMPA_vect // ATmega\r | |
45 | #endif\r | |
46 | \r | |
4225a882 | 47 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
48 | * timer 1 compare handler, called every 1/10000 sec\r | |
49 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
50 | */\r | |
775fabfa | 51 | ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r |
4225a882 | 52 | {\r |
53 | (void) irsnd_ISR(); // call irsnd ISR\r | |
1f54e86c | 54 | // call other timer interrupt routines here...\r |
4225a882 | 55 | }\r |
56 | \r | |
57 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
58 | * MAIN: main routine\r | |
59 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
60 | */\r | |
4225a882 | 61 | int\r |
62 | main (void)\r | |
63 | {\r | |
1f54e86c | 64 | IRMP_DATA irmp_data;\r |
65 | \r | |
775fabfa | 66 | irsnd_init(); // initialize irsnd\r |
67 | timer1_init(); // initialize timer\r | |
68 | sei (); // enable interrupts\r | |
1f54e86c | 69 | \r |
70 | for (;;)\r | |
71 | {\r | |
775fabfa | 72 | irmp_data.protocol = IRMP_NEC_PROTOCOL; // use NEC protocol\r |
73 | irmp_data.address = 0x00FF; // set address to 0x00FF\r | |
74 | irmp_data.command = 0x0001; // set command to 0x0001\r | |
75 | irmp_data.flags = 0; // don't repeat frame\r | |
1f54e86c | 76 | \r |
775fabfa | 77 | irsnd_send_data (&irmp_data, TRUE); // send frame, wait for completion\r |
1f54e86c | 78 | _delay_ms (1000);\r |
79 | }\r | |
4225a882 | 80 | }\r |