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7fe8188d | 1 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r |
4225a882 | 2 | * irsnd.h\r |
3 | *\r | |
7365350c | 4 | * Copyright (c) 2010-2016 Frank Meyer - frank(at)fli4l.de\r |
4225a882 | 5 | *\r |
30d1689d | 6 | * $Id: irsnd.h,v 1.26 2017/02/17 09:13:07 fm Exp $\r |
4225a882 | 7 | *\r |
8 | * This program is free software; you can redistribute it and/or modify\r | |
9 | * it under the terms of the GNU General Public License as published by\r | |
10 | * the Free Software Foundation; either version 2 of the License, or\r | |
11 | * (at your option) any later version.\r | |
12 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
13 | */\r | |
14 | \r | |
08f2dd9d | 15 | #ifndef _IRSND_H_\r |
16 | #define _IRSND_H_\r | |
4225a882 | 17 | \r |
08f2dd9d | 18 | #include "irmpsystem.h"\r |
19 | #ifndef IRSND_USE_AS_LIB\r | |
20 | # include "irsndconfig.h"\r | |
21 | #endif\r | |
9c86ff1a | 22 | \r |
08f2dd9d | 23 | #if defined (ARM_STM32) // STM32\r |
24 | # define _CONCAT(a,b) a##b\r | |
25 | # define CONCAT(a,b) _CONCAT(a,b)\r | |
26 | # define IRSND_PORT CONCAT(GPIO, IRSND_PORT_LETTER)\r | |
27 | # if defined (ARM_STM32L1XX)\r | |
28 | # define IRSND_PORT_RCC CONCAT(RCC_AHBPeriph_GPIO, IRSND_PORT_LETTER)\r | |
29 | # define IRSND_GPIO_AF CONCAT(GPIO_AF_TIM, IRSND_TIMER_NUMBER)\r | |
30 | # elif defined (ARM_STM32F10X)\r | |
31 | # define IRSND_PORT_RCC CONCAT(RCC_APB2Periph_GPIO, IRSND_PORT_LETTER)\r | |
32 | # elif defined (ARM_STM32F4XX)\r | |
33 | # define IRSND_PORT_RCC CONCAT(RCC_AHB1Periph_GPIO, IRSND_PORT_LETTER)\r | |
34 | # define IRSND_GPIO_AF CONCAT(GPIO_AF_TIM, IRSND_TIMER_NUMBER)\r | |
35 | # endif\r | |
36 | # define IRSND_BIT CONCAT(GPIO_Pin_, IRSND_BIT_NUMBER)\r | |
37 | # define IRSND_TIMER CONCAT(TIM, IRSND_TIMER_NUMBER)\r | |
acd29fb9 | 38 | # define IRSND_TIMER_CHANNEL CONCAT(TIM_Channel_, IRSND_TIMER_CHANNEL_NUMBER)\r |
08f2dd9d | 39 | # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r |
40 | # define IRSND_TIMER_RCC CONCAT(RCC_APB1Periph_TIM, IRSND_TIMER_NUMBER)\r | |
41 | # elif (IRSND_TIMER_NUMBER == 1) || ((IRSND_TIMER_NUMBER >= 8) && (IRSND_TIMER_NUMBER <= 11))\r | |
42 | # define IRSND_TIMER_RCC CONCAT(RCC_APB2Periph_TIM, IRSND_TIMER_NUMBER)\r | |
43 | # else\r | |
44 | # error IRSND_TIMER_NUMBER not valid.\r | |
45 | # endif\r | |
46 | # ifndef USE_STDPERIPH_DRIVER\r | |
47 | # warning The STM32 port of IRSND uses the ST standard peripheral drivers which are not enabled in your build configuration.\r | |
48 | # endif\r | |
beda975f | 49 | \r |
54cbcce6 L |
50 | #elif defined (LIBOPENCM3) // STM32 whith libopencm3\r |
51 | # define _CONCAT(a,b) a##b\r | |
52 | # define CONCAT(a,b) _CONCAT(a,b)\r | |
53 | # define IRSND_PORT CONCAT(GPIO, IRSND_PORT_LETTER)\r | |
54 | # define IRSND_PORT_RCC CONCAT(RCC_GPIO, IRSND_PORT_LETTER)\r | |
55 | # define IRSND_BIT CONCAT(GPIO, IRSND_BIT_NUMBER)\r | |
56 | # define IRSND_TIMER CONCAT(TIM, IRSND_TIMER_NUMBER)\r | |
57 | # define IRSND_TIMER_CHANNEL CONCAT(TIM_OC, IRSND_TIMER_CHANNEL_NUMBER)\r | |
58 | # define IRSND_TIMER_ARR TIM_ARR(IRSND_TIMER)\r | |
59 | # define IRSND_TIMER_ARR TIM_ARR(IRSND_TIMER)\r | |
60 | # define IRSND_TIMER_RCC CONCAT(RCC_TIM, IRSND_TIMER_NUMBER)\r | |
61 | \r | |
08f2dd9d | 62 | #elif defined(PIC_C18)\r |
7fe8188d | 63 | \r |
64 | # if defined(__12F1840)\r | |
65 | // Do not change lines below unless you have a different HW. This example is for 12F1840\r | |
66 | // setup macro for PWM used PWM module\r | |
30d1689d | 67 | \r |
7fe8188d | 68 | //~ # define PWMon() TMR2=0,IRSND_PIN=1\r |
69 | //~ # define PWMoff() CCP1CON &=(~0b1100)\r | |
70 | //~ # define PWMon() TMR2ON=1\r | |
71 | //~ # define PWMoff() TMR2ON=0\r | |
30d1689d | 72 | #if defined(IRSND_DEBUG)\r |
df24bb50 | 73 | #define PWMon() LATA0=1\r |
74 | #define PWMoff() LATA0=0\r | |
75 | #define IRSND_PIN LATA0\r | |
7fe8188d | 76 | #else\r |
df24bb50 | 77 | # define PWMon() TMR2=0,CCP1CON |=0b1100\r |
78 | # define PWMoff() CCP1CON &=(~0b1100)\r | |
79 | # define IRSND_PIN RA2\r | |
7fe8188d | 80 | #endif\r |
81 | \r | |
82 | #else\r | |
83 | // Do not change lines below until you have a different HW. Example is for 18F2550/18F4550\r | |
84 | // setup macro for PWM used PWM module\r | |
30d1689d | 85 | # if IRSND_OCx == IRSND_PIC_CCP2\r |
7fe8188d | 86 | # define PWMon() TMR2=0,CCP2CON |=0b1100\r |
87 | # define PWMoff() CCP2CON &=(~0b1100)\r | |
88 | # define IRSND_PIN TRISCbits.TRISC1 // RC1 = PWM2\r | |
30d1689d | 89 | # define SetDCPWM(x) SetDCPWM2(x)\r |
7fe8188d | 90 | # define ClosePWM ClosePWM2\r |
30d1689d | 91 | # define OpenPWM(x) OpenPWM2(x)\r |
7fe8188d | 92 | # endif\r |
30d1689d | 93 | # if IRSND_OCx == IRSND_PIC_CCP1\r |
7fe8188d | 94 | # define PWMon() TMR2=0,CCP1CON |=0b1100\r |
95 | # define PWMoff() CCP1CON &=(~0b1100)\r | |
96 | # define IRSND_PIN TRISCbits.TRISC2 // RC2 = PWM1\r | |
97 | # define SetDCPWM(x) SetDCPWM1(x)\r | |
98 | # define ClosePWM ClosePWM1\r | |
99 | # define OpenPWM(x) OpenPWM1(x)\r | |
30d1689d | 100 | # endif\r |
7fe8188d | 101 | # endif\r |
102 | # endif // PIC_C18\r | |
4225a882 | 103 | \r |
08f2dd9d | 104 | #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 && F_INTERRUPTS < 15000\r |
105 | # warning F_INTERRUPTS too low, SIEMENS protocol disabled (should be at least 15000)\r | |
106 | # undef IRSND_SUPPORT_SIEMENS_PROTOCOL\r | |
107 | # define IRSND_SUPPORT_SIEMENS_PROTOCOL 0\r | |
108 | #endif\r | |
4225a882 | 109 | \r |
fa09ce10 | 110 | #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1 && F_INTERRUPTS < 15000\r |
111 | # warning F_INTERRUPTS too low, A1TVBOX protocol disabled (should be at least 15000)\r | |
112 | # undef IRSND_SUPPORT_A1TVBOX_PROTOCOL\r | |
113 | # define IRSND_SUPPORT_A1TVBOX_PROTOCOL 0\r | |
114 | #endif\r | |
115 | \r | |
e664a9f3 | 116 | #if IRSND_SUPPORT_RECS80_PROTOCOL == 1 && F_INTERRUPTS < 15000\r |
117 | # warning F_INTERRUPTS too low, RECS80 protocol disabled (should be at least 15000)\r | |
08f2dd9d | 118 | # undef IRSND_SUPPORT_RECS80_PROTOCOL\r |
119 | # define IRSND_SUPPORT_RECS80_PROTOCOL 0\r | |
120 | #endif\r | |
4225a882 | 121 | \r |
e664a9f3 | 122 | #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 && F_INTERRUPTS < 15000\r |
123 | # warning F_INTERRUPTS too low, RECS80EXT protocol disabled (should be at least 15000)\r | |
08f2dd9d | 124 | # undef IRSND_SUPPORT_RECS80EXT_PROTOCOL\r |
125 | # define IRSND_SUPPORT_RECS80EXT_PROTOCOL 0\r | |
126 | #endif\r | |
beda975f | 127 | \r |
08f2dd9d | 128 | #if IRSND_SUPPORT_LEGO_PROTOCOL == 1 && F_INTERRUPTS < 20000\r |
129 | # warning F_INTERRUPTS too low, LEGO protocol disabled (should be at least 20000)\r | |
130 | # undef IRSND_SUPPORT_LEGO_PROTOCOL\r | |
131 | # define IRSND_SUPPORT_LEGO_PROTOCOL 0\r | |
132 | #endif\r | |
133 | \r | |
134 | #include "irmpprotocols.h"\r | |
135 | \r | |
136 | #define IRSND_NO_REPETITIONS 0 // no repetitions\r | |
137 | #define IRSND_MAX_REPETITIONS 14 // max # of repetitions\r | |
138 | #define IRSND_ENDLESS_REPETITION 15 // endless repetions\r | |
139 | #define IRSND_REPETITION_MASK 0x0F // lower nibble of flags\r | |
140 | \r | |
95b27043 | 141 | #ifdef __cplusplus\r |
142 | extern "C"\r | |
143 | {\r | |
144 | #endif\r | |
145 | \r | |
08f2dd9d | 146 | extern void irsnd_init (void);\r |
147 | extern uint8_t irsnd_is_busy (void);\r | |
148 | extern uint8_t irsnd_send_data (IRMP_DATA *, uint8_t);\r | |
149 | extern void irsnd_stop (void);\r | |
150 | extern uint8_t irsnd_ISR (void);\r | |
4225a882 | 151 | \r |
f50e01e7 | 152 | #if IRSND_USE_CALLBACK == 1\r |
08f2dd9d | 153 | extern void irsnd_set_callback_ptr (void (*cb)(uint8_t));\r |
f50e01e7 | 154 | #endif // IRSND_USE_CALLBACK == 1\r |
155 | \r | |
95b27043 | 156 | #ifdef __cplusplus\r |
157 | }\r | |
158 | #endif\r | |
159 | \r | |
08f2dd9d | 160 | #endif /* _IRSND_H_ */\r |