]>
Commit | Line | Data |
---|---|---|
1 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
2 | * main.c - demo main module to test irmp decoder\r | |
3 | *\r | |
4 | * Copyright (c) 2009-2013 Frank Meyer - frank(at)fli4l.de\r | |
5 | *\r | |
6 | * $Id: main.c,v 1.18 2014/07/01 07:50:33 fm Exp $\r | |
7 | *\r | |
8 | * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r | |
9 | *\r | |
10 | * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r | |
11 | * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r | |
12 | *\r | |
13 | * This program is free software; you can redistribute it and/or modify\r | |
14 | * it under the terms of the GNU General Public License as published by\r | |
15 | * the Free Software Foundation; either version 2 of the License, or\r | |
16 | * (at your option) any later version.\r | |
17 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
18 | */\r | |
19 | \r | |
20 | #include "irmp.h"\r | |
21 | \r | |
22 | #ifndef F_CPU\r | |
23 | #error F_CPU unkown\r | |
24 | #endif\r | |
25 | \r | |
26 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
27 | * ATMEL AVR part:\r | |
28 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
29 | */\r | |
30 | #if defined (ATMEL_AVR)\r | |
31 | \r | |
32 | void\r | |
33 | timer1_init (void)\r | |
34 | {\r | |
35 | #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r | |
36 | \r | |
37 | #if F_CPU >= 16000000L\r | |
38 | OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r | |
39 | TCCR1 = (1 << CTC1) | (1 << CS12); // switch CTC Mode on, set prescaler to 8\r | |
40 | #else\r | |
41 | OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r | |
42 | TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r | |
43 | #endif\r | |
44 | \r | |
45 | #else // ATmegaXX:\r | |
46 | OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r | |
47 | TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r | |
48 | #endif\r | |
49 | \r | |
50 | #ifdef TIMSK1\r | |
51 | TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r | |
52 | #else\r | |
53 | TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r | |
54 | #endif\r | |
55 | }\r | |
56 | \r | |
57 | #ifdef TIM1_COMPA_vect // ATtiny84\r | |
58 | #define COMPA_VECT TIM1_COMPA_vect\r | |
59 | #else\r | |
60 | #define COMPA_VECT TIMER1_COMPA_vect // ATmega\r | |
61 | #endif\r | |
62 | \r | |
63 | ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r | |
64 | {\r | |
65 | (void) irmp_ISR(); // call irmp ISR\r | |
66 | // call other timer interrupt routines...\r | |
67 | }\r | |
68 | \r | |
69 | int\r | |
70 | main (void)\r | |
71 | {\r | |
72 | IRMP_DATA irmp_data;\r | |
73 | \r | |
74 | irmp_init(); // initialize irmp\r | |
75 | timer1_init(); // initialize timer1\r | |
76 | sei (); // enable interrupts\r | |
77 | \r | |
78 | for (;;)\r | |
79 | {\r | |
80 | if (irmp_get_data (&irmp_data))\r | |
81 | {\r | |
82 | // ir signal decoded, do something here...\r | |
83 | // irmp_data.protocol is the protocol, see irmp.h\r | |
84 | // irmp_data.address is the address/manufacturer code of ir sender\r | |
85 | // irmp_data.command is the command code\r | |
86 | // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r | |
87 | }\r | |
88 | }\r | |
89 | }\r | |
90 | \r | |
91 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
92 | * LM4F120 Launchpad (ARM Cortex M4):\r | |
93 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
94 | */\r | |
95 | #elif defined(STELLARIS_ARM_CORTEX_M4)\r | |
96 | \r | |
97 | void\r | |
98 | timer1_init (void)\r | |
99 | {\r | |
100 | SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r | |
101 | TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r | |
102 | \r | |
103 | TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r | |
104 | IntEnable(INT_TIMER1A);\r | |
105 | TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r | |
106 | TimerEnable(TIMER1_BASE, TIMER_A);\r | |
107 | // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r | |
108 | }\r | |
109 | \r | |
110 | void\r | |
111 | Timer1IntHandler(void) // Timer1 Interrupt Handler\r | |
112 | {\r | |
113 | (void) irmp_ISR(); // call irmp ISR\r | |
114 | // call other timer interrupt routines...\r | |
115 | }\r | |
116 | \r | |
117 | int\r | |
118 | main (void)\r | |
119 | {\r | |
120 | IRMP_DATA irmp_data;\r | |
121 | \r | |
122 | ROM_FPUEnable();\r | |
123 | ROM_FPUStackingEnable();\r | |
124 | ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r | |
125 | \r | |
126 | irmp_init(); // initialize irmp\r | |
127 | timer1_init(); // initialize timer1\r | |
128 | sei (); // enable interrupts\r | |
129 | \r | |
130 | for (;;)\r | |
131 | {\r | |
132 | if (irmp_get_data (&irmp_data))\r | |
133 | {\r | |
134 | // ir signal decoded, do something here...\r | |
135 | // irmp_data.protocol is the protocol, see irmp.h\r | |
136 | // irmp_data.address is the address/manufacturer code of ir sender\r | |
137 | // irmp_data.command is the command code\r | |
138 | // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r | |
139 | }\r | |
140 | }\r | |
141 | }\r | |
142 | \r | |
143 | /*---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
144 | * PIC18F4520 with XC8 compiler:\r | |
145 | *---------------------------------------------------------------------------------------------------------------------------------------------------\r | |
146 | */\r | |
147 | #elif defined (__XC8)\r | |
148 | \r | |
149 | #define _XTAL_FREQ 32000000UL // 32MHz clock\r | |
150 | #define FOSC _XTAL_FREQ\r | |
151 | #define FCY FOSC / 4UL // --> 8MHz\r | |
152 | \r | |
153 | #define BAUDRATE 19200UL\r | |
154 | #define BRG (( FCY 16 BAUDRATE ) -1UL)\r | |
155 | \r | |
156 | #include <stdio.h>\r | |
157 | #include <stdlib.h>\r | |
158 | \r | |
159 | int\r | |
160 | main (void)\r | |
161 | {\r | |
162 | IRMP_DATA irmp_data;\r | |
163 | \r | |
164 | irmp_init(); // initialize irmp\r | |
165 | \r | |
166 | // infinite loop, interrupts will blink PORTD pins and handle UART communications.\r | |
167 | while (1)\r | |
168 | {\r | |
169 | LATBbits.LATB0 = ~LATBbits.LATB0;\r | |
170 | \r | |
171 | if (irmp_get_data (&irmp_data))\r | |
172 | {\r | |
173 | // ir signal decoded, do something here...\r | |
174 | // irmp_data.protocol is the protocol, see irmp.h\r | |
175 | // irmp_data.address is the address/manufacturer code of ir sender\r | |
176 | // irmp_data.command is the command code\r | |
177 | // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r | |
178 | printf("proto %d addr %d cmd %d\n", irmp_data.protocol, irmp_data.address, irmp_data.command );\r | |
179 | }\r | |
180 | }\r | |
181 | }\r | |
182 | \r | |
183 | void interrupt high_priority high_isr(void)\r | |
184 | {\r | |
185 | if (TMR2IF)\r | |
186 | {\r | |
187 | TMR2IF = 0; // clear Timer 0 interrupt flag\r | |
188 | irmp_ISR();\r | |
189 | }\r | |
190 | }\r | |
191 | \r | |
192 | #endif\r |