/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* main.c - demo main module to test irmp decoder\r
*\r
- * Copyright (c) 2009-2011 Frank Meyer - frank(at)fli4l.de\r
+ * Copyright (c) 2009-2015 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: main.c,v 1.9 2011/04/11 12:54:25 fm Exp $\r
+ * $Id: main.c,v 1.27 2015/02/27 10:19:20 fm Exp $\r
*\r
- * ATMEGA88 @ 8 MHz\r
+ * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
*\r
- * Fuses: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
+ * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
+ * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
*\r
* This program is free software; you can redistribute it and/or modify\r
* it under the terms of the GNU General Public License as published by\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*/\r
\r
-#include <inttypes.h>\r
-#include <avr/io.h>\r
-#include <util/delay.h>\r
-#include <avr/pgmspace.h>\r
-#include <avr/interrupt.h>\r
-\r
-#include "irmpconfig.h"\r
#include "irmp.h"\r
\r
#ifndef F_CPU\r
-#error F_CPU unkown\r
+#error F_CPU unknown\r
#endif\r
\r
-void\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * ATMEL AVR part:\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#if defined (ATMEL_AVR)\r
+\r
+#include "irmp.h"\r
+#define BAUD 9600L\r
+#include <util/setbaud.h>\r
+\r
+#ifdef UBRR0H\r
+\r
+#define UART0_UBRRH UBRR0H\r
+#define UART0_UBRRL UBRR0L\r
+#define UART0_UCSRA UCSR0A\r
+#define UART0_UCSRB UCSR0B\r
+#define UART0_UCSRC UCSR0C\r
+#define UART0_UDRE_BIT_VALUE (1<<UDRE0)\r
+#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ01)\r
+#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ00)\r
+#ifdef URSEL0\r
+#define UART0_URSEL_BIT_VALUE (1<<URSEL0)\r
+#else\r
+#define UART0_URSEL_BIT_VALUE (0)\r
+#endif\r
+#define UART0_TXEN_BIT_VALUE (1<<TXEN0)\r
+#define UART0_UDR UDR0\r
+#define UART0_U2X U2X0\r
+\r
+#else\r
+\r
+#define UART0_UBRRH UBRRH\r
+#define UART0_UBRRL UBRRL\r
+#define UART0_UCSRA UCSRA\r
+#define UART0_UCSRB UCSRB\r
+#define UART0_UCSRC UCSRC\r
+#define UART0_UDRE_BIT_VALUE (1<<UDRE)\r
+#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ1)\r
+#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ0)\r
+#ifdef URSEL\r
+#define UART0_URSEL_BIT_VALUE (1<<URSEL)\r
+#else\r
+#define UART0_URSEL_BIT_VALUE (0)\r
+#endif\r
+#define UART0_TXEN_BIT_VALUE (1<<TXEN)\r
+#define UART0_UDR UDR\r
+#define UART0_U2X U2X\r
+\r
+#endif //UBRR0H\r
+\r
+static void\r
+uart_init (void)\r
+{\r
+ UART0_UBRRH = UBRRH_VALUE; // set baud rate\r
+ UART0_UBRRL = UBRRL_VALUE;\r
+\r
+#if USE_2X\r
+ UART0_UCSRA |= (1<<UART0_U2X);\r
+#else\r
+ UART0_UCSRA &= ~(1<<UART0_U2X);\r
+#endif\r
+\r
+ UART0_UCSRC = UART0_UCSZ1_BIT_VALUE | UART0_UCSZ0_BIT_VALUE | UART0_URSEL_BIT_VALUE;\r
+ UART0_UCSRB |= UART0_TXEN_BIT_VALUE; // enable UART TX\r
+}\r
+\r
+static void\r
+uart_putc (unsigned char ch)\r
+{\r
+ while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
+ {\r
+ ;\r
+ }\r
+\r
+ UART0_UDR = ch;\r
+}\r
+\r
+static void\r
+uart_puts (char * s)\r
+{\r
+ while (*s)\r
+ {\r
+ uart_putc (*s);\r
+ s++;\r
+ }\r
+}\r
+\r
+static void\r
+uart_puts_P (PGM_P s)\r
+{\r
+ uint8_t ch;\r
+\r
+ while ((ch = pgm_read_byte(s)) != '\0')\r
+ {\r
+ uart_putc (ch);\r
+ s++;\r
+ }\r
+}\r
+\r
+static char *\r
+itoh (char * buf, uint8_t digits, uint16_t number)\r
+{\r
+ for (buf[digits] = 0; digits--; number >>= 4)\r
+ {\r
+ buf[digits] = "0123456789ABCDEF"[number & 0x0F];\r
+ }\r
+ return buf;\r
+}\r
+\r
+static void\r
timer1_init (void)\r
{\r
-#if defined (__AVR_ATtiny85__) // ATtiny85:\r
- OCR1A = (F_CPU / (2 * F_INTERRUPTS) / 2) - 1; // compare value: 1/28800 of CPU frequency, presc = 2\r
- TCCR1 = (1 << CTC1) | (1 << CS11); // switch CTC Mode on, set prescaler to 2\r
-#else // ATmegaXX:\r
- OCR1A = (F_CPU / (2 * F_INTERRUPTS)) - 1; // compare value: 1/28800 of CPU frequency\r
- TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
+#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r
+\r
+#if F_CPU >= 16000000L\r
+ OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r
+ TCCR1 = (1 << CTC1) | (1 << CS12); // switch CTC Mode on, set prescaler to 8\r
+#else\r
+ OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r
+ TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
+#endif\r
+\r
+#else // ATmegaXX:\r
+ OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
+ TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
#ifdef TIMSK1\r
- TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
+ TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
#else\r
- TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
+ TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
#endif\r
}\r
\r
+#ifdef TIM1_COMPA_vect // ATtiny84\r
+#define COMPA_VECT TIM1_COMPA_vect\r
+#else\r
+#define COMPA_VECT TIMER1_COMPA_vect // ATmega\r
+#endif\r
+\r
+ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
+{\r
+ (void) irmp_ISR(); // call irmp ISR\r
+ // call other timer interrupt routines...\r
+}\r
+\r
+int\r
+main (void)\r
+{\r
+ IRMP_DATA irmp_data;\r
+ char buf[3];\r
+\r
+ irmp_init(); // initialize irmp\r
+ timer1_init(); // initialize timer1\r
+ uart_init(); // initialize uart\r
+\r
+ sei (); // enable interrupts\r
+\r
+ for (;;)\r
+ {\r
+ if (irmp_get_data (&irmp_data))\r
+ {\r
+ uart_puts_P (PSTR("protocol: 0x"));\r
+ itoh (buf, 2, irmp_data.protocol);\r
+ uart_puts (buf);\r
+\r
+#if IRMP_PROTOCOL_NAMES == 1\r
+ uart_puts_P (PSTR(" "));\r
+ uart_puts_P (pgm_read_word (&(irmp_protocol_names[irmp_data.protocol])));\r
+#endif\r
+\r
+ uart_puts_P (PSTR(" address: 0x"));\r
+ itoh (buf, 4, irmp_data.address);\r
+ uart_puts (buf);\r
+\r
+ uart_puts_P (PSTR(" command: 0x"));\r
+ itoh (buf, 4, irmp_data.command);\r
+ uart_puts (buf);\r
+\r
+ uart_puts_P (PSTR(" flags: 0x"));\r
+ itoh (buf, 2, irmp_data.flags);\r
+ uart_puts (buf);\r
+\r
+ uart_puts_P (PSTR("\r\n"));\r
+ }\r
+ }\r
+}\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * LM4F120 Launchpad (ARM Cortex M4):\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+\r
+void\r
+timer1_init (void)\r
+{\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
+ TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
+\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
+ IntEnable(INT_TIMER1A);\r
+ TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+ TimerEnable(TIMER1_BASE, TIMER_A);\r
+ // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
+}\r
+\r
+void\r
+Timer1IntHandler(void) // Timer1 Interrupt Handler\r
+{\r
+ (void) irmp_ISR(); // call irmp ISR\r
+ // call other timer interrupt routines...\r
+}\r
+\r
int\r
main (void)\r
{\r
IRMP_DATA irmp_data;\r
\r
+ ROM_FPUEnable();\r
+ ROM_FPUStackingEnable();\r
+ ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
+\r
irmp_init(); // initialize irmp\r
- timer1_init(); // initialize timer 1\r
+ timer1_init(); // initialize timer1\r
sei (); // enable interrupts\r
\r
for (;;)\r
}\r
}\r
}\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * PIC18F4520 with XC8 compiler:\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#elif defined (__XC8)\r
+\r
+#define _XTAL_FREQ 32000000UL // 32MHz clock\r
+#define FOSC _XTAL_FREQ\r
+#define FCY FOSC / 4UL // --> 8MHz\r
+\r
+#define BAUDRATE 19200UL\r
+#define BRG (( FCY 16 BAUDRATE ) -1UL)\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+\r
+int\r
+main (void)\r
+{\r
+ IRMP_DATA irmp_data;\r
+\r
+ irmp_init(); // initialize irmp\r
+\r
+ // infinite loop, interrupts will blink PORTD pins and handle UART communications.\r
+ while (1)\r
+ {\r
+ LATBbits.LATB0 = ~LATBbits.LATB0;\r
+\r
+ if (irmp_get_data (&irmp_data))\r
+ {\r
+ // ir signal decoded, do something here...\r
+ // irmp_data.protocol is the protocol, see irmp.h\r
+ // irmp_data.address is the address/manufacturer code of ir sender\r
+ // irmp_data.command is the command code\r
+ // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
+ printf("proto %d addr %d cmd %d\n", irmp_data.protocol, irmp_data.address, irmp_data.command );\r
+ }\r
+ }\r
+}\r
+\r
+void interrupt high_priority high_isr(void)\r
+{\r
+ if (TMR2IF)\r
+ {\r
+ TMR2IF = 0; // clear Timer 0 interrupt flag\r
+ irmp_ISR();\r
+ }\r
+}\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * STM32:\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#elif defined(ARM_STM32)\r
+\r
+uint32_t\r
+SysCtlClockGet(void)\r
+{\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ return RCC_ClocksStatus.SYSCLK_Frequency;\r
+}\r
+\r
+void\r
+timer2_init (void)\r
+{\r
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
+ NVIC_InitTypeDef NVIC_InitStructure;\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+\r
+ TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
+ TIM_TimeBaseStructure.TIM_Period = 7;\r
+ TIM_TimeBaseStructure.TIM_Prescaler = ((F_CPU / F_INTERRUPTS)/8) - 1;\r
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);\r
+\r
+ TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);\r
+\r
+ NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
+ NVIC_Init(&NVIC_InitStructure);\r
+\r
+ TIM_Cmd(TIM2, ENABLE);\r
+}\r
+\r
+void\r
+TIM2_IRQHandler(void) // Timer2 Interrupt Handler\r
+{\r
+ TIM_ClearITPendingBit(TIM2, TIM_IT_Update);\r
+ (void) irmp_ISR(); // call irmp ISR\r
+ // call other timer interrupt routines...\r
+}\r
+\r
+int\r
+main (void)\r
+{\r
+ IRMP_DATA irmp_data;\r
+ \r
+ irmp_init(); // initialize irmp\r
+ timer2_init(); // initialize timer2\r
+\r
+ for (;;)\r
+ {\r
+ if (irmp_get_data (&irmp_data))\r
+ {\r
+ // ir signal decoded, do something here...\r
+ // irmp_data.protocol is the protocol, see irmp.h\r
+ // irmp_data.address is the address/manufacturer code of ir sender\r
+ // irmp_data.command is the command code\r
+ // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
+ }\r
+ }\r
+}\r
+#endif\r
projects / irmp.git / blobdiff