/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* main.c - demo main module to test irmp decoder\r
*\r
- * Copyright (c) 2009-2011 Frank Meyer - frank(at)fli4l.de\r
+ * Copyright (c) 2009-2013 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: main.c,v 1.9 2011/04/11 12:54:25 fm Exp $\r
+ * $Id: main.c,v 1.17 2013/01/17 07:33:14 fm Exp $\r
*\r
- * ATMEGA88 @ 8 MHz\r
+ * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
*\r
- * Fuses: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
+ * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
+ * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
*\r
* This program is free software; you can redistribute it and/or modify\r
* it under the terms of the GNU General Public License as published by\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*/\r
\r
-#include <inttypes.h>\r
-#include <avr/io.h>\r
-#include <util/delay.h>\r
-#include <avr/pgmspace.h>\r
-#include <avr/interrupt.h>\r
-\r
-#include "irmpconfig.h"\r
#include "irmp.h"\r
\r
#ifndef F_CPU\r
#error F_CPU unkown\r
#endif\r
\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * ATMEL AVR part:\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#if defined (ATMEL_AVR)\r
+\r
void\r
timer1_init (void)\r
{\r
-#if defined (__AVR_ATtiny85__) // ATtiny85:\r
- OCR1A = (F_CPU / (2 * F_INTERRUPTS) / 2) - 1; // compare value: 1/28800 of CPU frequency, presc = 2\r
- TCCR1 = (1 << CTC1) | (1 << CS11); // switch CTC Mode on, set prescaler to 2\r
-#else // ATmegaXX:\r
- OCR1A = (F_CPU / (2 * F_INTERRUPTS)) - 1; // compare value: 1/28800 of CPU frequency\r
- TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
+#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r
+\r
+#if F_CPU >= 16000000L\r
+ OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r
+ TCCR1 = (1 << CTC1) | (1 << CS12); // switch CTC Mode on, set prescaler to 8\r
+#else\r
+ OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r
+ TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
+#endif\r
+\r
+#else // ATmegaXX:\r
+ OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
+ TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
#ifdef TIMSK1\r
- TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
+ TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
#else\r
- TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
+ TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
#endif\r
}\r
\r
+#ifdef TIM1_COMPA_vect // ATtiny84\r
+#define COMPA_VECT TIM1_COMPA_vect\r
+#else\r
+#define COMPA_VECT TIMER1_COMPA_vect // ATmega\r
+#endif\r
+\r
+ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
+{\r
+ (void) irmp_ISR(); // call irmp ISR\r
+ // call other timer interrupt routines...\r
+}\r
+\r
int\r
main (void)\r
{\r
IRMP_DATA irmp_data;\r
\r
irmp_init(); // initialize irmp\r
- timer1_init(); // initialize timer 1\r
+ timer1_init(); // initialize timer1\r
sei (); // enable interrupts\r
\r
for (;;)\r
}\r
}\r
}\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ * LM4F120 Launchpad (ARM Cortex M4):\r
+ *---------------------------------------------------------------------------------------------------------------------------------------------------\r
+ */\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+\r
+void\r
+timer1_init (void)\r
+{\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
+ TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
+\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
+ IntEnable(INT_TIMER1A);\r
+ TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+ TimerEnable(TIMER1_BASE, TIMER_A);\r
+ // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
+}\r
+\r
+void\r
+Timer1IntHandler(void) // Timer1 Interrupt Handler\r
+{\r
+ (void) irmp_ISR(); // call irmp ISR\r
+ // call other timer interrupt routines...\r
+}\r
+\r
+int\r
+main (void)\r
+{\r
+ IRMP_DATA irmp_data;\r
+\r
+ ROM_FPUEnable();\r
+ ROM_FPUStackingEnable();\r
+ ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
+\r
+ irmp_init(); // initialize irmp\r
+ timer1_init(); // initialize timer1\r
+ sei (); // enable interrupts\r
+\r
+ for (;;)\r
+ {\r
+ if (irmp_get_data (&irmp_data))\r
+ {\r
+ // ir signal decoded, do something here...\r
+ // irmp_data.protocol is the protocol, see irmp.h\r
+ // irmp_data.address is the address/manufacturer code of ir sender\r
+ // irmp_data.command is the command code\r
+ // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
+ }\r
+ }\r
+}\r
+\r
+#endif\r
projects / irmp.git / blobdiff