-#define SIEMENS_BIT_TIME 250.0e-6 // 250 usec pulse/pause\r
-#define SIEMENS_FRAME_REPEAT_PAUSE_TIME 45.0e-3 // frame repeat after 45ms\r
-#define SIEMENS_ADDRESS_OFFSET 2 // skip 2 start bits\r
-#define SIEMENS_ADDRESS_LEN 12 // read 12 address bits\r
-#define SIEMENS_COMMAND_OFFSET 15 // skip 15 bits (2 start bits + 12 address bits + 1 inverted bit)\r
-#define SIEMENS_COMMAND_LEN 7 // read 7 command bits\r
-#define SIEMENS_COMPLETE_DATA_LEN 23 // complete length\r
-#define SIEMENS_STOP_BIT 0 // has no stop bit\r
-#define SIEMENS_LSB 0 // MSB...LSB\r
-#define SIEMENS_FLAGS (IRMP_PARAM_FLAG_IS_MANCHESTER | IRMP_PARAM_FLAG_1ST_PULSE_IS_1) // flags\r
-\r
-#define FDC1_START_BIT_PULSE_TIME 1390.0e-6 // 1390 usec pulse\r
-#define FDC1_START_BIT_PAUSE_TIME 640.0e-6 // 640 usec pause\r
-#define FDC1_PULSE_TIME 200.0e-6 // 200 usec pulse\r
-#define FDC1_1_PAUSE_TIME 475.0e-6 // 475 usec pause\r
-#define FDC1_0_PAUSE_TIME 145.0e-6 // 145 usec pause\r
-#define FDC1_FRAME_REPEAT_PAUSE_TIME 40.0e-3 // frame repeat after 40ms\r
-#define FDC1_ADDRESS_OFFSET 0 // skip 0 bits\r
-#define FDC1_ADDRESS_LEN 8 // read 8 address bits\r
-#define FDC1_COMMAND_OFFSET 24 // skip 24 bits (8 address bits + 12 status bits + 4 repeat bits)\r
-#define FDC1_COMMAND_LEN 8 // read 8 bits\r
-#define FDC1_COMPLETE_DATA_LEN 40 // complete length\r
-#define FDC1_STOP_BIT 1 // has stop bit\r
-#define FDC1_LSB 1 // LSB...MSB\r
-#define FDC1_FLAGS 0 // flags\r
-\r
-#define FDC2_START_BIT_PULSE_TIME 2120.0e-6 // 2120 usec pulse\r
-#define FDC2_START_BIT_PAUSE_TIME 900.0e-6 // 900 usec pause\r
-#define FDC2_PULSE_TIME 360.0e-6 // 360 usec pulse\r
-#define FDC2_1_PAUSE_TIME 650.0e-6 // 650 usec pause\r
-#define FDC2_0_PAUSE_TIME 180.0e-6 // 180 usec pause\r
-#define FDC2_FRAME_REPEAT_PAUSE_TIME 40.0e-3 // frame repeat after 40ms\r
-#define FDC2_ADDRESS_OFFSET 0 // skip 0 bits\r
-#define FDC2_ADDRESS_LEN 8 // read 8 address bits\r
-#define FDC2_COMMAND_OFFSET 24 // skip 24 bits (8 address bits + 12 status bits + 4 repeat bits)\r
-#define FDC2_COMMAND_LEN 8 // read 8 bits\r
-#define FDC2_COMPLETE_DATA_LEN 40 // complete length\r
-#define FDC2_STOP_BIT 1 // has stop bit\r
-#define FDC2_LSB 1 // LSB...MSB\r
-#define FDC2_FLAGS 0 // flags\r
-\r
-#define AUTO_FRAME_REPETITION_TIME 50.0e-3 // SIRCS/SAMSUNG32/NUBERT: automatic repetition after 25-50ms\r
+#define IR60_TIMEOUT_TIME 5000.0e-6 // timeout grundig frame, switch to IR60\r
+#define IR60_ADDRESS_OFFSET 0 // skip 1 bits\r
+#define IR60_ADDRESS_LEN 0 // read 0 address bits\r
+#define IR60_COMMAND_OFFSET 0 // skip 1 bit (start bit after pre bit, always 1)\r
+#define IR60_COMMAND_LEN 7 // read 6 command bits\r
+#define IR60_COMPLETE_DATA_LEN 7 // complete length\r
+\r
+#define SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME 275.0e-6 // 275 usec pulse\r
+#define SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME 550.0e-6 // 550 usec pause\r
+#define SIEMENS_OR_RUWIDO_BIT_PULSE_TIME 275.0e-6 // 275 usec short pulse\r
+#define SIEMENS_OR_RUWIDO_BIT_PULSE_TIME_2 550.0e-6 // 550 usec long pulse\r
+#define SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME 275.0e-6 // 275 usec short pause\r
+#define SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME_2 550.0e-6 // 550 usec long pause\r
+#define SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME 45.0e-3 // frame repeat after 45ms\r
+#define SIEMENS_OR_RUWIDO_STOP_BIT 0 // has no stop bit\r
+#define SIEMENS_OR_RUWIDO_LSB 0 // MSB...LSB\r
+#define SIEMENS_OR_RUWIDO_FLAGS (IRMP_PARAM_FLAG_IS_MANCHESTER | IRMP_PARAM_FLAG_1ST_PULSE_IS_1) // flags\r
+\r
+#define RUWIDO_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define RUWIDO_ADDRESS_LEN 9 // read 9 address bits\r
+#define RUWIDO_COMMAND_OFFSET 9 // skip 9 bits\r
+#define RUWIDO_COMMAND_LEN 8 // read 7 + 1 command bits, last bit is only check bit\r
+#define RUWIDO_COMPLETE_DATA_LEN 17 // complete length\r
+\r
+#define SIEMENS_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define SIEMENS_ADDRESS_LEN 11 // read 11 bits\r
+#define SIEMENS_COMMAND_OFFSET 11 // skip 11 bits\r
+#define SIEMENS_COMMAND_LEN 11 // read 10 + 1 command bits, last bit is only check bit\r
+#define SIEMENS_COMPLETE_DATA_LEN 22 // complete length\r
+\r
+#define FDC_START_BIT_PULSE_TIME 2085.0e-6 // 2085 usec pulse\r
+#define FDC_START_BIT_PAUSE_TIME 966.0e-6 // 966 usec pause\r
+#define FDC_PULSE_TIME 300.0e-6 // 300 usec pulse\r
+#define FDC_1_PAUSE_TIME 715.0e-6 // 715 usec pause\r
+#define FDC_0_PAUSE_TIME 220.0e-6 // 220 usec pause\r
+#define FDC_FRAME_REPEAT_PAUSE_TIME 60.0e-3 // frame repeat after 60ms\r
+#define FDC_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define FDC_ADDRESS_LEN 14 // read 14 address bits, but use only 6, shift 8 into command\r
+#define FDC_COMMAND_OFFSET 20 // skip 20 bits\r
+#define FDC_COMMAND_LEN 12 // read 12 bits\r
+#define FDC_COMPLETE_DATA_LEN 40 // complete length\r
+#define FDC_STOP_BIT 1 // has stop bit\r
+#define FDC_LSB 1 // LSB...MSB\r
+#define FDC_FLAGS 0 // flags\r
+\r
+#define RCCAR_START_BIT_PULSE_TIME 2000.0e-6 // 2000 usec pulse\r
+#define RCCAR_START_BIT_PAUSE_TIME 2000.0e-6 // 2000 usec pause\r
+#define RCCAR_PULSE_TIME 600.0e-6 // 360 usec pulse\r
+#define RCCAR_1_PAUSE_TIME 450.0e-6 // 650 usec pause\r
+#define RCCAR_0_PAUSE_TIME 900.0e-6 // 180 usec pause\r
+#define RCCAR_FRAME_REPEAT_PAUSE_TIME 40.0e-3 // frame repeat after 40ms\r
+#define RCCAR_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define RCCAR_ADDRESS_LEN 0 // read 0 address bits\r
+#define RCCAR_COMMAND_OFFSET 0 // skip 0 bits\r
+#define RCCAR_COMMAND_LEN 13 // read 13 bits\r
+#define RCCAR_COMPLETE_DATA_LEN 13 // complete length\r
+#define RCCAR_STOP_BIT 1 // has stop bit\r
+#define RCCAR_LSB 1 // LSB...MSB\r
+#define RCCAR_FLAGS 0 // flags\r
+\r
+#define JVC_START_BIT_PULSE_TIME 9000.0e-6 // 9000 usec pulse\r
+#define JVC_START_BIT_PAUSE_TIME 4500.0e-6 // 4500 usec pause\r
+#define JVC_PULSE_TIME 560.0e-6 // 560 usec pulse\r
+#define JVC_1_PAUSE_TIME 1690.0e-6 // 1690 usec pause\r
+#define JVC_0_PAUSE_TIME 560.0e-6 // 560 usec pause\r
+#define JVC_FRAME_REPEAT_PAUSE_TIME 22.0e-3 // frame repeat after 22ms\r
+#define JVC_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define JVC_ADDRESS_LEN 4 // read 4 address bits\r
+#define JVC_COMMAND_OFFSET 4 // skip 4 bits\r
+#define JVC_COMMAND_LEN 12 // read 12 bits\r
+#define JVC_COMPLETE_DATA_LEN 16 // complete length\r
+#define JVC_STOP_BIT 1 // has stop bit\r
+#define JVC_LSB 1 // LSB...MSB\r
+#define JVC_FLAGS 0 // flags\r
+\r
+#define NIKON_START_BIT_PULSE_TIME 2200.0e-6 // 2200 usec pulse\r
+#define NIKON_START_BIT_PAUSE_TIME 27100.0e-6 // 27100 usec pause\r
+#define NIKON_PULSE_TIME 500.0e-6 // 520 usec pulse\r
+#define NIKON_1_PAUSE_TIME 3500.0e-6 // 3500 usec pause\r
+#define NIKON_0_PAUSE_TIME 1500.0e-6 // 1500 usec pause\r
+#define NIKON_FRAME_REPEAT_PAUSE_TIME 60.0e-3 // frame repeat after 60ms\r
+#define NIKON_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define NIKON_ADDRESS_LEN 0 // read 0 address bits\r
+#define NIKON_COMMAND_OFFSET 0 // skip 0 bits\r
+#define NIKON_COMMAND_LEN 2 // read 2 bits\r
+#define NIKON_COMPLETE_DATA_LEN 2 // complete length\r
+#define NIKON_STOP_BIT 1 // has stop bit\r
+#define NIKON_LSB 0 // LSB...MSB\r
+#define NIKON_FLAGS 0 // flags\r
+\r
+#define KATHREIN_START_BIT_PULSE_TIME 210.0e-6 // 1340 usec pulse\r
+#define KATHREIN_START_BIT_PAUSE_TIME 6218.0e-6 // 340 usec pause\r
+#define KATHREIN_1_PULSE_TIME 210.0e-6 // 1340 usec pulse\r
+#define KATHREIN_1_PAUSE_TIME 3000.0e-6 // 340 usec pause\r
+#define KATHREIN_0_PULSE_TIME 210.0e-6 // 500 usec pulse\r
+#define KATHREIN_0_PAUSE_TIME 1400.0e-6 // 1300 usec pause\r
+#define KATHREIN_SYNC_BIT_PAUSE_LEN_TIME 4600.0e-6 // 4600 usec sync (on 6th and/or 8th bit)\r
+#define KATHREIN_FRAMES 1 // Kathrein sends 1 frame\r
+#define KATHREIN_AUTO_REPETITION_PAUSE_TIME 35.0e-3 // auto repetition after 35ms\r
+#define KATHREIN_FRAME_REPEAT_PAUSE_TIME 35.0e-3 // frame repeat after 35ms\r
+#define KATHREIN_ADDRESS_OFFSET 1 // skip 1 bits\r
+#define KATHREIN_ADDRESS_LEN 4 // read 4 address bits\r
+#define KATHREIN_COMMAND_OFFSET 5 // skip 5 bits\r
+#define KATHREIN_COMMAND_LEN 7 // read 7 bits\r
+#define KATHREIN_COMPLETE_DATA_LEN 13 // complete length\r
+#define KATHREIN_STOP_BIT 1 // has stop bit\r
+#define KATHREIN_LSB 0 // MSB\r
+#define KATHREIN_FLAGS 0 // flags\r
+\r
+#define NETBOX_START_BIT_PULSE_TIME 2400.0e-6 // 2400 usec pulse\r
+#define NETBOX_START_BIT_PAUSE_TIME 800.0e-6 // 800 usec pause\r
+#define NETBOX_PULSE_TIME 800.0e-6 // 800 usec pulse\r
+#define NETBOX_PAUSE_TIME 800.0e-6 // 800 usec pause\r
+#define NETBOX_FRAMES 1 // Netbox sends 1 frame\r
+#define NETBOX_AUTO_REPETITION_PAUSE_TIME 35.0e-3 // auto repetition after 35ms\r
+#define NETBOX_FRAME_REPEAT_PAUSE_TIME 35.0e-3 // frame repeat after 35ms\r
+#define NETBOX_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define NETBOX_ADDRESS_LEN 3 // read 3 address bits\r
+#define NETBOX_COMMAND_OFFSET 3 // skip 3 bits\r
+#define NETBOX_COMMAND_LEN 13 // read 13 bits\r
+#define NETBOX_COMPLETE_DATA_LEN 16 // complete length\r
+#define NETBOX_STOP_BIT 0 // has no stop bit\r
+#define NETBOX_LSB 1 // LSB\r
+#define NETBOX_FLAGS IRMP_PARAM_FLAG_IS_SERIAL // flags\r
+\r
+#define IMON_START_BIT_PULSE_TIME 1333.0e-6 // 1333 usec pulse\r
+#define IMON_START_BIT_PAUSE_TIME 1172.0e-6 // 1333 usec pause\r
+#define IMON_PULSE_TIME 500.0e-6 // 500 usec pulse\r
+#define IMON_PAUSE_TIME 500.0e-6 // 500 usec pause\r
+#define IMON_FRAMES 1 // Imon sends 1 frame\r
+#define IMON_AUTO_REPETITION_PAUSE_TIME 35.0e-3 // auto repetition after 35ms\r
+#define IMON_FRAME_REPEAT_PAUSE_TIME 35.0e-3 // frame repeat after 35ms\r
+#define IMON_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define IMON_ADDRESS_LEN 0 // read 0 address bits\r
+#define IMON_COMMAND_OFFSET 26 // skip 26 bits\r
+#define IMON_COMMAND_LEN 16 // read last 16 bits, ignore rest\r
+#define IMON_COMPLETE_DATA_LEN 42 // complete length, last is stop bit\r
+#define IMON_STOP_BIT 1 // has stop bit\r
+#define IMON_LSB 1 // LSB\r
+#define IMON_FLAGS IRMP_PARAM_FLAG_IS_SERIAL // flags\r
+\r
+#define AUTO_FRAME_REPETITION_TIME 80.0e-3 // SIRCS/SAMSUNG32/NUBERT: automatic repetition after 25-50ms\r
+ // KASEIKYO: automatic repetition after 75ms\r