-\r
-#define FDC1_START_BIT_PULSE_TIME 1390.0e-6 // 1390 usec pulse\r
-#define FDC1_START_BIT_PAUSE_TIME 640.0e-6 // 640 usec pause\r
-#define FDC1_PULSE_TIME 200.0e-6 // 200 usec pulse\r
-#define FDC1_1_PAUSE_TIME 475.0e-6 // 475 usec pause\r
-#define FDC1_0_PAUSE_TIME 145.0e-6 // 145 usec pause\r
-#define FDC1_FRAME_REPEAT_PAUSE_TIME 40.0e-3 // frame repeat after 40ms\r
-#define FDC1_ADDRESS_OFFSET 0 // skip 0 bits\r
-#define FDC1_ADDRESS_LEN 8 // read 8 address bits\r
-#define FDC1_COMMAND_OFFSET 24 // skip 24 bits (8 address bits + 12 status bits + 4 repeat bits)\r
-#define FDC1_COMMAND_LEN 8 // read 8 bits\r
-#define FDC1_COMPLETE_DATA_LEN 40 // complete length\r
-#define FDC1_STOP_BIT 1 // has stop bit\r
-#define FDC1_LSB 1 // LSB...MSB\r
-\r
-#define FDC2_START_BIT_PULSE_TIME 2120.0e-6 // 2120 usec pulse\r
-#define FDC2_START_BIT_PAUSE_TIME 920.0e-6 // 920 usec pause\r
-#define FDC2_PULSE_TIME 400.0e-6 // 400 usec pulse\r
-#define FDC2_1_PAUSE_TIME 660.0e-6 // 660 usec pause\r
-#define FDC2_0_PAUSE_TIME 145.0e-6 // 140 usec pause\r
-#define FDC2_FRAME_REPEAT_PAUSE_TIME 40.0e-3 // frame repeat after 40ms\r
-#define FDC2_ADDRESS_OFFSET 0 // skip 0 bits\r
-#define FDC2_ADDRESS_LEN 8 // read 8 address bits\r
-#define FDC2_COMMAND_OFFSET 24 // skip 24 bits (8 address bits + 12 status bits + 4 repeat bits)\r
-#define FDC2_COMMAND_LEN 8 // read 8 bits\r
-#define FDC2_COMPLETE_DATA_LEN 40 // complete length\r
-#define FDC2_STOP_BIT 1 // has stop bit\r
-#define FDC2_LSB 1 // LSB...MSB\r
+#define SIEMENS_FLAGS (IRMP_PARAM_FLAG_IS_MANCHESTER | IRMP_PARAM_FLAG_1ST_PULSE_IS_1) // flags\r
+\r
+#define FDC_START_BIT_PULSE_TIME 2085.0e-6 // 2085 usec pulse\r
+#define FDC_START_BIT_PAUSE_TIME 966.0e-6 // 966 usec pause\r
+#define FDC_PULSE_TIME 300.0e-6 // 300 usec pulse\r
+#define FDC_1_PAUSE_TIME 715.0e-6 // 715 usec pause\r
+#define FDC_0_PAUSE_TIME 220.0e-6 // 220 usec pause\r
+#define FDC_FRAME_REPEAT_PAUSE_TIME 60.0e-3 // frame repeat after 60ms\r
+#define FDC_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define FDC_ADDRESS_LEN 8 // read 8 address bits\r
+#define FDC_COMMAND_OFFSET 24 // skip 24 bits (8 address bits + 12 status bits + 4 repeat bits)\r
+#define FDC_COMMAND_LEN 8 // read 8 bits\r
+#define FDC_COMPLETE_DATA_LEN 40 // complete length\r
+#define FDC_STOP_BIT 1 // has stop bit\r
+#define FDC_LSB 1 // LSB...MSB\r
+#define FDC_FLAGS 0 // flags\r
+\r
+#define RCCAR_START_BIT_PULSE_TIME 2000.0e-6 // 2000 usec pulse\r
+#define RCCAR_START_BIT_PAUSE_TIME 2000.0e-6 // 2000 usec pause\r
+#define RCCAR_PULSE_TIME 600.0e-6 // 360 usec pulse\r
+#define RCCAR_1_PAUSE_TIME 450.0e-6 // 650 usec pause\r
+#define RCCAR_0_PAUSE_TIME 900.0e-6 // 180 usec pause\r
+#define RCCAR_FRAME_REPEAT_PAUSE_TIME 40.0e-3 // frame repeat after 40ms\r
+#define RCCAR_ADDRESS_OFFSET 0 // skip 0 bits\r
+#define RCCAR_ADDRESS_LEN 0 // read 0 address bits\r
+#define RCCAR_COMMAND_OFFSET 0 // skip 0 bits\r
+#define RCCAR_COMMAND_LEN 13 // read 13 bits\r
+#define RCCAR_COMPLETE_DATA_LEN 13 // complete length\r
+#define RCCAR_STOP_BIT 1 // has stop bit\r
+#define RCCAR_LSB 1 // LSB...MSB\r
+#define RCCAR_FLAGS 0 // flags\r