X-Git-Url: http://cloudbase.mooo.com/gitweb/irmp.git/blobdiff_plain/95eab03cca00d71c839a8f265ca0d9fbf3b41c44..afd1e690e5576608cc0754b348faed22f674a32a:/main.c

diff --git a/main.c b/main.c
index dbcd57f..2327ac6 100644
--- a/main.c
+++ b/main.c
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
  *
- * $Id: main.c,v 1.14 2012/05/15 10:25:21 fm Exp $
+ * $Id: main.c,v 1.15 2012/11/18 17:51:26 fm Exp $
  *
  * ATMEGA88 @ 8 MHz
  *
@@ -35,15 +35,26 @@ timer1_init (void)
     TCCR1   = (1 << CTC1) | (1 << CS11) | (1 << CS10);                      // switch CTC Mode on, set prescaler to 4
 #endif
 
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
+    TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);
+
+    TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);
+    IntEnable(INT_TIMER1A);
+    TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
+    TimerEnable(TIMER1_BASE, TIMER_A);
+    // Important: Timer1IntHandler has to be configured in startup_ccs.c !
 #else                                                                       // ATmegaXX:
     OCR1A   =  (F_CPU / F_INTERRUPTS) - 1;                                  // compare value: 1/15000 of CPU frequency
     TCCR1B  = (1 << WGM12) | (1 << CS10);                                   // switch CTC Mode on, set prescaler to 1
 #endif
 
-#ifdef TIMSK1
+#if (!defined(STELLARIS_ARM_CORTEX_M4))
+#  ifdef TIMSK1
     TIMSK1  = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare
-#else
+#  else
     TIMSK   = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare
+#  endif
 #endif
 }
 
@@ -53,6 +64,8 @@ timer1_init (void)
  */
 #ifdef TIM1_COMPA_vect                                                      // ATtiny84
 ISR(TIM1_COMPA_vect)
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+void Timer1IntHandler(void)
 #else
 ISR(TIMER1_COMPA_vect)
 #endif
@@ -67,6 +80,12 @@ main (void)
 {
     IRMP_DATA irmp_data;
 
+#if defined(STELLARIS_ARM_CORTEX_M4)
+    ROM_FPUEnable();
+    ROM_FPUStackingEnable();
+    ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
+#endif
+
     irmp_init();                                                            // initialize irmp
     timer1_init();                                                          // initialize timer 1
     sei ();                                                                 // enable interrupts