From afd1e690e5576608cc0754b348faed22f674a32a Mon Sep 17 00:00:00 2001
From: ukw <ukw@aeb2e35e-bfc4-4214-b83c-9e8de998ed28>
Date: Mon, 19 Nov 2012 10:54:26 +0000
Subject: [PATCH] Version 2.3.3: port to Stellaris ARM Cortex M4

git-svn-id: svn://mikrocontroller.net/irmp@108 aeb2e35e-bfc4-4214-b83c-9e8de998ed28
---
 README.txt   |  2 +-
 irmp.c       | 17 ++++++++++++++++-
 irmp.h       | 11 ++++++++++-
 irmpconfig.h | 10 +++++++++-
 irmpsystem.h | 23 +++++++++++++++++++++--
 main.c       | 25 ++++++++++++++++++++++---
 6 files changed, 79 insertions(+), 9 deletions(-)

diff --git a/README.txt b/README.txt
index d431f7e..00ad31c 100644
--- a/README.txt
+++ b/README.txt
@@ -1,7 +1,7 @@
 IRMP - Infrared Multi Protocol Decoder
 --------------------------------------
 
-Version IRMP:  2.3.2 06.11.2012
+Version IRMP:  2.3.3 19.11.2012
 Version IRSND: 2.3.2 29.10.2012
 
 Dokumentation:
diff --git a/irmp.c b/irmp.c
index ab3d59f..c8bc29f 100644
--- a/irmp.c
+++ b/irmp.c
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
  *
- * $Id: irmp.c,v 1.130 2012/11/06 10:19:41 fm Exp $
+ * $Id: irmp.c,v 1.131 2012/11/18 17:51:26 fm Exp $
  *
  * ATMEGA88 @ 8 MHz
  *
@@ -1292,6 +1292,15 @@ irmp_init (void)
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
  #endif
    GPIO_Init(IRMP_PORT, &GPIO_InitStructure);
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+     // Enable the GPIO port
+     ROM_SysCtlPeripheralEnable(IRMP_PORT_PERIPH);
+
+     // Set as an input
+     ROM_GPIODirModeSet(IRMP_PORT_BASE, IRMP_PORT_PIN, GPIO_DIR_MODE_IN);
+     ROM_GPIOPadConfigSet(IRMP_PORT_BASE, IRMP_PORT_PIN,
+                          GPIO_STRENGTH_2MA,
+                          GPIO_PIN_TYPE_STD_WPU);
 #else                                                                   // AVR
     IRMP_PORT &= ~(1<<IRMP_BIT);                                        // deactivate pullup
     IRMP_DDR &= ~(1<<IRMP_BIT);                                         // set pin to input
@@ -3235,6 +3244,12 @@ irmp_ISR (void)
             }
         }
     }
+
+#if defined(STELLARIS_ARM_CORTEX_M4)
+    // Clear the timer interrupt
+    TimerIntClear(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
+#endif
+
     return (irmp_ir_detected);
 }
 
diff --git a/irmp.h b/irmp.h
index 8427be5..8413801 100644
--- a/irmp.h
+++ b/irmp.h
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
  *
- * $Id: irmp.h,v 1.79 2012/05/23 12:26:25 fm Exp $
+ * $Id: irmp.h,v 1.80 2012/11/18 17:51:26 fm Exp $
  *
  * ATMEGA88 @ 8 MHz
  *
@@ -52,6 +52,15 @@
 #  ifndef USE_STDPERIPH_DRIVER
 #    warning The STM32 port of IRMP uses the ST standard peripheral drivers which are not enabled in your build configuration.
 #  endif
+#elif defined (STELLARIS_ARM_CORTEX_M4)
+#  define _CONCAT(a,b)                          a##b
+#  define CONCAT(a,b)                           _CONCAT(a,b)
+#  define IRMP_PORT_PERIPH                      CONCAT(SYSCTL_PERIPH_GPIO, IRMP_PORT_LETTER)
+#  define IRMP_PORT_BASE                        CONCAT(GPIO_PORT, CONCAT(IRMP_PORT_LETTER, _BASE))
+#  define IRMP_PORT_PIN                         CONCAT(GPIO_PIN_, IRMP_BIT_NUMBER)
+#  define IRMP_PIN                              IRMP_PORT_PIN
+#  define input(x)                              ((uint8_t)(ROM_GPIOPinRead(IRMP_PORT_BASE, IRMP_PORT_PIN)))
+#  define sei()                                 IntMasterEnable()
 #endif
 
 #if IRMP_SUPPORT_DENON_PROTOCOL == 1 && IRMP_SUPPORT_RUWIDO_PROTOCOL == 1
diff --git a/irmpconfig.h b/irmpconfig.h
index 08fdc49..646bb42 100644
--- a/irmpconfig.h
+++ b/irmpconfig.h
@@ -5,7 +5,7 @@
  *
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
  *
- * $Id: irmpconfig.h,v 1.94 2012/10/26 08:12:17 fm Exp $
+ * $Id: irmpconfig.h,v 1.95 2012/11/18 17:51:26 fm Exp $
  *
  * ATMEGA88 @ 8 MHz
  *
@@ -113,6 +113,14 @@
 #  define IRMP_PORT_LETTER                      C
 #  define IRMP_BIT_NUMBER                       13
 
+/*---------------------------------------------------------------------------------------------------------------------------------------------------
+ * Change hardware pin here for Stellaris ARM Cortex M4
+ *---------------------------------------------------------------------------------------------------------------------------------------------------
+ */
+#elif defined (STELLARIS_ARM_CORTEX_M4)                                 // use B4 as IR input on Stellaris LM4F
+#  define IRMP_PORT_LETTER                      B
+#  define IRMP_BIT_NUMBER                       4
+
 /*---------------------------------------------------------------------------------------------------------------------------------------------------
  * Handling of unknown target system: DON'T CHANGE
  *---------------------------------------------------------------------------------------------------------------------------------------------------
diff --git a/irmpsystem.h b/irmpsystem.h
index 1e2e4df..b73d81f 100644
--- a/irmpsystem.h
+++ b/irmpsystem.h
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
  *
- * $Id: irmpsystem.h,v 1.6 2012/05/23 14:02:45 fm Exp $
+ * $Id: irmpsystem.h,v 1.7 2012/11/18 17:51:26 fm Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -38,6 +38,9 @@
 #  include <stm32f4xx.h>
 #  define ARM_STM32
 #  define ARM_STM32F4XX
+#elif defined(TARGET_IS_BLIZZARD_RA2)                                                                                           // TI Stellaris (tested on Stellaris Launchpad with Code Composer Studio)
+#  define STELLARIS_ARM_CORTEX_M4
+#  define F_CPU (SysCtlClockGet())
 #elif defined(unix) || defined(WIN32)                                               // Unix/Linux or Windows
 #  define UNIX_OR_WINDOWS
 #else
@@ -74,12 +77,28 @@ typedef unsigned short                  uint16_t;
 #  define IRSND_OC0                     3       // OC0
 #  define IRSND_OC0A                    4       // OC0A
 #  define IRSND_OC0B                    5       // OC0B
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+#  include "inc/hw_ints.h"
+#  include "inc/hw_memmap.h"
+#  include "inc/hw_types.h"
+#  include "inc/hw_gpio.h"
+#  include "driverlib/fpu.h"
+#  include "driverlib/sysctl.h"
+#  include "driverlib/interrupt.h"
+#  include "driverlib/gpio.h"
+#  include "driverlib/rom.h"
+#  include "driverlib/systick.h"
+#  include "driverlib/pin_map.h"
+#  include "driverlib/timer.h"
+#  define PROGMEM volatile
+#  define memcpy_P memcpy
+#  define APP_SYSTICKS_PER_SEC          32
 #else
 #  define PROGMEM
 #  define memcpy_P                      memcpy
 #endif
 
-#if defined(PIC_CCS) || defined(PIC_C18) || defined(ARM_STM32)
+#if defined(PIC_CCS) || defined(PIC_C18) || defined(ARM_STM32) || defined(STELLARIS_ARM_CORTEX_M4)
 typedef unsigned char                   uint8_t;
 typedef unsigned short                  uint16_t;
 #endif
diff --git a/main.c b/main.c
index dbcd57f..2327ac6 100644
--- a/main.c
+++ b/main.c
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de
  *
- * $Id: main.c,v 1.14 2012/05/15 10:25:21 fm Exp $
+ * $Id: main.c,v 1.15 2012/11/18 17:51:26 fm Exp $
  *
  * ATMEGA88 @ 8 MHz
  *
@@ -35,15 +35,26 @@ timer1_init (void)
     TCCR1   = (1 << CTC1) | (1 << CS11) | (1 << CS10);                      // switch CTC Mode on, set prescaler to 4
 #endif
 
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
+    TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);
+
+    TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);
+    IntEnable(INT_TIMER1A);
+    TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
+    TimerEnable(TIMER1_BASE, TIMER_A);
+    // Important: Timer1IntHandler has to be configured in startup_ccs.c !
 #else                                                                       // ATmegaXX:
     OCR1A   =  (F_CPU / F_INTERRUPTS) - 1;                                  // compare value: 1/15000 of CPU frequency
     TCCR1B  = (1 << WGM12) | (1 << CS10);                                   // switch CTC Mode on, set prescaler to 1
 #endif
 
-#ifdef TIMSK1
+#if (!defined(STELLARIS_ARM_CORTEX_M4))
+#  ifdef TIMSK1
     TIMSK1  = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare
-#else
+#  else
     TIMSK   = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare
+#  endif
 #endif
 }
 
@@ -53,6 +64,8 @@ timer1_init (void)
  */
 #ifdef TIM1_COMPA_vect                                                      // ATtiny84
 ISR(TIM1_COMPA_vect)
+#elif defined(STELLARIS_ARM_CORTEX_M4)
+void Timer1IntHandler(void)
 #else
 ISR(TIMER1_COMPA_vect)
 #endif
@@ -67,6 +80,12 @@ main (void)
 {
     IRMP_DATA irmp_data;
 
+#if defined(STELLARIS_ARM_CORTEX_M4)
+    ROM_FPUEnable();
+    ROM_FPUStackingEnable();
+    ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
+#endif
+
     irmp_init();                                                            // initialize irmp
     timer1_init();                                                          // initialize timer 1
     sei ();                                                                 // enable interrupts
-- 
2.39.2