projects / z180-stamp-cpm3.git / blame
| Commit | Line | Data |
|---|---|---|
| ea5293bb L |
1 | page 200\r |
| 2 | \r | |
| 3 | ; Simple polling drivers for ASCI0 and ASCI1\r | |
| 4 | \r | |
| 5 | extrn ioiniml\r | |
| 6 | \r | |
| 7 | global as0init\r | |
| 8 | global as0ista,as0inp\r | |
| 9 | global as0osta,as0out\r | |
| 10 | global as1init\r | |
| 11 | global as1ista,as1inp\r | |
| 12 | global as1osta,as1out\r | |
| 13 | \r | |
| 14 | include config.inc\r | |
| 15 | include z180reg.inc\r | |
| 16 | \r | |
| 17 | \r | |
| 18 | ;--------------------------------------------------------------\r | |
| 19 | ;\r | |
| 20 | ;\r | |
| 21 | ; TC = (f PHI /(2*baudrate*Clock_mode)) - 2\r | |
| 22 | ;\r | |
| 23 | ; TC = (f PHI / (32 * baudrate)) - 2\r | |
| 24 | ;\r | |
| 25 | \r | |
| 26 | cseg\r | |
| 27 | ;\r | |
| 28 | ; Init Serial I/O for console input and output (ASCI1)\r | |
| 29 | ;\r | |
| 30 | \r | |
| 31 | ; TODO: set baudrate\r | |
| 32 | \r | |
| 33 | as0init:\r | |
| 34 | ld hl,initab0\r | |
| 35 | jp ioiniml\r | |
| 36 | \r | |
| 37 | as1init:\r | |
| 38 | ld hl,initab1\r | |
| 39 | jp ioiniml\r | |
| 40 | \r | |
| 41 | \r | |
| 42 | \r | |
| 43 | \r | |
| 44 | initab0:\r | |
| 45 | db 1,stat0,0 ;Disable rx/tx interrupts\r | |
| 46 | ;Enable baud rate generator\r | |
| 47 | db 1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS\r | |
| 48 | db 2,astc0l,low 28, high 28\r | |
| 49 | db 1,cntlb0,M_MPBT ;No MP Mode, X16\r | |
| 50 | db 1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r | |
| 51 | db 0\r | |
| 52 | \r | |
| 53 | initab1:\r | |
| 54 | db 1,stat1,0 ;Disable rx/tx ints, disable CTS1\r | |
| 55 | db 1,asext1,M_BRGMOD ;Enable baud rate generator\r | |
| 56 | db 2,astc1l,low 3, high 3\r | |
| 57 | db 1,cntlb1,M_MPBT ;No MP Mode, X16\r | |
| 58 | db 1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1\r | |
| 59 | db 0\r | |
| 60 | \r | |
| 61 | \r | |
| 62 | ;--------------------------------------------------------------\r | |
| 63 | \r | |
| 64 | as0ista:\r | |
| 65 | in0 a,(stat0)\r | |
| 66 | and M_RDRF\r | |
| 67 | ret z\r | |
| 68 | or 0ffh\r | |
| 69 | ret\r | |
| 70 | \r | |
| 71 | as1ista:\r | |
| 72 | in0 a,(stat1)\r | |
| 73 | and M_RDRF\r | |
| 74 | ret z\r | |
| 75 | or 0ffh\r | |
| 76 | ret\r | |
| 77 | \r | |
| 78 | \r | |
| 79 | as0inp:\r | |
| 80 | in0 a,(stat0)\r | |
| 81 | rlca\r | |
| 82 | jr nc,as0inp\r | |
| 83 | in0 a,rdr0\r | |
| 84 | ret\r | |
| 85 | \r | |
| 86 | as1inp:\r | |
| 87 | in0 a,(stat1)\r | |
| 88 | rlca\r | |
| 89 | jr nc,as1inp\r | |
| 90 | in0 a,rdr1\r | |
| 91 | ret\r | |
| 92 | \r | |
| 93 | \r | |
| 94 | \r | |
| 95 | as0osta:\r | |
| 96 | in0 a,(stat0)\r | |
| 97 | and M_TDRE\r | |
| 98 | ret z\r | |
| 99 | or 0ffh\r | |
| 100 | ret\r | |
| 101 | \r | |
| 102 | as1osta:\r | |
| 103 | in0 a,(stat1)\r | |
| 104 | and M_TDRE\r | |
| 105 | ret z\r | |
| 106 | or 0ffh\r | |
| 107 | ret\r | |
| 108 | \r | |
| 109 | \r | |
| 110 | as0out:\r | |
| 111 | in0 a,(stat0)\r | |
| 112 | and M_TDRE\r | |
| 113 | jr z,as0out\r | |
| 114 | out0 (tdr0),c\r | |
| 115 | ld a,c\r | |
| 116 | ret\r | |
| 117 | \r | |
| 118 | as1out:\r | |
| 119 | in0 a,(stat1)\r | |
| 120 | and M_TDRE\r | |
| 121 | jr z,as1out\r | |
| 122 | out0 (tdr1),c\r | |
| 123 | ld a,c\r | |
| 124 | ret\r | |
| 125 | \r | |
| 126 | end\r |