New memory map: bank 1 and common are now contiguous

[z180-stamp-cpm3.git] / cbios / conbuf.180

	page	255\r
	.z80\r
\r
;\r
; FIFO channels for communication with avr\r
;\r
	global	ff.init,ff.in,ff.ist,ff.out,ff.ost\r
\r
	extrn	bufinit,fifolst\r
\r
	include config.inc\r
	if CPU_Z180\r
	include	z180reg.inc\r
	endif\r
\r
	dseg\r
	mkbuf	ci.fifo_id, ci.fifo, ci.fifo_len\r
	mkbuf	co.fifo_id, co.fifo, co.fifo_len\r
\r
ici	equ	ci.fifo_id * 2\r
ico	equ	co.fifo_id * 2\r
\r
\r
;--------------------------------------------------------------\r
\r
; Init Serial I/O for console input and output\r
;\r
	dseg\r
ff.init:\r
	ld	a,(INIDONE)\r
	cp	INIDONEVAL\r
	ret	z\r
\r
	ld	ix,ci.fifo\r
	call	bufinit\r
	ld	ix,co.fifo\r
	jp	bufinit\r
\r
;--------------------------------------------------------------\r
; Input status\r
; buffer is empty, if output index and input index are the same\r
\r
	dseg\r
ff.ist:\r
	push	ix\r
	ld	ix,(fifolst+ici)	;\r
\r
buf.empty:\r
	ld	a,(ix+o.in_idx)		;\r
	sub	(ix+o.out_idx)		;\r
	pop	ix\r
	ret	z\r
	or	0ffh\r
	ret\r
\r
\r
;--------------------------------------------------------------\r
; Output status\r
; buffer is full, if output index is one behind input index\r
\r
ff.in:\r
	push	ix\r
	ld	ix,(fifolst+ici)	;\r
\r
buf.get:\r
	push	ix\r
	pop	hl\r
	ld	c,(ix+o.out_idx)	;\r
	ld	b,0\r
	add	hl,bc\r
	ld	a,c\r
bg.wait:\r
	cp	(ix+o.in_idx)		;\r
	jr	z,bg.wait\r
	ld	b,(hl)\r
	ld	a,c			;\r
	inc	a\r
	and	(ix+o.mask)\r
	ld	(ix+o.out_idx),a\r
	ld	a,b\r
	pop	ix\r
	ret\r
\r
;--------------------------------------------------------------\r
; Output status\r
; buffer is full, if output index is one behind input index\r
\r
ff.ost:\r
	push	ix\r
	ld	ix,(fifolst+ico)	;\r
\r
buf.full:\r
	ld	a,(ix+o.in_idx)		;\r
	inc	a\r
	and	(ix+o.mask)\r
	sub	(ix+o.out_idx)		;\r
	pop	ix\r
	ret	z\r
	or	0ffh\r
	ret\r
\r
\r
;--------------------------------------------------------------\r
; put character in c in buffer\r
; destroys hl, bc\r
; returns output char in a\r
\r
ff.out:\r
	push	ix			;\r
	ld	ix,(fifolst+ico)	;\r
buf.put:\r
	push	ix			;\r
	pop	hl			; get buffer start address\r
\r
	ld	a,c			;\r
	ld	c,(ix+o.in_idx)		; add input index\r
	ld	b,0			;\r
	add	hl,bc			;\r
	ld	(hl),a			; one place is allways free\r
	ld	b,a			;\r
\r
	ld	a,c			; bump input index\r
	inc	a			;\r
	and	(ix+o.mask)		;\r
bp.wait:				; do\r
	cp	(ix+o.out_idx)		;\r
	jr	z,bp.wait		; while new input idx == ouput idx\r
	ld	(ix+o.in_idx),a		;\r
\r
	out	(AVRINT6),a		; tell monitor\r
	ld	a,b			;\r
	pop	ix			;\r
	ret				;\r
\r
	end\r