[z180-stamp-cpm3.git] / cbios / misc.180


	public intinit
	public bufinit
	public cpu_frq
	public get_tmr

	public fifolst

	extrn div32_r,?pmsg
	extrn msg.sm,msg.recv,hwl2phy

	include config.inc
	include	z180reg.inc


;----------------------------------------------------------------------

	dseg

intinit:
	ld	hl,ivtab	;
	ld	a,h		;
	ld	i,a		;
	out0	(il),l		;
	im	2

; Let all vectors point to spurious int routines.

	ld	de,sp.int0
	ld	bc,sp.int.len
	ld	a,9
ivt_i1:
	ld	(hl),e
	inc	l
	ld	(hl),d
	inc	l
	ex	de,hl
	add	hl,bc
	ex	de,hl
	dec	a
	jr	nz,ivt_i1
	ret


;--------------------------------------------------------------------
; Spurious interrupt handler

	cseg	; common area
sp.int0:
	ld	a,00h
	jr	sp.i.1
sp.int.len equ	$-sp.int0
	ld	a,01h
	jr	sp.i.1
	ld	a,02h
	jr	sp.i.1
	ld	a,03h
	jr	sp.i.1
	ld	a,04h
	jr	sp.i.1
	ld	a,05h
	jr	sp.i.1
	ld	a,06h
	jr	sp.i.1
	ld	a,07h
	jr	sp.i.1
	ld	a,08h
sp.i.1:
;	out	(80h),a

	add	a,'0'
	ld	(spi$nr),a
	ld	hl,spi$msg
	call	?pmsg
sp.i.2:
	halt
	jr	sp.i.2

spi$msg:
	db	13,10,'Spurious Int: '
spi$nr:	db	'0'
	db	0

;--------------------------------------------------------------------
;
; Get/compute CPU clock
;
;    return:
;	hlde:	CPU frequency (Hz)
;

	dseg

cpu_frq:
	ld	hl,0
	ld	d,h
	ld	e,l
	call	get_tmr
	push	de
	push	hl

; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
;

;	ld	hl,8192		; 147456/18
	ld	hl,(10240-100)*5 ; 184320/18
	ld	de,1
	or	a
dly_lp:
	sbc	hl,de		; 10
	jr	nz,dly_lp	; 6/8  -> 18 cycles

	pop	hl
	pop	de
	call	get_tmr

	ld	b,h
	ld	c,l
	ld	de,036EEh	;18432000/(2**16) * 50
	ld	hl,08000h	;18432000%(2**16) * 50

	ld	a,b
	or	a
	jr	nz,cpuf_div
	ld	a,c
	cp	2
	jr	c,cpuf_done
cpuf_div:
	call	div32_r
cpuf_done:
	ret

;--------------------------------------------------------------------

	dseg
get_tmr:
	push	de
	push	hl
	ld	hl,1*256 + 3		; h = subcommand, l = command
	push	hl
	ld	hl,0
	add	hl,sp
	ld	b,6
	call	msg.sm

	dec	sp
	ld	hl,0
	add	hl,sp
	ld	b,7			; max receive message len
	call	msg.recv

	pop	bc
	inc	sp
	pop	hl
	pop	de
	ret

;--------------------------------------------------------------------

	dseg

fifolst:
	rept 4
	 dw	0
	endm

;--------------------------------------------------------------------

	dseg

bufinit:
	ld	(ix+o.in_idx),0		;reset pointers (empty fifo)
	ld	(ix+o.out_idx),0
	ld	a,(ix+o.id)
	ld	hl,fifolst
	ld	e,a
	ld	d,0
	add	hl,de
	add	hl,de
	push	ix
	pop	de
	cp	4
	jr	nc,bfi_skip

	ld	(hl),e
	inc	hl
	ld	(hl),d

bfi_skip:
	ex	de,hl
	call	hwl2phy			;get phys. address of fifo
	ld	c,a
	ld	a,(ix+o.id)		;fifo id
	or	a			;test if fifo 0
	ret	z

	ld	b,a
	push	bc			;c: bank-addr, b: ignored
	push	hl			;address
	ld	c,0
	push	bc			;c: function, b:subf
	ld	b,5
	ld	h,c
	ld	l,c
	add	hl,sp
	call	msg.sm
	pop	hl
	pop	hl
	pop	hl
	ret

;----------------------------------------------------------------------


	end
Commit	Line	Data
ea5293bb	1
40df51ae L	2	public intinit
	3	public bufinit
	4	public cpu_frq
	5	public get_tmr
ea5293bb	6
40df51ae	7	public fifolst
ea5293bb	8
50f3b8f0	9	extrn div32_r,?pmsg
f80331a6	10	extrn msg.sm,msg.recv,hwl2phy
ea5293bb L	11
	12	include config.inc
	13	include z180reg.inc
	14
43bb4ff6	15
ea5293bb L	16	;----------------------------------------------------------------------
	17
	18	dseg
	19
	20	intinit:
	21	ld hl,ivtab ;
	22	ld a,h ;
	23	ld i,a ;
	24	out0 (il),l ;
	25	im 2
	26
	27	; Let all vectors point to spurious int routines.
	28
	29	ld de,sp.int0
	30	ld bc,sp.int.len
	31	ld a,9
	32	ivt_i1:
	33	ld (hl),e
	34	inc l
	35	ld (hl),d
	36	inc l
	37	ex de,hl
	38	add hl,bc
	39	ex de,hl
	40	dec a
	41	jr nz,ivt_i1
	42	ret
	43
	44
	45	;--------------------------------------------------------------------
	46	; Spurious interrupt handler
	47
	48	cseg ; common area
	49	sp.int0:
	50	ld a,00h
	51	jr sp.i.1
	52	sp.int.len equ $-sp.int0
	53	ld a,01h
	54	jr sp.i.1
	55	ld a,02h
	56	jr sp.i.1
	57	ld a,03h
	58	jr sp.i.1
	59	ld a,04h
	60	jr sp.i.1
	61	ld a,05h
	62	jr sp.i.1
	63	ld a,06h
	64	jr sp.i.1
	65	ld a,07h
	66	jr sp.i.1
	67	ld a,08h
	68	sp.i.1:
	69	; out (80h),a
	70
	71	add a,'0'
	72	ld (spi$nr),a
	73	ld hl,spi$msg
	74	call ?pmsg
	75	sp.i.2:
	76	halt
	77	jr sp.i.2
	78
	79	spi$msg:
80	db 13,10,'Spurious Int: '
81	spi$nr: db '0'
82	db 0
83
f80331a6 L	84	;--------------------------------------------------------------------
	85	;
	86	; Get/compute CPU clock
	87	;
	88	; return:
	89	; hlde: CPU frequency (Hz)
	90	;
	91
	92	dseg
	93
	94	cpu_frq:
8e627f7e L	95	ld hl,0
	96	ld d,h
	97	ld e,l
40df51ae	98	call get_tmr
8e627f7e	99	push de
43bb4ff6	100	push hl
f80331a6 L	101
	102	; delay ~8ms @ 18.432MHz --> 147456 clock cycles
	103	; delay ~10ms @ 18.432MHz --> 184320 clock cycles
	104	;
	105
	106	; ld hl,8192 ; 147456/18
50f3b8f0	107	ld hl,(10240-100)*5 ; 184320/18
f80331a6 L	108	ld de,1
	109	or a
	110	dly_lp:
	111	sbc hl,de ; 10
50f3b8f0	112	jr nz,dly_lp ; 6/8 -> 18 cycles
f80331a6	113
8e627f7e	114	pop hl
43bb4ff6	115	pop de
40df51ae	116	call get_tmr
f80331a6	117
43bb4ff6 L	118	ld b,h
43bb4ff6 L	119	ld c,l
50f3b8f0 L	120	ld de,036EEh ;18432000/(2*16) 50
50f3b8f0 L	121	ld hl,08000h ;18432000%(2*16) 50
f80331a6 L	122
	123	ld a,b
	124	or a
	125	jr nz,cpuf_div
	126	ld a,c
	127	cp 2
	128	jr c,cpuf_done
	129	cpuf_div:
43bb4ff6	130	call div32_r
f80331a6 L	131	cpuf_done:
	132	ret
	133
	134	;--------------------------------------------------------------------
	135
40df51ae L	136	dseg
40df51ae L	137	get_tmr:
8e627f7e	138	push de
43bb4ff6	139	push hl
40df51ae	140	ld hl,1*256 + 3 ; h = subcommand, l = command
8e627f7e L	141	push hl
	142	ld hl,0
	143	add hl,sp
	144	ld b,6
f80331a6 L	145	call msg.sm
f80331a6 L	146
8e627f7e L	147	dec sp
	148	ld hl,0
	149	add hl,sp
	150	ld b,7 ; max receive message len
	151	call msg.recv
f80331a6	152
8e627f7e L	153	pop bc
8e627f7e L	154	inc sp
8e627f7e	155	pop hl
43bb4ff6	156	pop de
8e627f7e	157	ret
ea5293bb L	158
	159	;--------------------------------------------------------------------
	160
1e1c17d3	161	dseg
ea5293bb L	162
	163	fifolst:
	164	rept 4
	165	dw 0
ea5293bb L	166	endm
	167
	168	;--------------------------------------------------------------------
	169
	170	dseg
	171
	172	bufinit:
40df51ae L	173	ld (ix+o.in_idx),0 ;reset pointers (empty fifo)
40df51ae L	174	ld (ix+o.out_idx),0
ea5293bb	175	ld a,(ix+o.id)
ea5293bb L	176	ld hl,fifolst
	177	ld e,a
	178	ld d,0
	179	add hl,de
	180	add hl,de
ea5293bb L	181	push ix
ea5293bb L	182	pop de
40df51ae L	183	cp 4
	184	jr nc,bfi_skip
	185
ea5293bb L	186	ld (hl),e
	187	inc hl
	188	ld (hl),d
ea5293bb	189
40df51ae	190	bfi_skip:
ea5293bb	191	ex de,hl
40df51ae	192	call hwl2phy ;get phys. address of fifo
ea5293bb L	193	ld c,a
	194	ld a,(ix+o.id) ;fifo id
	195	or a ;test if fifo 0
40df51ae	196	ret z
ea5293bb	197
40df51ae L	198	ld b,a
	199	push bc ;c: bank-addr, b: ignored
	200	push hl ;address
	201	ld c,0
	202	push bc ;c: function, b:subf
	203	ld b,5
	204	ld h,c
	205	ld l,c
	206	add hl,sp
ea5293bb	207	call msg.sm
40df51ae L	208	pop hl
	209	pop hl
	210	pop hl
ea5293bb L	211	ret
ea5293bb L	212
ea5293bb L	213	;----------------------------------------------------------------------
	214
	215
	216	end