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Commit | Line | Data |
---|---|---|
fcf62661 L |
1 | \r |
2 | FALSE equ 0\r | |
3 | TRUE equ NOT FALSE\r | |
4 | \r | |
5 | \r | |
fcf62661 L |
6 | banked equ true\r |
7 | \r | |
8 | ;-----------------------------------------------------\r | |
9 | ; CPU and BANKING types\r | |
10 | \r | |
11 | \r | |
12 | CPU_Z180 equ TRUE\r | |
13 | CPU_Z80 equ FALSE\r | |
14 | \r | |
15 | ROMSYS equ FALSE\r | |
16 | \r | |
17 | AVRCLK equ 18432 ;[KHz]\r | |
18 | \r | |
19 | if CPU_Z180\r | |
20 | \r | |
21 | ;-----------------------------------------------------\r | |
22 | ;FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]\r | |
23 | ;PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)\r | |
24 | \r | |
25 | ;----------------------------------------------------------------------\r | |
26 | ; Baudrate Generator for x16 clock mode:\r | |
27 | ; TC = (f PHI / (32 * baudrate)) - 2\r | |
28 | ;\r | |
29 | ; PHI [MHz]: 9.216 18.432\r | |
30 | ; baudrate TC TC\r | |
31 | ; ----------------------\r | |
32 | ; 115200 - 3\r | |
33 | ; 57600 3 8\r | |
34 | ; 38400 - 13\r | |
35 | ; 19200 13 28\r | |
36 | ; 9600 28 58\r | |
37 | \r | |
38 | \r | |
39 | ;-----------------------------------------------------\r | |
40 | ; Programmable Reload Timer (PRT)\r | |
41 | \r | |
42 | PRT_PRE equ 20 ;PRT prescaler\r | |
43 | \r | |
44 | ;-----------------------------------------------------\r | |
45 | ; MMU\r | |
46 | \r | |
47 | COMMON_SIZE equ 4*1024 ;Common Area size in bytes\r | |
48 | ;must be multiple of 4K\r | |
49 | if (COMMON_SIZE mod 1000h)\r | |
50 | .printx COMMON_SIZE not multiple of 4K!\r | |
51 | end ;stop assembly\r | |
52 | endif\r | |
53 | CMN_SIZE equ COMMON_SIZE/1000h ;4K units\r | |
54 | BNK_SIZE equ 64/4 - CMN_SIZE ;bank size (4K units)\r | |
55 | BANKS equ (512/4 - CMN_SIZE)/BNK_SIZE ;max nr. of banks\r | |
56 | \r | |
57 | ; Logical address space, CBAR values\r | |
58 | \r | |
59 | CA equ 10h - CMN_SIZE ;common area start (64K - common size)\r | |
60 | BA equ 0 ;banked area start\r | |
61 | \r | |
62 | if 0\r | |
63 | \r | |
64 | SYS$CBR equ 0\r | |
65 | SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r | |
66 | USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r | |
67 | \r | |
68 | endif\r | |
69 | if 1\r | |
70 | \r | |
71 | SYS$CBR equ BNK_SIZE\r | |
72 | SYS$CBAR equ CA*16 + CA ;CBAR in system mode\r | |
73 | USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)\r | |
74 | \r | |
75 | endif\r | |
76 | \r | |
77 | \r | |
78 | ;-----------------------------------------------------\r | |
79 | \r | |
80 | CREFSH equ 0 ;Refresh rate register (disable refresh)\r | |
81 | CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States\r | |
82 | PHI_X2 equ 0 ;set to M_X2CM to enable the clock doubler\r | |
83 | \r | |
84 | endif ;CPU_Z180\r | |
85 | if CPU_Z80\r | |
86 | \r | |
87 | PHI equ AVRCLK/5 ;CPU frequency [KHz]\r | |
88 | BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]\r | |
89 | ;BDCLK16 equ\r | |
90 | \r | |
91 | SIOAD EQU 0bch\r | |
92 | SIOAC EQU 0bdh\r | |
93 | SIOBD EQU 0beh\r | |
94 | SIOBC EQU 0bfh\r | |
95 | \r | |
96 | CTC0 EQU 0f4h\r | |
97 | CTC1 EQU 0f5h\r | |
98 | CTC2 EQU 0f6h\r | |
99 | CTC3 EQU 0f7h\r | |
100 | \r | |
101 | ;\r | |
102 | ; Init Serial I/O for console input and output (SIO-A)\r | |
103 | ;\r | |
104 | ; Baudrate clock: 1843200 Hz (Bus connector pin A17)\r | |
105 | ;\r | |
106 | ; Baudrate Divider SIO CTC\r | |
107 | ; ---------------------------------\r | |
108 | ; 115200 16 16 1\r | |
109 | ; 57600 32 16 2\r | |
110 | ; 38400 48 16 3\r | |
111 | ; 19200 96 16 6\r | |
112 | ; 9600 192 16 12\r | |
113 | ; 4800 384 16 24\r | |
114 | ; 2400 768 16 48\r | |
115 | ; 1200 1536 16 96\r | |
116 | ; 600 3072 16 192\r | |
117 | ; 300 6144 64 92\r | |
118 | \r | |
119 | endif ; CPU_Z80\r | |
120 | \r | |
121 | if ROMSYS\r | |
122 | c$rom equ 0a5h\r | |
123 | ROM_EN equ 0C0h\r | |
124 | ROM_DIS equ ROMEN+1\r | |
125 | if CPU_Z180\r | |
126 | CWAITROM equ 2 shl MWI0\r | |
127 | endif\r | |
128 | endif\r | |
129 | \r | |
130 | \r | |
131 | DDTZRSTVEC equ 030h ;DDTZ Restart vector (breakpoints)\r | |
132 | \r | |
133 | INIDONE equ 03Fh ;CP/M skip hw init, if this address\r | |
134 | INIDONEVAL equ 080h ; is set to this value.\r | |
135 | \r | |
136 | mtx.fifo_len equ 64 ;Message transfer fifos\r | |
137 | mtx.fifo_id equ 0 ; This *must* have #0\r | |
138 | mrx.fifo_len equ 64\r | |
139 | mrx.fifo_id equ 1\r | |
140 | \r | |
141 | ci.fifo_len equ 32 ;AVRCON (USB0) Character I/O via AVR\r | |
142 | ci.fifo_id equ 2\r | |
143 | co.fifo_len equ 32\r | |
144 | co.fifo_id equ 3\r | |
145 | \r | |
146 | s0.rx_len equ 128 ;Serial 0 (ASCI0) buffers\r | |
147 | s0.rx_id equ 4 ;\r | |
148 | s0.tx_len equ 128 ;\r | |
149 | s0.tx_id equ 5 ;\r | |
150 | \r | |
151 | s1.rx_len equ 128 ;Serial 1 (ASCI1) buffers\r | |
152 | s1.rx_id equ 6 ;\r | |
153 | s1.tx_len equ 128 ;\r | |
154 | s1.tx_id equ 7 ;\r | |
155 | \r | |
156 | AVRINT5 equ 4Fh\r | |
157 | AVRINT6 equ 5Fh\r | |
158 | ;PMSG equ 80h\r | |
159 | \r | |
4fc939ea L |
160 | IDEBASE equ 60h\r |
161 | \r | |
fcf62661 L |
162 | ;-----------------------------------------------------\r |
163 | ; Definition of (logical) top 2 memory pages\r | |
164 | \r | |
165 | sysram_start equ 0FE00h\r | |
166 | bs$stack$size equ 80\r | |
167 | \r | |
168 | isvsw_loc equ 0FEE0h\r | |
169 | \r | |
170 | ivtab equ 0ffc0h ;int vector table\r | |
171 | iv2tab equ ivtab + 2*9\r | |
172 | \r | |
173 | \r | |
174 | \r | |
175 | ;-----------------------------------------------------\r | |
176 | \r | |
177 | o.id equ -4\r | |
178 | o.mask equ -3\r | |
179 | o.in_idx equ -2\r | |
180 | o.out_idx equ -1\r | |
181 | \r | |
182 | .lall\r | |
183 | \r | |
184 | mkbuf macro id,name,size\r | |
185 | if ((size AND (size-1)) NE 0) OR (size GT 256)\r | |
186 | .printx Error: buffer ^size must be power of 2 and in range 0..256!\r | |
187 | name&.mask equ ;wrong size error\r | |
188 | else\r | |
189 | db id\r | |
190 | db size-1\r | |
191 | ds 2\r | |
192 | name:: ds size\r | |
193 | name&.mask equ low (size-1)\r | |
194 | if size ne 0\r | |
195 | name&.end equ $-1\r | |
196 | name&.len equ size\r | |
197 | name&.id equ id\r | |
198 | endif\r | |
199 | endif\r | |
200 | endm\r | |
201 | \r | |
202 | ;-----------------------------------------------------\r | |
203 | \r | |
204 | inidat macro\r | |
205 | cseg\r | |
206 | ??ps.a defl $\r | |
207 | endm\r | |
208 | \r | |
209 | inidate macro\r | |
210 | ??ps.len defl $ - ??ps.a\r | |
211 | dseg\r | |
212 | ds ??ps.len\r | |
213 | endm\r | |
214 | \r | |
215 | ;-----------------------------------------------------\r | |
216 | \r | |
217 | b0call macro address\r | |
218 | call _b0call\r | |
219 | dw address\r | |
220 | endm\r |